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36// Copyright 2009-2014 Sandia Coporation.  Under the terms
37// of Contract DE-AC04-94AL85000 with Sandia Corporation, the U.S.
38// Government retains certain rights in this software.
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40// Copyright (c) 2009-2014, Sandia Corporation
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42//
43// For license information, see the LICENSE file in the current directory.
44
45#ifndef EXT_SST_EXTSLAVE_HH
46#define EXT_SST_EXTSLAVE_HH
47
48#include <core/interfaces/simpleMem.h>
49
50#include <sim/sim_object.hh>
51#include <mem/packet.hh>
52#include <mem/request.hh>
53#include <mem/external_slave.hh>
54
55namespace SST {
56class Link;
57class Event;
58class MemEvent;
59namespace gem5 {
60
61class gem5Component;
62
63class ExtSlave : public ExternalSlave::Port {
64  public:
65    const std::string name;
66
67    bool
68    recvTimingSnoopResp(PacketPtr packet)
69    {
70        fatal("recvTimingSnoopResp unimplemented");
71        return false;
72    }
73
74    bool recvTimingReq(PacketPtr packet);
75
76    void recvFunctional(PacketPtr packet);
77
78    void recvRespRetry();
79
80    Tick
81    recvAtomic(PacketPtr packet)
82    {
83        fatal("recvAtomic unimplemented");
84    }
85
86    enum Phase { CONSTRUCTION, INIT, RUN };
87
88    gem5Component *comp;
89    Output &out;
90    Phase simPhase;
91
92    std::list<MemEvent*>* initPackets;
93    Link* link;
94    std::list<PacketPtr> respQ;
95    bool blocked() { return !respQ.empty(); }
96
97    typedef std::map<Event::id_type, ::Packet*> PacketMap_t;
98    PacketMap_t PacketMap; // SST Event id -> gem5 Packet*
99
100public:
101    ExtSlave(gem5Component*, Output&, ExternalSlave&, std::string&);
102    void init(unsigned phase);
103
104    void
105    setup()
106    {
107        simPhase = RUN;
108    }
109
110    void handleEvent(Event*);
111};
112
113}
114}
115
116#endif
117