110779SCurtis.Dunham@arm.com// Copyright (c) 2015 ARM Limited 210779SCurtis.Dunham@arm.com// All rights reserved. 310779SCurtis.Dunham@arm.com// 410779SCurtis.Dunham@arm.com// The license below extends only to copyright in the software and shall 510779SCurtis.Dunham@arm.com// not be construed as granting a license to any other intellectual 610779SCurtis.Dunham@arm.com// property including but not limited to intellectual property relating 710779SCurtis.Dunham@arm.com// to a hardware implementation of the functionality of the software 810779SCurtis.Dunham@arm.com// licensed hereunder. You may use the software subject to the license 910779SCurtis.Dunham@arm.com// terms below provided that you ensure that this notice is replicated 1010779SCurtis.Dunham@arm.com// unmodified and in its entirety in all distributions of the software, 1110779SCurtis.Dunham@arm.com// modified or unmodified, in source code or in binary form. 1210779SCurtis.Dunham@arm.com// 1310779SCurtis.Dunham@arm.com// Redistribution and use in source and binary forms, with or without 1410779SCurtis.Dunham@arm.com// modification, are permitted provided that the following conditions are 1510779SCurtis.Dunham@arm.com// met: redistributions of source code must retain the above copyright 1610779SCurtis.Dunham@arm.com// notice, this list of conditions and the following disclaimer; 1710779SCurtis.Dunham@arm.com// redistributions in binary form must reproduce the above copyright 1810779SCurtis.Dunham@arm.com// notice, this list of conditions and the following disclaimer in the 1910779SCurtis.Dunham@arm.com// documentation and/or other materials provided with the distribution; 2010779SCurtis.Dunham@arm.com// neither the name of the copyright holders nor the names of its 2110779SCurtis.Dunham@arm.com// contributors may be used to endorse or promote products derived from 2210779SCurtis.Dunham@arm.com// this software without specific prior written permission. 2310779SCurtis.Dunham@arm.com// 2410779SCurtis.Dunham@arm.com// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2510779SCurtis.Dunham@arm.com// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2610779SCurtis.Dunham@arm.com// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2710779SCurtis.Dunham@arm.com// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2810779SCurtis.Dunham@arm.com// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2910779SCurtis.Dunham@arm.com// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3010779SCurtis.Dunham@arm.com// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3110779SCurtis.Dunham@arm.com// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3210779SCurtis.Dunham@arm.com// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3310779SCurtis.Dunham@arm.com// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3410779SCurtis.Dunham@arm.com// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3510779SCurtis.Dunham@arm.com 3610779SCurtis.Dunham@arm.com// Copyright 2009-2014 Sandia Coporation. Under the terms 3710779SCurtis.Dunham@arm.com// of Contract DE-AC04-94AL85000 with Sandia Corporation, the U.S. 3810779SCurtis.Dunham@arm.com// Government retains certain rights in this software. 3910779SCurtis.Dunham@arm.com// 4010779SCurtis.Dunham@arm.com// Copyright (c) 2009-2014, Sandia Corporation 4110779SCurtis.Dunham@arm.com// All rights reserved. 4210779SCurtis.Dunham@arm.com// 4310779SCurtis.Dunham@arm.com// For license information, see the LICENSE file in the current directory. 4410779SCurtis.Dunham@arm.com 4510779SCurtis.Dunham@arm.com#ifndef EXT_SST_EXTMASTER_HH 4610779SCurtis.Dunham@arm.com#define EXT_SST_EXTMASTER_HH 4710779SCurtis.Dunham@arm.com 4810779SCurtis.Dunham@arm.com#include <list> 4910779SCurtis.Dunham@arm.com#include <set> 5010779SCurtis.Dunham@arm.com 5111618SCurtis.Dunham@arm.com#include <core/component.h> 5211618SCurtis.Dunham@arm.com#include <elements/memHierarchy/memEvent.h> 5310779SCurtis.Dunham@arm.com 5410779SCurtis.Dunham@arm.com#include <sim/sim_object.hh> 5510779SCurtis.Dunham@arm.com#include <mem/packet.hh> 5610779SCurtis.Dunham@arm.com#include <mem/request.hh> 5710779SCurtis.Dunham@arm.com#include <mem/external_master.hh> 5810779SCurtis.Dunham@arm.com 5910779SCurtis.Dunham@arm.comnamespace SST { 6010779SCurtis.Dunham@arm.com 6110779SCurtis.Dunham@arm.comusing MemHierarchy::MemEvent; 6210779SCurtis.Dunham@arm.comclass Link; 6310779SCurtis.Dunham@arm.comclass Event; 6410779SCurtis.Dunham@arm.com 6510779SCurtis.Dunham@arm.comnamespace MemHierarchy { 6610779SCurtis.Dunham@arm.comclass MemNIC; 6710779SCurtis.Dunham@arm.com} 6810779SCurtis.Dunham@arm.com 6910779SCurtis.Dunham@arm.comnamespace gem5 { 7010779SCurtis.Dunham@arm.com 7110779SCurtis.Dunham@arm.comclass gem5Component; 7210779SCurtis.Dunham@arm.com 7310779SCurtis.Dunham@arm.comclass ExtMaster : public ExternalMaster::Port { 7410779SCurtis.Dunham@arm.com 7510779SCurtis.Dunham@arm.com enum Phase { CONSTRUCTION, INIT, RUN }; 7610779SCurtis.Dunham@arm.com 7710779SCurtis.Dunham@arm.com Output& out; 7810779SCurtis.Dunham@arm.com const ExternalMaster& port; 7910779SCurtis.Dunham@arm.com Phase simPhase; 8010779SCurtis.Dunham@arm.com 8110779SCurtis.Dunham@arm.com gem5Component *const gem5; 8210779SCurtis.Dunham@arm.com const std::string name; 8310779SCurtis.Dunham@arm.com std::list<PacketPtr> sendQ; 8410779SCurtis.Dunham@arm.com bool blocked() { return !sendQ.empty(); } 8510779SCurtis.Dunham@arm.com 8610779SCurtis.Dunham@arm.com MemHierarchy::MemNIC * nic; 8710779SCurtis.Dunham@arm.com 8810779SCurtis.Dunham@arm.com struct SenderState : public Packet::SenderState 8910779SCurtis.Dunham@arm.com { 9010779SCurtis.Dunham@arm.com MemEvent *event; 9110779SCurtis.Dunham@arm.com SenderState(MemEvent* e) : event(e) {} 9210779SCurtis.Dunham@arm.com }; 9310779SCurtis.Dunham@arm.com 9410779SCurtis.Dunham@arm.com std::set<AddrRange> ranges; 9510779SCurtis.Dunham@arm.com 9610779SCurtis.Dunham@arm.compublic: 9710779SCurtis.Dunham@arm.com bool recvTimingResp(PacketPtr); 9810779SCurtis.Dunham@arm.com void recvReqRetry(); 9910779SCurtis.Dunham@arm.com 10010779SCurtis.Dunham@arm.com ExtMaster(gem5Component*, Output&, ExternalMaster&, std::string&); 10110779SCurtis.Dunham@arm.com void init(unsigned phase); 10210779SCurtis.Dunham@arm.com void setup(); 10310779SCurtis.Dunham@arm.com void finish(); 10410779SCurtis.Dunham@arm.com 10510779SCurtis.Dunham@arm.com void clock(); 10610779SCurtis.Dunham@arm.com 10710779SCurtis.Dunham@arm.com // receive Requests from SST bound for a gem5 slave; 10810779SCurtis.Dunham@arm.com // this module is "external" from gem5's perspective, thus ExternalMaster. 10910779SCurtis.Dunham@arm.com void handleEvent(SST::Event*); 11010779SCurtis.Dunham@arm.com 11110779SCurtis.Dunham@arm.comprotected: 11210779SCurtis.Dunham@arm.com virtual void recvRangeChange(); 11310779SCurtis.Dunham@arm.com}; 11410779SCurtis.Dunham@arm.com 11510779SCurtis.Dunham@arm.com} // namespace gem5 11610779SCurtis.Dunham@arm.com} // namespace SST 11710779SCurtis.Dunham@arm.com 11810779SCurtis.Dunham@arm.com#endif 119