Searched refs:IntRegClass (Results 1 - 18 of 18) sorted by relevance
| /gem5/src/arch/x86/ |
| H A D | isa.hh | 77 case IntRegClass:
78 return RegId(IntRegClass, flattenIntIndex(regId.index()));
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| /gem5/src/cpu/ |
| H A D | reg_class.hh | 57 IntRegClass, ///< Integer register enumerator in enum:RegClass
77 * index 3 is represented by Regid(IntRegClass, 3).
91 RegId() : RegId(IntRegClass, 0) {}
143 return ((regClass == IntRegClass && regIdx == TheISA::ZeroReg) ||
149 bool isIntReg() const { return regClass == IntRegClass; }
188 case IntRegClass:
236 explicit PhysRegId() : RegId(IntRegClass, -1), flatIdx(-1),
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| /gem5/src/arch/sparc/ |
| H A D | isa.hh | 196 case IntRegClass:
197 return RegId(IntRegClass, flattenIntIndex(regId.index()));
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| /gem5/src/cpu/o3/ |
| H A D | free_list.hh | 272 case IntRegClass:
305 case IntRegClass:
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| H A D | rename_map.cc | 56 : freeList(NULL), zeroReg(IntRegClass,0)
70 zeroReg = RegId(IntRegClass, _zeroReg);
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| H A D | rename_map.hh | 232 case IntRegClass:
271 case IntRegClass:
313 case IntRegClass:
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| H A D | thread_context.hh | 193 return readIntRegFlat(flattenRegId(RegId(IntRegClass,
199 return readIntRegFlat(flattenRegId(RegId(IntRegClass,
315 setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val);
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| H A D | regfile.cc | 89 intRegIds.emplace_back(IntRegClass, phys_reg, flat_reg_idx++);
203 case IntRegClass:
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| H A D | cpu.cc | 248 renameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg);
249 commitRenameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg);
785 for (RegId reg_id(IntRegClass, 0); reg_id.index() < TheISA::NumIntRegs;
1320 RegId(IntRegClass, reg_idx));
1403 RegId(IntRegClass, reg_idx));
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| H A D | dyn_inst.hh | 218 case IntRegClass:
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| H A D | rename_impl.hh | 1080 case IntRegClass:
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| /gem5/src/arch/mips/ |
| H A D | mt.hh | 66 case IntRegClass:
90 case IntRegClass:
197 setRegOtherThread(tc, RegId(IntRegClass, Rd_bits), Rt, tid);
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| /gem5/src/arch/x86/insts/ |
| H A D | static_inst.hh | 66 return IntRegClass;
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| /gem5/src/cpu/minor/ |
| H A D | scoreboard.cc | 61 case IntRegClass:
147 inst->flatDestRegIdx[dest_index] = RegId(IntRegClass,
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| H A D | dyn_inst.cc | 167 case IntRegClass:
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| /gem5/src/arch/arm/tracers/ |
| H A D | tarmac_record.cc | 175 case IntRegClass:
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| /gem5/src/cpu/checker/ |
| H A D | cpu_impl.hh | 606 case IntRegClass:
641 case IntRegClass:
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| /gem5/src/arch/arm/ |
| H A D | isa.hh | 452 case IntRegClass:
453 return RegId(IntRegClass, flattenIntIndex(regId.index()));
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