Searched refs:ISA (Results 1 - 25 of 37) sorted by relevance

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/gem5/src/arch/power/
H A Disa.cc47 ISA::ISA(Params *p) function in class:PowerISA::ISA
54 ISA::params() const
61 PowerISA::ISA *
64 return new PowerISA::ISA(this);
H A Ddecoder.hh41 class ISA;
50 Decoder(ISA* isa = nullptr) : instDone(false)
H A Disa.hh50 class ISA : public SimObject class in namespace:PowerISA
142 ISA(Params *p);
/gem5/src/arch/generic/
H A Dtraits.hh48 /** Helper structure to get the vector register mode for a given ISA.
49 * This way we implement a default 'full' mode, and only those ISA that care
51 * appropriate member of the ISA.
53 template <typename ISA>
56 static Enums::VecRegRenameMode init(const ISA*) { return Enums::Full; } argument
63 * Compare the initial rename mode of two instances of the ISA.
66 static bool equalsInit(const ISA*, const ISA*) { return true; } argument
/gem5/src/arch/arm/
H A Disa_device.hh51 class ISA;
66 virtual void setISA(ISA *isa);
86 ISA *isa;
93 * is not present. For example, the ISA code uses it to avoid having
H A Disa_device.cc53 BaseISADevice::setISA(ISA *_isa)
H A Ddecoder.hh58 class ISA;
99 Decoder(ISA* isa = nullptr);
181 * @note The implementation of this method is generated by the ISA
H A Disa.cc61 ISA::ISA(Params *p) function in class:ArmISA::ISA
79 // Give all ISA devices a pointer to this ISA
119 std::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS);
122 ISA::params() const
128 ISA::clear()
215 ISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst)
267 ISA
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H A Disa.hh66 class ISA : public SimObject class in namespace:ArmISA
76 /** Dummy device for to handle non-existing ISA devices */
79 // PMU belonging to this ISA
82 // Generic timer interface belonging to this ISA
85 // GICv3 CPU interface belonging to this ISA
758 ISA(Params *p);
763 struct RenameMode<ArmISA::ISA>
766 init(const ArmISA::ISA* isa)
782 equalsInit(const ArmISA::ISA* isa1, const ArmISA::ISA* isa
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/gem5/src/arch/alpha/
H A Disa.cc43 ISA::ISA(Params *p) function in class:AlphaISA::ISA
51 ISA::params() const
57 ISA::serialize(CheckpointOut &cp) const
67 ISA::unserialize(CheckpointIn &cp)
78 ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
98 ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
117 ISA::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
143 ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc, ThreadID tid)
169 AlphaISA::ISA *
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H A Ddecoder.hh42 class ISA;
51 Decoder(ISA* isa = nullptr) : instDone(false)
H A Disa.hh53 class ISA : public SimObject class in namespace:AlphaISA
145 ISA(Params *p);
/gem5/src/arch/riscv/
H A Disa.cc48 ISA::ISA(Params *p) : SimObject(p) function in class:RiscvISA::ISA
55 ISA::params() const
60 void ISA::clear()
76 ISA::hpmCounterEnabled(int misc_reg) const
99 ISA::readMiscRegNoEffect(int misc_reg) const
112 ISA::readMiscReg(int misc_reg, ThreadContext *tc)
169 ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
180 ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
201 RiscvISA::ISA *
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H A Ddecoder.hh47 class ISA;
62 Decoder(ISA* isa=nullptr) { reset(); }
H A Disa.hh65 class ISA : public SimObject class in namespace:RiscvISA
98 ISA(Params *p);
/gem5/src/arch/mips/
H A Ddecoder.hh43 class ISA;
52 Decoder(ISA* isa = nullptr) : instDone(false)
H A Disa.hh52 class ISA : public SimObject class in namespace:MipsISA
56 typedef ISA CP0;
61 // Number of threads and vpes an individual ISA state can handle
139 ISA(Params *p);
H A Disa.cc46 ISA::miscRegNames[NumMiscRegs] =
92 ISA::ISA(Params *p) function in class:MipsISA::ISA
146 ISA::params() const
152 ISA::clear()
165 ISA::configCP()
414 ISA::getVPENum(ThreadID tid) const
421 ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
435 ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
448 ISA
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/gem5/src/arch/sparc/
H A Disa.hh50 class ISA : public SimObject class in namespace:SparcISA
131 typedef CpuEventWrapper<ISA,
132 &ISA::processTickCompare> TickCompareEvent;
135 typedef CpuEventWrapper<ISA,
136 &ISA::processSTickCompare> STickCompareEvent;
139 typedef CpuEventWrapper<ISA,
140 &ISA::processHSTickCompare> HSTickCompareEvent;
260 ISA(Params *p);
H A Ddecoder.hh42 class ISA;
52 Decoder(ISA* isa = nullptr) : instDone(false), asi(0)
H A Disa.cc63 ISA::ISA(Params *p) function in class:SparcISA::ISA
74 ISA::params() const
80 ISA::reloadRegMap()
94 ISA::installWindow(int cwp, int offset)
104 ISA::installGlobals(int gl, int offset)
114 ISA::clear()
173 panic("Tick comparison event active when clearing the ISA object.\n");
177 ISA::readMiscRegNoEffect(int miscReg) const
338 ISA
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H A Dua2005.cc47 ISA::checkSoftInt(ThreadContext *tc)
92 ISA::setFSReg(int miscReg, RegVal val, ThreadContext *tc)
247 ISA::readFSReg(int miscReg, ThreadContext * tc)
321 ISA::processTickCompare(ThreadContext *tc)
327 ISA::processSTickCompare(ThreadContext *tc)
351 ISA::processHSTickCompare(ThreadContext *tc)
/gem5/src/arch/x86/
H A Disa.cc44 ISA::updateHandyM5Reg(Efer efer, CR0 cr0,
106 ISA::clear()
115 ISA::ISA(Params *p) function in class:X86ISA::ISA
122 ISA::params() const
128 ISA::readMiscRegNoEffect(int miscReg) const
139 ISA::readMiscReg(int miscReg, ThreadContext * tc)
155 ISA::setMiscRegNoEffect(int miscReg, RegVal val)
197 ISA::setMiscReg(int miscReg, RegVal val, ThreadContext * tc)
398 ISA
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H A Disa.hh51 class ISA : public SimObject class in namespace:X86ISA
64 ISA(Params *p);
/gem5/src/cpu/
H A Dsimple_thread.cc78 BaseTLB *_dtb, TheISA::ISA *_isa)
89 TheISA::ISA *_isa, bool use_kernel_stats)

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