Searched refs:FloatRegClass (Results 1 - 17 of 17) sorted by relevance

/gem5/src/arch/x86/
H A Disa.hh79 case FloatRegClass:
80 return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
/gem5/src/cpu/
H A Dreg_class.hh58 FloatRegClass, ///< Floating-point register enumerator in enum:RegClass
144 (THE_ISA == ALPHA_ISA && regClass == FloatRegClass &&
152 bool isFloatReg() const { return regClass == FloatRegClass; }
189 case FloatRegClass:
/gem5/src/arch/sparc/
H A Disa.hh198 case FloatRegClass:
199 return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
/gem5/src/cpu/o3/
H A Dfree_list.hh275 case FloatRegClass:
308 case FloatRegClass:
H A Drename_map.hh234 case FloatRegClass:
274 case FloatRegClass:
317 case FloatRegClass:
H A Dregfile.cc95 floatRegIds.emplace_back(FloatRegClass, phys_reg, flat_reg_idx++);
205 case FloatRegClass:
H A Dthread_context.hh206 return readFloatRegFlat(flattenRegId(RegId(FloatRegClass,
321 setFloatRegFlat(flattenRegId(RegId(FloatRegClass,
H A Dcpu.cc254 renameMap[tid].setEntry(RegId(FloatRegClass, ridx), phys_reg);
256 RegId(FloatRegClass, ridx), phys_reg);
793 for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs;
1331 RegId(FloatRegClass, reg_idx));
1414 RegId(FloatRegClass, reg_idx));
H A Ddyn_inst.hh222 case FloatRegClass:
H A Drename_impl.hh1083 case FloatRegClass:
/gem5/src/arch/x86/insts/
H A Dstatic_inst.hh68 return FloatRegClass;
/gem5/src/cpu/minor/
H A Ddyn_inst.cc157 case FloatRegClass:
H A Dscoreboard.cc65 case FloatRegClass:
/gem5/src/arch/mips/
H A Dmt.hh69 case FloatRegClass:
93 case FloatRegClass:
/gem5/src/arch/arm/tracers/
H A Dtarmac_record.cc172 case FloatRegClass:
/gem5/src/cpu/checker/
H A Dcpu_impl.hh610 case FloatRegClass:
645 case FloatRegClass:
/gem5/src/arch/arm/
H A Disa.hh454 case FloatRegClass:
455 return RegId(FloatRegClass, flattenFloatIndex(regId.index()));

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