Searched refs:Bridge (Results 1 - 9 of 9) sorted by relevance

/gem5/src/mem/
H A Dbridge.cc54 #include "debug/Bridge.hh"
55 #include "params/Bridge.hh"
57 Bridge::BridgeSlavePort::BridgeSlavePort(const std::string& _name,
58 Bridge& _bridge,
69 Bridge::BridgeMasterPort::BridgeMasterPort(const std::string& _name,
70 Bridge& _bridge,
79 Bridge::Bridge(Params *p) function in class:Bridge
89 Bridge::getPort(const std::string &if_name, PortID idx)
101 Bridge
[all...]
H A Dbridge.hh58 #include "params/Bridge.hh"
74 class Bridge : public ClockedObject class in inherits:ClockedObject
109 Bridge& bridge;
174 BridgeSlavePort(const std::string& _name, Bridge& _bridge,
229 Bridge& bridge;
271 BridgeMasterPort(const std::string& _name, Bridge& _bridge,
327 Bridge(Params *p);
H A DBridge.py45 class Bridge(ClockedObject): class in inherits:ClockedObject
46 type = 'Bridge'
/gem5/src/gpu-compute/
H A DGPU.py44 from m5.objects.Bridge import Bridge
132 ldsBus = Bridge() # the bridge between the CU and its LDS
/gem5/tests/configs/
H A Dtwosys-tsunami-simple-atomic.py64 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
96 drive_sys.iobridge = Bridge(delay='50ns', ranges = drive_sys.mem_ranges)
/gem5/configs/common/
H A DHMC.py69 # SerialLink is a simple variation of the Bridge class, with the ability to
428 # then it will be forward to correct xbar. Bridge is used to connect xbars
433 system.hmc_dev.buffers = [Bridge(req_size=opt.xbar_buffer_size_req,
468 system.hmc_dev.buffer30 = Bridge(ranges=system.mem_ranges[0:4])
472 system.hmc_dev.buffer31 = Bridge(ranges=system.mem_ranges[4:8])
476 system.hmc_dev.buffer32 = Bridge(ranges=system.mem_ranges[8:12])
480 system.hmc_dev.buffer20 = Bridge(ranges=system.mem_ranges[0:4])
484 system.hmc_dev.buffer21 = Bridge(ranges=system.mem_ranges[4:8])
488 system.hmc_dev.buffer23 = Bridge(ranges=system.mem_ranges[12:16])
H A DFSConfig.py114 self.bridge = Bridge(delay='50ns',
161 self.bridge = Bridge(delay='50ns')
226 self.bridge = Bridge(delay='50ns')
412 self.bridge = Bridge(delay='50ns')
453 # North Bridge
455 x86_sys.bridge = Bridge(delay='50ns')
475 x86_sys.apicbridge = Bridge(delay='50ns')
489 # North Bridge
/gem5/configs/example/arm/
H A Ddevices.py214 self.iobridge = Bridge(delay='50ns')
223 self.dmabridge = Bridge(delay='50ns',
/gem5/configs/example/
H A Dfs.py190 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
284 drive_sys.iobridge = Bridge(delay='50ns',

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