Searched refs:x3 (Results 51 - 75 of 76) sorted by relevance
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/gem5/src/arch/arm/insts/ |
H A D | static_inst.cc | 690 if ((el == EL0 && cpacr.fpen != 0x3) || 725 if ((cur_el == EL0 && cpacr_cp10 != 0x3) || 1012 if ((el == EL0 && cpacr.zen != 0x3) ||
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/gem5/src/arch/arm/ |
H A D | tlb.cc | 661 switch ((dacr >> (static_cast<uint8_t>(te->domain) * 2)) & 0x3) { 849 uint8_t ap = 0x3 & (te->ap); // 2-bit access protection field 871 uint8_t hap = 0x3 & te->hap; 1121 temp_te.innerAttrs = 0x3; 1122 temp_te.outerAttrs = 0x3;
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H A D | table_walker.cc | 1242 uint8_t attr_3_2 = (attr >> 2) & 0x3; 1243 uint8_t attr_1_0 = attr & 0x3; 1330 te.innerAttrs = attr_7_4 == 0 ? 0x3 : 0; 1367 uint8_t attr_hi = (attr >> 2) & 0x3; 1368 uint8_t attr_lo = attr & 0x3; 1428 case 0x1 ... 0x3: // Normal Memory, Outer Write-through transient 1434 case 0x1 ... 0x3: // Normal Memory, Inner Write-through transient
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H A D | semihosting.cc | 121 0x3, // EXT_EXIT_EXTENDED, EXT_STDOUT_STDERR
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H A D | isa.cc | 563 ctr.l1IndexPolicy = 0x3;
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/gem5/ext/libelf/ |
H A D | elf_common.h | 438 #define STV_PROTECTED 0x3 /* Visible but not preemptible. */
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/gem5/ext/systemc/src/sysc/datatypes/fx/ |
H A D | scfx_rep.cpp | 2115 scfx_index x3 = calc_indices( params.iwl() - 1 - n_bits ); 2120 o_set( x, x3, enc, under ); 2190 scfx_index x3 = calc_indices( params.iwl() - 1 - n_bits ); 2198 o_set( x, x3, SC_TC_, under );
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/gem5/src/systemc/dt/fx/ |
H A D | scfx_rep.cc | 1922 scfx_index x3 = calc_indices(params.iwl() - 1 - n_bits); 1927 o_set(x, x3, enc, under); 1989 scfx_index x3 = calc_indices(params.iwl() - 1 - n_bits); 1997 o_set(x, x3, SC_TC_, under);
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/gem5/src/dev/alpha/ |
H A D | tsunami_cchip.cc | 113 (pkt->req->contextId() & 0x3));
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/gem5/src/dev/net/ |
H A D | i8254xGBe_defs.hh | 118 const uint8_t PHY_EPID = 0x3; 235 const uint8_t TXD_ADVDATA = 0x3;
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/gem5/src/dev/storage/ |
H A D | ide_disk.cc | 133 driveID.atap_piomode_supp = 0x3; 609 curPrdAddr = pciToDma((Addr)(prdTableBase & ~ULL(0x3)));
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H A D | ide_ctrl.cc | 476 bmiRegs.bmidtp = htole(*(uint32_t *)data & ~0x3);
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/gem5/system/alpha/palcode/ |
H A D | platform.S | 78 #define MAXPROC 0x3 626 and r13, 0x3, r10 // check for PCIA bits 739 and r13, 0x3, r10 // check for PCIA bits 763 and r13, 0x3, r10 // check for PCIA bits 792 and r13, 0x3, r10 // check for PCIA bits
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/gem5/tests/test-progs/asmtest/src/riscv/env/ |
H A D | encoding.h | 303 #define MATCH_LB 0x3 753 #define CSR_FCSR 0x3 965 #define CAUSE_BREAKPOINT 0x3
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/gem5/util/statetrace/arch/sparc/ |
H A D | tracechild.cc | 226 (sig == 0x1 || sig == 0x2 || sig == 0x3 || sig == 0x5 || sig == 0x6);
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/gem5/src/arch/sparc/ |
H A D | isa.cc | 355 return fprs | 0x3;
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H A D | tlb.cc | 386 sfsr = 0x3; 481 if (vaddr & 0x3) {
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/gem5/src/dev/arm/ |
H A D | generic_timer.cc | 629 return 0x3; // Frame 0 implemented with virtual timers
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H A D | gic_v3_distributor.cc | 795 irqNsacr[int_id] = (data >> (2 * int_id)) & 0x3;
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/gem5/src/arch/x86/ |
H A D | interrupts.cc | 73 int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
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/gem5/src/cpu/kvm/ |
H A D | x86_cpu.cc | 1333 } else if ((port & ~0x3) == IO_PCI_CONF_DATA_BASE) { 1337 (port & 0x3));
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/gem5/system/alpha/console/ |
H A D | console.c | 827 #define CONSCB_RESET_TERM 0x3
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/gem5/src/arch/hsail/insts/ |
H A D | decl.hh | 541 if ((src1 & 0x3) && (fpclass == FP_NAN)) {
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/gem5/src/python/m5/ext/pyfdt/ |
H A D | pyfdt.py | 34 FDT_PROP = 0x3
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/gem5/src/cpu/o3/ |
H A D | commit_impl.hh | 1059 (!(pc[0].instAddr() & 0x3)));
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