Searched refs:set (Results 76 - 100 of 322) sorted by relevance

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/gem5/ext/pybind11/tests/
H A Dtest_pytypes.cpp32 py::set set;
33 set.add(py::str("key1"));
34 set.add("key2");
35 set.add(std::string("key3"));
36 return set;
38 m.def("print_set", [](py::set set) {
39 for (auto item : set)
42 m.def("set_contains", [](py::set se
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/gem5/ext/dsent/model/std_cells/
H A DXOR2.cc254 cache->set(cell_name + "->ActiveArea", area);
287 cache->set(cell_name + "->Leakage->!A!B", leakage_00);
288 cache->set(cell_name + "->Leakage->!AB", leakage_01);
289 cache->set(cell_name + "->Leakage->A!B", leakage_10);
290 cache->set(cell_name + "->Leakage->AB", leakage_11);
303 cache->set(cell_name + "->Event_A_Flip", event_a_flip);
310 cache->set(cell_name + "->Event_B_Flip", event_b_flip);
316 cache->set(cell_name + "->Event_Y_Flip", event_y_flip);
330 cache->set(cell_name + "->Cap->A", a_cap);
331 cache->set(cell_nam
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H A DOR2.cc228 cache->set(cell_name + "->ActiveArea", area);
252 cache->set(cell_name + "->Leakage->!A!B", leakage_00);
253 cache->set(cell_name + "->Leakage->!AB", leakage_01);
254 cache->set(cell_name + "->Leakage->A!B", leakage_10);
255 cache->set(cell_name + "->Leakage->AB", leakage_11);
270 cache->set(cell_name + "->Cap->A", a_cap);
271 cache->set(cell_name + "->Cap->B", b_cap);
272 cache->set(cell_name + "->Cap->Y_b", y_b_cap);
273 cache->set(cell_name + "->Cap->Y", y_cap);
289 cache->set(cell_nam
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H A DDFFQ.cc333 cache->set(cell_name + "->Area->Active", area);
334 cache->set(cell_name + "->Area->Metal1Wire", area);
440 cache->set(cell_name + "->Leakage->!D!CK!Q", leakage_000);
441 cache->set(cell_name + "->Leakage->!D!CKQ", leakage_001);
442 cache->set(cell_name + "->Leakage->!DCK!Q", leakage_010);
443 cache->set(cell_name + "->Leakage->!DCKQ", leakage_011);
444 cache->set(cell_name + "->Leakage->D!CK!Q", leakage_100);
445 cache->set(cell_name + "->Leakage->D!CKQ", leakage_101);
446 cache->set(cell_name + "->Leakage->DCK!Q", leakage_110);
447 cache->set(cell_nam
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/gem5/ext/systemc/src/sysc/utils/
H A Dsc_list.h58 void set(handle_t h, void* d);
86 void set(void* d);
127 void set(handle_t h, T d) { sc_plist_base::set(h, (void*)d); } function in class:sc_core::sc_plist
162 void set(T d) { sc_plist_base_iter::set((void*) d); } function in class:sc_core::sc_plist_iter
/gem5/ext/dsent/model/
H A DEventInfo.cc41 m_trans_info_map_->set(port_name, TransitionInfo());
60 m_trans_info_map_->set(port_name_, trans_info_);
69 m_trans_info_map_->set(port_name_, TransitionInfo(0.5, 0.0, 0.5));
/gem5/ext/nomali/tests/
H A Dnomali_test_ints.c27 on_int(nomali_handle_t h, void *usr, nomali_int_t intno, int set) argument
29 test_diag("on_int: intno: %i, set: %i", intno, set);
30 *(int*)usr = !!set;
/gem5/src/mem/cache/tags/
H A Dsector_blk.cc172 SectorBlk::setPosition(const uint32_t set, const uint32_t way) argument
174 ReplaceableEntry::setPosition(set, way);
176 blk->setPosition(set, way);
/gem5/src/cpu/pred/
H A Dras.cc47 addrStack[i].set(0);
/gem5/src/mem/slicc/ast/
H A DDeclListAST.py42 s = set()
H A DTypeDeclAST.py43 return set()
49 return set(("%s.hh" % ident, "%s.cc" % ident))
H A DEnumDeclAST.py43 return set()
49 s = set(("%s.hh" % ident, "%s.cc" % ident))
H A DStateDeclAST.py42 return set()
48 s = set(("%s.hh" % ident, "%s.cc" % ident))
/gem5/ext/nomali/lib/
H A Dnomali_api.cc61 void callbackInt(nomali_int_t intno, int set);
89 void intJob(int set) override { api.callbackInt(NOMALI_INT_JOB, set); }
90 void intMMU(int set) override { api.callbackInt(NOMALI_INT_MMU, set); }
91 void intGPU(int set) override { api.callbackInt(NOMALI_INT_GPU, set); }
206 NoMaliApi::callbackInt(nomali_int_t intno, int set) argument
211 c.func.interrupt(static_cast<nomali_handle_t>(this), c.usr, intno, set); local
H A Djobcontrol.hh87 void onInterrupt(int set) override;
H A Dmmu.hh57 void onInterrupt(int set) override;
H A Dmmu.cc103 MMU::onInterrupt(int set) argument
105 gpu.intMMU(set);
/gem5/ext/systemc/src/tlm_core/tlm_2/tlm_quantum/
H A Dtlm_global_quantum.h38 // the global quantum is set.
58 void set(const sc_core::sc_time& t) function in class:tlm::tlm_global_quantum
/gem5/src/mem/cache/tags/indexing_policies/
H A Dbase.hh62 * from it determine hash functions that should be applied based on the set
80 * The amount to shift the address to get the set.
85 * Mask out all bits that aren't part of the set index.
124 * Get an entry based on its set and way. All entries must have been set
127 * @param set The set of the desired entry.
131 ReplaceableEntry* getEntry(const uint32_t set, const uint32_t way) const;
/gem5/src/mem/
H A Dpacket.hh301 /// Is the data pointer set to a value that shouldn't be freed
539 // look at the hasSharers flag (if not set, the response is to
578 * first, ignoring the cacheResponding flag if hasSharers is set.
591 flags.set(CACHE_RESPONDING);
597 * above. If the hasSharers flag is not set, the packet is passing
619 void setHasSharers() { flags.set(HAS_SHARERS); }
629 * other copies), the express snoop flag is set by the downstream
631 * the express snoop flag is also set to be able to distinguish
635 void setExpressSnoop() { flags.set(EXPRESS_SNOOP); }
641 * Owned response to a Modified one. If this flag is not set, th
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/gem5/src/cpu/
H A Dbase_dyn_inst.hh183 /** The status of this BaseDynInst. Several bits can be set. */
549 void setSerializeBefore() { status.set(SerializeBefore); }
554 /** Checks if this serializeBefore is only temporarily set. */
558 void setSerializeAfter() { status.set(SerializeAfter); }
563 /** Checks if this serializeAfter is only temporarily set. */
567 void setSerializeHandled() { status.set(SerializeHandled); }
670 /** Records an integer register being set to a value. */
676 /** Records a CC register being set to a value. */
682 /** Record a vector register being set to a value */
689 /** Records an fp register being set t
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/gem5/src/arch/arm/kvm/
H A Darm_cpu.hh43 #include <set>
167 static const std::set<uint64_t> invariant_regs;
/gem5/src/base/
H A Dflags.hh70 void set(Type flags) { _flags |= flags; } function in class:Flags
71 void set(Type f, bool val) { _flags = (_flags & ~f) | (val ? f : 0); } function in class:Flags
/gem5/ext/sst/
H A DExtMaster.hh49 #include <set>
94 std::set<AddrRange> ranges;
/gem5/src/dev/arm/
H A Dgpu_nomali.hh128 * @param set True is the interrupt is being asserted, false otherwise.
130 virtual void onInterrupt(nomali_int_t intno, bool set);
155 * @param set Was the interrupt raised (1) or lowered (0)?
158 nomali_int_t intno, int set);

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