1/*
2 * Copyright (c) 2014-2016 ARM Limited
3 * All rights reserved
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 *     http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 * Authors: Andreas Sandberg
18 */
19
20#ifndef _LIBNOMALIMODEL_MMU_HH
21#define _LIBNOMALIMODEL_MMU_HH
22
23#include <vector>
24
25#include "gpublock.hh"
26#include "addrspace.hh"
27#include "types.hh"
28
29namespace NoMali {
30
31class GPU;
32
33/**
34 * MMU dummy implementation.
35 *
36 * This is a dummy implementation of a Midgard GPU MMU block. The only
37 * features supported by the block is interrupt delivery and registers
38 * related to interrupt delivery. Writes to unimplemented registers
39 * (most registers) are discarded and their values are read as zero.
40 */
41class MMU
42    : public GPUBlockInt
43{
44  public:
45    MMU(GPU &_gpu);
46    virtual ~MMU();
47
48    void reset() override;
49
50    uint32_t readReg(RegAddr idx)  override;
51    void writeReg(RegAddr idx, uint32_t value) override;
52
53    uint32_t readRegRaw(RegAddr idx)  override;
54    void writeRegRaw(RegAddr idx, uint32_t value) override;
55
56  protected:
57    void onInterrupt(int set) override;
58
59    /** Address spaces belonging to this MMU block */
60    std::vector<AddrSpace> spaces;
61};
62
63}
64
65#endif // _LIBNOMALIMODEL_MMU_HH
66