Searched refs:mode (Results 76 - 100 of 141) sorted by relevance

123456

/gem5/src/gpu-compute/
H A Dgpu_tlb.cc609 // TODO If CPL > IOPL or in virtual mode, check the I/O permission
667 DPRINTF(GPUTLB, "In protected mode.\n");
668 // make sure we are in 64-bit mode
669 assert(m5Reg.mode == LongMode);
702 Translation *translation, Mode mode,
721 // If protected mode has been enabled...
723 DPRINTF(GPUTLB, "In protected mode.\n");
724 // If we're not in 64-bit mode, do protection/limit checks
725 if (m5Reg.mode != LongMode) {
726 DPRINTF(GPUTLB, "Not in long mode
701 translate(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, bool &delayedResponse, bool timing, int &latency) argument
904 translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode, int &latency) argument
914 translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, int &latency) argument
1125 pagingProtectionChecks(ThreadContext *tc, PacketPtr pkt, TlbEntry * tlb_entry, Mode mode) argument
1170 Mode mode = sender_state->tlbMode; local
1416 Mode mode = sender_state->tlbMode; local
[all...]
H A Dshader.hh105 // is this simulation going to be timing mode in the memory?
196 void functionalTLBAccess(PacketPtr pkt, int cu_id, BaseTLB::Mode mode);
/gem5/src/arch/x86/
H A Dpagetable_walker.cc73 // TODO: in timing mode, instead of blocking when there are other
186 mode = _mode;
206 currState->req, currState->tc, currState->mode);
297 bool badNX = pte.nx && mode == BaseTLB::Execute && enableNX;
301 "Got long mode PML4 entry %#016x.\n", (uint64_t)pte);
317 "Got long mode PDP entry %#016x.\n", (uint64_t)pte);
332 "Got long mode PD entry %#016x.\n", (uint64_t)pte);
363 "Got long mode PTE entry %#016x.\n", (uint64_t)pte);
383 "Got legacy mode PAE PDP entry %#08x.\n", (uint32_t)pte);
394 "Got legacy mode PA
[all...]
H A Dfaults.hh322 PageFault(Addr _addr, bool present, BaseTLB::Mode mode, argument
328 code.write = (mode == BaseTLB::Write);
331 code.fetch = (mode == BaseTLB::Execute);
/gem5/util/
H A Dcheckpoint_aggregator.py56 merged_mem = gzip.GzipFile(fileobj= agg_mem_file, mode="wb")
103 gf = gzip.GzipFile(fileobj=f, mode="rb")
H A Dcompile168 help="Do not compile System Call Emulation mode")
170 help="Do not compile Full System mode")
225 sys.exit("must specify at least one mode")
231 # valid combinations of ISA and emulation mode
237 # experimental combinations of ISA and emulation mode
246 for mode in modes:
248 build = valid[(isa, mode)]
254 sys.exit("must specify at least one valid combination of ISA and mode")
/gem5/src/dev/x86/
H A DSouthBridge.py50 _pic1 = I8259(pio_addr=x86IOAddress(0x20), mode='I8259Master')
51 _pic2 = I8259(pio_addr=x86IOAddress(0xA0), mode='I8259Slave')
/gem5/src/arch/mips/
H A Ddsp.cc423 MipsISA::dspMuleu(int32_t a, int32_t b, int32_t mode, uint32_t *dspctl) argument
434 switch (mode) {
457 MipsISA::dspMuleq(int32_t a, int32_t b, int32_t mode, uint32_t *dspctl) argument
471 switch (mode) {
495 int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode,
509 switch (mode) {
562 int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode,
576 switch (mode) {
629 int32_t fmt, int32_t sign, int32_t mode)
639 switch (mode) {
494 dspDpaq(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode, uint32_t *dspctl) argument
561 dspDpsq(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode, uint32_t *dspctl) argument
628 dspDpa(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t sign, int32_t mode) argument
656 dspDps(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t sign, int32_t mode) argument
684 dspMaq(int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t mode, int32_t saturate, uint32_t *dspctl) argument
873 dspPrece(int32_t a, int32_t infmt, int32_t insign, int32_t outfmt, int32_t outsign, int32_t mode) argument
[all...]
H A Ddt_constants.hh97 Bitfield<11, 7> mode; member in namespace:MipsISA
/gem5/src/sim/
H A Dfd_array.cc271 * Assume that this has the mode of an output file so there's no
272 * need to worry about properly recording the mode. If you're
298 FDArray::openFile(std::string const& filename, int flags, mode_t mode) const
300 int sim_fd = open(filename.c_str(), flags, mode);
303 fatal("Unable to open %s with mode %O", filename, mode);
/gem5/src/arch/arm/insts/
H A Dstatic_inst.cc1025 const ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t)spsr.mode);
1052 const OperatingMode mode = (OperatingMode) (uint8_t)spsr.mode;
1053 if (unknownMode(mode))
1056 const OperatingMode cur_mode = (OperatingMode) (uint8_t)cpsr.mode;
1057 const ExceptionLevel target_el = opModeToEL(mode);
1092 return unknownMode32(mode);
1113 new_cpsr.mode = cpsr.mode;
1121 if (spsr.width && unknownMode32((OperatingMode)(uint8_t)spsr.mode)) {
[all...]
H A Dvfp.cc44 * the rounding mode might be set after the operation it was intended for, the
466 unsigned mode = rMode; local
467 if ((mode == VfpRoundUpward && !neg && extra) ||
468 (mode == VfpRoundDown && neg && extra) ||
469 (mode == VfpRoundNearest &&
511 unsigned mode = rMode; local
513 if ((mode == VfpRoundUpward && !neg && nonZero) ||
514 (mode == VfpRoundDown && neg && nonZero) ||
515 (mode == VfpRoundNearest && topOne &&
537 if ((mode
[all...]
H A Dmem.hh82 AddrMode mode; member in class:ArmISA::RfeOp
92 base(_base), mode(_mode), wb(_wb),
127 AddrMode mode; member in class:ArmISA::SrsOp
136 regMode(_regMode), mode(_mode), wb(_wb), uops(NULL)
/gem5/src/python/m5/
H A Dsimulate.py183 """Drain the simulator in preparation of a checkpoint or memory mode
235 def _changeMemoryMode(system, mode):
239 if system.getMemoryMode() != mode:
240 system.setMemoryMode(mode)
242 print("System already in target mode. Memory mode unchanged.")
247 Note: This method may switch the memory mode of the system if that
295 raise RuntimeError("Invalid memory mode (%s)" % memory_mode_name)
303 # Change the memory mode if required. We check if this is needed
306 # Flush the memory system if we are switching to a memory mode
[all...]
/gem5/src/arch/arm/
H A Dintregs.hh166 /* USR mode */
187 /* SVC mode */
204 /* MON mode */
221 /* ABT mode */
238 /* HYP mode */
257 /* UND mode */
274 /* IRQ mode */
291 /* FIQ mode */
464 intRegInMode(OperatingMode mode, int reg)
467 return mode * intRegsPerMod
[all...]
H A Dstage2_mmu.cc122 ThreadContext *tc, BaseTLB::Mode mode)
120 finish(const Fault &_fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode) argument
H A Dinterrupts.hh186 virtWake &= (cpsr.mode != MODE_HYP) && !inSecureState(scr, cpsr);
196 useHcrMux = (cpsr.mode != MODE_HYP) && !inSecureState(scr, cpsr);
H A Disa.hh386 switch (cpsr.mode) {
413 panic("Unrecognized mode setting in CPSR.\n");
483 (OperatingMode) (uint8_t) cpsr.mode);
547 switch (cpsr.mode) {
549 warn("User mode does not have SPSR\n");
565 warn("User mode does not have SPSR\n");
590 warn("Trying to access SPSR in an invalid mode: %d\n",
591 cpsr.mode);
772 mode(const ArmISA::PCState& pc) function in struct:RenameMode
/gem5/src/cpu/minor/
H A Dlsq.hh283 ThreadContext *tc, BaseTLB::Mode mode)
344 ThreadContext *tc, BaseTLB::Mode mode);
417 ThreadContext *tc, BaseTLB::Mode mode);
282 finish(const Fault &fault_, const RequestPtr &request_, ThreadContext *tc, BaseTLB::Mode mode) argument
H A Dfetch1.hh167 ThreadContext *tc, BaseTLB::Mode mode);
/gem5/src/mem/cache/prefetch/
H A Dqueued.hh125 ThreadContext *tc, BaseTLB::Mode mode) override;
/gem5/src/cpu/o3/
H A Dfetch.hh131 BaseTLB::Mode mode)
133 assert(mode == BaseTLB::Execute);
130 finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode) argument
/gem5/src/dev/storage/
H A Ddisk_image.cc86 ios::openmode mode = ios::in | ios::binary; local
88 mode |= ios::out;
89 stream.open(file.c_str(), mode);
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64si/
H A Ddirty.S24 # Set up MPRV with MPP=S, so loads and stores use S-mode
/gem5/configs/dram/
H A Dsweep.py76 parser.add_option("--mode", type="choice", default="DRAM",
187 generator = dram_generators[options.mode](system.tgen)

Completed in 50 milliseconds

123456