1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#include <cassert>
44
45#ifndef __ARCH_ARM_INTREGS_HH__
46#define __ARCH_ARM_INTREGS_HH__
47
48#include "arch/arm/types.hh"
49
50namespace ArmISA
51{
52
53enum IntRegIndex
54{
55    /* All the unique register indices. */
56    INTREG_R0,
57    INTREG_R1,
58    INTREG_R2,
59    INTREG_R3,
60    INTREG_R4,
61    INTREG_R5,
62    INTREG_R6,
63    INTREG_R7,
64    INTREG_R8,
65    INTREG_R9,
66    INTREG_R10,
67    INTREG_R11,
68    INTREG_R12,
69    INTREG_R13,
70    INTREG_SP = INTREG_R13,
71    INTREG_R14,
72    INTREG_LR = INTREG_R14,
73    INTREG_R15,
74    INTREG_PC = INTREG_R15,
75
76    INTREG_R13_SVC,
77    INTREG_SP_SVC = INTREG_R13_SVC,
78    INTREG_R14_SVC,
79    INTREG_LR_SVC = INTREG_R14_SVC,
80
81    INTREG_R13_MON,
82    INTREG_SP_MON = INTREG_R13_MON,
83    INTREG_R14_MON,
84    INTREG_LR_MON = INTREG_R14_MON,
85
86    INTREG_R13_HYP,
87    INTREG_SP_HYP = INTREG_R13_HYP,
88
89    INTREG_R13_ABT,
90    INTREG_SP_ABT = INTREG_R13_ABT,
91    INTREG_R14_ABT,
92    INTREG_LR_ABT = INTREG_R14_ABT,
93
94    INTREG_R13_UND,
95    INTREG_SP_UND = INTREG_R13_UND,
96    INTREG_R14_UND,
97    INTREG_LR_UND = INTREG_R14_UND,
98
99    INTREG_R13_IRQ,
100    INTREG_SP_IRQ = INTREG_R13_IRQ,
101    INTREG_R14_IRQ,
102    INTREG_LR_IRQ = INTREG_R14_IRQ,
103
104    INTREG_R8_FIQ,
105    INTREG_R9_FIQ,
106    INTREG_R10_FIQ,
107    INTREG_R11_FIQ,
108    INTREG_R12_FIQ,
109    INTREG_R13_FIQ,
110    INTREG_SP_FIQ = INTREG_R13_FIQ,
111    INTREG_R14_FIQ,
112    INTREG_LR_FIQ = INTREG_R14_FIQ,
113
114    INTREG_ZERO,
115    INTREG_UREG0,
116    INTREG_UREG1,
117    INTREG_UREG2,
118    INTREG_DUMMY, // Dummy reg used to throw away int reg results
119
120    INTREG_SP0,
121    INTREG_SP1,
122    INTREG_SP2,
123    INTREG_SP3,
124
125    NUM_INTREGS,
126    NUM_ARCH_INTREGS = 32,
127
128    /* AArch64 registers */
129    INTREG_X0 = 0,
130    INTREG_X1,
131    INTREG_X2,
132    INTREG_X3,
133    INTREG_X4,
134    INTREG_X5,
135    INTREG_X6,
136    INTREG_X7,
137    INTREG_X8,
138    INTREG_X9,
139    INTREG_X10,
140    INTREG_X11,
141    INTREG_X12,
142    INTREG_X13,
143    INTREG_X14,
144    INTREG_X15,
145    INTREG_X16,
146    INTREG_X17,
147    INTREG_X18,
148    INTREG_X19,
149    INTREG_X20,
150    INTREG_X21,
151    INTREG_X22,
152    INTREG_X23,
153    INTREG_X24,
154    INTREG_X25,
155    INTREG_X26,
156    INTREG_X27,
157    INTREG_X28,
158    INTREG_X29,
159    INTREG_X30,
160    INTREG_X31,
161
162    INTREG_SPX = NUM_INTREGS,
163
164    /* All the aliased indexes. */
165
166    /* USR mode */
167    INTREG_R0_USR = INTREG_R0,
168    INTREG_R1_USR = INTREG_R1,
169    INTREG_R2_USR = INTREG_R2,
170    INTREG_R3_USR = INTREG_R3,
171    INTREG_R4_USR = INTREG_R4,
172    INTREG_R5_USR = INTREG_R5,
173    INTREG_R6_USR = INTREG_R6,
174    INTREG_R7_USR = INTREG_R7,
175    INTREG_R8_USR = INTREG_R8,
176    INTREG_R9_USR = INTREG_R9,
177    INTREG_R10_USR = INTREG_R10,
178    INTREG_R11_USR = INTREG_R11,
179    INTREG_R12_USR = INTREG_R12,
180    INTREG_R13_USR = INTREG_R13,
181    INTREG_SP_USR = INTREG_SP,
182    INTREG_R14_USR = INTREG_R14,
183    INTREG_LR_USR = INTREG_LR,
184    INTREG_R15_USR = INTREG_R15,
185    INTREG_PC_USR = INTREG_PC,
186
187    /* SVC mode */
188    INTREG_R0_SVC = INTREG_R0,
189    INTREG_R1_SVC = INTREG_R1,
190    INTREG_R2_SVC = INTREG_R2,
191    INTREG_R3_SVC = INTREG_R3,
192    INTREG_R4_SVC = INTREG_R4,
193    INTREG_R5_SVC = INTREG_R5,
194    INTREG_R6_SVC = INTREG_R6,
195    INTREG_R7_SVC = INTREG_R7,
196    INTREG_R8_SVC = INTREG_R8,
197    INTREG_R9_SVC = INTREG_R9,
198    INTREG_R10_SVC = INTREG_R10,
199    INTREG_R11_SVC = INTREG_R11,
200    INTREG_R12_SVC = INTREG_R12,
201    INTREG_PC_SVC = INTREG_PC,
202    INTREG_R15_SVC = INTREG_R15,
203
204    /* MON mode */
205    INTREG_R0_MON = INTREG_R0,
206    INTREG_R1_MON = INTREG_R1,
207    INTREG_R2_MON = INTREG_R2,
208    INTREG_R3_MON = INTREG_R3,
209    INTREG_R4_MON = INTREG_R4,
210    INTREG_R5_MON = INTREG_R5,
211    INTREG_R6_MON = INTREG_R6,
212    INTREG_R7_MON = INTREG_R7,
213    INTREG_R8_MON = INTREG_R8,
214    INTREG_R9_MON = INTREG_R9,
215    INTREG_R10_MON = INTREG_R10,
216    INTREG_R11_MON = INTREG_R11,
217    INTREG_R12_MON = INTREG_R12,
218    INTREG_PC_MON = INTREG_PC,
219    INTREG_R15_MON = INTREG_R15,
220
221    /* ABT mode */
222    INTREG_R0_ABT = INTREG_R0,
223    INTREG_R1_ABT = INTREG_R1,
224    INTREG_R2_ABT = INTREG_R2,
225    INTREG_R3_ABT = INTREG_R3,
226    INTREG_R4_ABT = INTREG_R4,
227    INTREG_R5_ABT = INTREG_R5,
228    INTREG_R6_ABT = INTREG_R6,
229    INTREG_R7_ABT = INTREG_R7,
230    INTREG_R8_ABT = INTREG_R8,
231    INTREG_R9_ABT = INTREG_R9,
232    INTREG_R10_ABT = INTREG_R10,
233    INTREG_R11_ABT = INTREG_R11,
234    INTREG_R12_ABT = INTREG_R12,
235    INTREG_PC_ABT = INTREG_PC,
236    INTREG_R15_ABT = INTREG_R15,
237
238    /* HYP mode */
239    INTREG_R0_HYP = INTREG_R0,
240    INTREG_R1_HYP = INTREG_R1,
241    INTREG_R2_HYP = INTREG_R2,
242    INTREG_R3_HYP = INTREG_R3,
243    INTREG_R4_HYP = INTREG_R4,
244    INTREG_R5_HYP = INTREG_R5,
245    INTREG_R6_HYP = INTREG_R6,
246    INTREG_R7_HYP = INTREG_R7,
247    INTREG_R8_HYP = INTREG_R8,
248    INTREG_R9_HYP = INTREG_R9,
249    INTREG_R10_HYP = INTREG_R10,
250    INTREG_R11_HYP = INTREG_R11,
251    INTREG_R12_HYP = INTREG_R12,
252    INTREG_LR_HYP = INTREG_LR,
253    INTREG_R14_HYP = INTREG_R14,
254    INTREG_PC_HYP = INTREG_PC,
255    INTREG_R15_HYP = INTREG_R15,
256
257    /* UND mode */
258    INTREG_R0_UND = INTREG_R0,
259    INTREG_R1_UND = INTREG_R1,
260    INTREG_R2_UND = INTREG_R2,
261    INTREG_R3_UND = INTREG_R3,
262    INTREG_R4_UND = INTREG_R4,
263    INTREG_R5_UND = INTREG_R5,
264    INTREG_R6_UND = INTREG_R6,
265    INTREG_R7_UND = INTREG_R7,
266    INTREG_R8_UND = INTREG_R8,
267    INTREG_R9_UND = INTREG_R9,
268    INTREG_R10_UND = INTREG_R10,
269    INTREG_R11_UND = INTREG_R11,
270    INTREG_R12_UND = INTREG_R12,
271    INTREG_PC_UND = INTREG_PC,
272    INTREG_R15_UND = INTREG_R15,
273
274    /* IRQ mode */
275    INTREG_R0_IRQ = INTREG_R0,
276    INTREG_R1_IRQ = INTREG_R1,
277    INTREG_R2_IRQ = INTREG_R2,
278    INTREG_R3_IRQ = INTREG_R3,
279    INTREG_R4_IRQ = INTREG_R4,
280    INTREG_R5_IRQ = INTREG_R5,
281    INTREG_R6_IRQ = INTREG_R6,
282    INTREG_R7_IRQ = INTREG_R7,
283    INTREG_R8_IRQ = INTREG_R8,
284    INTREG_R9_IRQ = INTREG_R9,
285    INTREG_R10_IRQ = INTREG_R10,
286    INTREG_R11_IRQ = INTREG_R11,
287    INTREG_R12_IRQ = INTREG_R12,
288    INTREG_PC_IRQ = INTREG_PC,
289    INTREG_R15_IRQ = INTREG_R15,
290
291    /* FIQ mode */
292    INTREG_R0_FIQ = INTREG_R0,
293    INTREG_R1_FIQ = INTREG_R1,
294    INTREG_R2_FIQ = INTREG_R2,
295    INTREG_R3_FIQ = INTREG_R3,
296    INTREG_R4_FIQ = INTREG_R4,
297    INTREG_R5_FIQ = INTREG_R5,
298    INTREG_R6_FIQ = INTREG_R6,
299    INTREG_R7_FIQ = INTREG_R7,
300    INTREG_PC_FIQ = INTREG_PC,
301    INTREG_R15_FIQ = INTREG_R15
302};
303
304typedef IntRegIndex IntRegMap[NUM_ARCH_INTREGS];
305
306const IntRegMap IntReg64Map = {
307    INTREG_R0,      INTREG_R1,      INTREG_R2,      INTREG_R3,
308    INTREG_R4,      INTREG_R5,      INTREG_R6,      INTREG_R7,
309    INTREG_R8_USR,  INTREG_R9_USR,  INTREG_R10_USR, INTREG_R11_USR,
310    INTREG_R12_USR, INTREG_R13_USR, INTREG_R14_USR, INTREG_R13_HYP,
311    INTREG_R14_IRQ, INTREG_R13_IRQ, INTREG_R14_SVC, INTREG_R13_SVC,
312    INTREG_R14_ABT, INTREG_R13_ABT, INTREG_R14_UND, INTREG_R13_UND,
313    INTREG_R8_FIQ,  INTREG_R9_FIQ,  INTREG_R10_FIQ, INTREG_R11_FIQ,
314    INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_R14_FIQ, INTREG_ZERO
315};
316
317const IntRegMap IntRegUsrMap = {
318    INTREG_R0_USR,  INTREG_R1_USR,  INTREG_R2_USR,  INTREG_R3_USR,
319    INTREG_R4_USR,  INTREG_R5_USR,  INTREG_R6_USR,  INTREG_R7_USR,
320    INTREG_R8_USR,  INTREG_R9_USR,  INTREG_R10_USR, INTREG_R11_USR,
321    INTREG_R12_USR, INTREG_R13_USR, INTREG_R14_USR, INTREG_R15_USR,
322    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
323    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
324    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
325    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
326};
327
328static inline IntRegIndex
329INTREG_USR(unsigned index)
330{
331    assert(index < NUM_ARCH_INTREGS);
332    return IntRegUsrMap[index];
333}
334
335const IntRegMap IntRegHypMap = {
336    INTREG_R0_HYP,  INTREG_R1_HYP,  INTREG_R2_HYP,  INTREG_R3_HYP,
337    INTREG_R4_HYP,  INTREG_R5_HYP,  INTREG_R6_HYP,  INTREG_R7_HYP,
338    INTREG_R8_HYP,  INTREG_R9_HYP,  INTREG_R10_HYP, INTREG_R11_HYP,
339    INTREG_R12_HYP, INTREG_R13_HYP, INTREG_R14_HYP, INTREG_R15_HYP,
340    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
341    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
342    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
343    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
344};
345
346static inline IntRegIndex
347INTREG_HYP(unsigned index)
348{
349    assert(index < NUM_ARCH_INTREGS);
350    return IntRegHypMap[index];
351}
352
353const IntRegMap IntRegSvcMap = {
354    INTREG_R0_SVC,  INTREG_R1_SVC,  INTREG_R2_SVC,  INTREG_R3_SVC,
355    INTREG_R4_SVC,  INTREG_R5_SVC,  INTREG_R6_SVC,  INTREG_R7_SVC,
356    INTREG_R8_SVC,  INTREG_R9_SVC,  INTREG_R10_SVC, INTREG_R11_SVC,
357    INTREG_R12_SVC, INTREG_R13_SVC, INTREG_R14_SVC, INTREG_R15_SVC,
358    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
359    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
360    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
361    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
362};
363
364static inline IntRegIndex
365INTREG_SVC(unsigned index)
366{
367    assert(index < NUM_ARCH_INTREGS);
368    return IntRegSvcMap[index];
369}
370
371const IntRegMap IntRegMonMap = {
372    INTREG_R0_MON,  INTREG_R1_MON,  INTREG_R2_MON,  INTREG_R3_MON,
373    INTREG_R4_MON,  INTREG_R5_MON,  INTREG_R6_MON,  INTREG_R7_MON,
374    INTREG_R8_MON,  INTREG_R9_MON,  INTREG_R10_MON, INTREG_R11_MON,
375    INTREG_R12_MON, INTREG_R13_MON, INTREG_R14_MON, INTREG_R15_MON,
376    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
377    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
378    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
379    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
380};
381
382static inline IntRegIndex
383INTREG_MON(unsigned index)
384{
385    assert(index < NUM_ARCH_INTREGS);
386    return IntRegMonMap[index];
387}
388
389const IntRegMap IntRegAbtMap = {
390    INTREG_R0_ABT,  INTREG_R1_ABT,  INTREG_R2_ABT,  INTREG_R3_ABT,
391    INTREG_R4_ABT,  INTREG_R5_ABT,  INTREG_R6_ABT,  INTREG_R7_ABT,
392    INTREG_R8_ABT,  INTREG_R9_ABT,  INTREG_R10_ABT, INTREG_R11_ABT,
393    INTREG_R12_ABT, INTREG_R13_ABT, INTREG_R14_ABT, INTREG_R15_ABT,
394    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
395    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
396    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
397    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
398};
399
400static inline IntRegIndex
401INTREG_ABT(unsigned index)
402{
403    assert(index < NUM_ARCH_INTREGS);
404    return IntRegAbtMap[index];
405}
406
407const IntRegMap IntRegUndMap = {
408    INTREG_R0_UND,  INTREG_R1_UND,  INTREG_R2_UND,  INTREG_R3_UND,
409    INTREG_R4_UND,  INTREG_R5_UND,  INTREG_R6_UND,  INTREG_R7_UND,
410    INTREG_R8_UND,  INTREG_R9_UND,  INTREG_R10_UND, INTREG_R11_UND,
411    INTREG_R12_UND, INTREG_R13_UND, INTREG_R14_UND, INTREG_R15_UND,
412    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
413    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
414    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
415    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
416};
417
418static inline IntRegIndex
419INTREG_UND(unsigned index)
420{
421    assert(index < NUM_ARCH_INTREGS);
422    return IntRegUndMap[index];
423}
424
425const IntRegMap IntRegIrqMap = {
426    INTREG_R0_IRQ,  INTREG_R1_IRQ,  INTREG_R2_IRQ,  INTREG_R3_IRQ,
427    INTREG_R4_IRQ,  INTREG_R5_IRQ,  INTREG_R6_IRQ,  INTREG_R7_IRQ,
428    INTREG_R8_IRQ,  INTREG_R9_IRQ,  INTREG_R10_IRQ, INTREG_R11_IRQ,
429    INTREG_R12_IRQ, INTREG_R13_IRQ, INTREG_R14_IRQ, INTREG_R15_IRQ,
430    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
431    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
432    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
433    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
434};
435
436static inline IntRegIndex
437INTREG_IRQ(unsigned index)
438{
439    assert(index < NUM_ARCH_INTREGS);
440    return IntRegIrqMap[index];
441}
442
443const IntRegMap IntRegFiqMap = {
444    INTREG_R0_FIQ,  INTREG_R1_FIQ,  INTREG_R2_FIQ,  INTREG_R3_FIQ,
445    INTREG_R4_FIQ,  INTREG_R5_FIQ,  INTREG_R6_FIQ,  INTREG_R7_FIQ,
446    INTREG_R8_FIQ,  INTREG_R9_FIQ,  INTREG_R10_FIQ, INTREG_R11_FIQ,
447    INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_R14_FIQ, INTREG_R15_FIQ,
448    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
449    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
450    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,
451    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO,    INTREG_ZERO
452};
453
454static inline IntRegIndex
455INTREG_FIQ(unsigned index)
456{
457    assert(index < NUM_ARCH_INTREGS);
458    return IntRegFiqMap[index];
459}
460
461static const unsigned intRegsPerMode = NUM_INTREGS;
462
463static inline int
464intRegInMode(OperatingMode mode, int reg)
465{
466    assert(reg < NUM_ARCH_INTREGS);
467    return mode * intRegsPerMode + reg;
468}
469
470static inline int
471flattenIntRegModeIndex(int reg)
472{
473    int mode = reg / intRegsPerMode;
474    reg = reg % intRegsPerMode;
475    switch (mode) {
476      case MODE_USER:
477      case MODE_SYSTEM:
478        return INTREG_USR(reg);
479      case MODE_FIQ:
480        return INTREG_FIQ(reg);
481      case MODE_IRQ:
482        return INTREG_IRQ(reg);
483      case MODE_SVC:
484        return INTREG_SVC(reg);
485      case MODE_MON:
486        return INTREG_MON(reg);
487      case MODE_ABORT:
488        return INTREG_ABT(reg);
489      case MODE_HYP:
490        return INTREG_HYP(reg);
491      case MODE_UNDEFINED:
492        return INTREG_UND(reg);
493      default:
494        panic("%d: Flattening into an unknown mode: reg:%#x mode:%#x\n",
495                curTick(), reg, mode);
496    }
497}
498
499
500static inline IntRegIndex
501makeSP(IntRegIndex reg)
502{
503    if (reg == INTREG_X31)
504        reg = INTREG_SPX;
505    return reg;
506}
507
508static inline IntRegIndex
509makeZero(IntRegIndex reg)
510{
511    if (reg == INTREG_X31)
512        reg = INTREG_ZERO;
513    return reg;
514}
515
516static inline bool
517isSP(IntRegIndex reg)
518{
519    return reg == INTREG_SPX;
520}
521
522}
523
524#endif
525