Searched refs:inst (Results 26 - 50 of 148) sorted by relevance

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/gem5/src/arch/riscv/
H A Ddecoder.cc53 Decoder::moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) argument
55 DPRINTF(Decode, "Requesting bytes 0x%08x from address %#x\n", inst,
60 emi = inst;
68 emi |= (inst & LowerBitMask) << sizeof(MachInst)*4;
73 emi = (inst & UpperBitMask) >> sizeof(MachInst)*4;
H A Ddecoder.hh67 inline bool compressed(ExtMachInst inst) { return (inst & 0x3) < 0x3; } argument
71 void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst);
H A Dstacktrace.cc72 StackTrace::StackTrace(ThreadContext *_tc, const StaticInstPtr &inst) argument
97 StackTrace::decodeStack(MachInst inst, int &disp) argument
104 StackTrace::decodeSave(MachInst inst, int &reg, int &disp) argument
/gem5/src/cpu/minor/
H A Dlsq.cc63 inst(inst_),
80 SimpleThread &thread = *port.cpu.threads[inst->id.threadId];
82 ExecContext context(port.cpu, thread, port.execute, inst);
83 Fault M5_VAR_USED fault = inst->translationFault;
86 inst->translationFault = inst->staticInst->initiateAcc(&context, nullptr);
87 if (inst->translationFault == NoFault) {
89 "Translation fault suppressed for inst:%s\n", *inst);
91 assert(inst
250 clearMemBarrier(MinorDynInstPtr inst) argument
913 completeMemBarrierInst(MinorDynInstPtr inst, bool committed) argument
1477 findResponse(MinorDynInstPtr inst) argument
1574 pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data, unsigned int size, Addr addr, Request::Flags flags, uint64_t *res, AtomicOpFunctorPtr amo_op, const std::vector<bool>& byteEnable) argument
1649 pushFailedRequest(MinorDynInstPtr inst) argument
1700 issuedMemBarrierInst(MinorDynInstPtr inst) argument
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H A Ddecode.cc109 dynInstAddTracing(MinorDynInstPtr inst, StaticInstPtr static_inst, argument
112 inst->traceData = cpu.getTracer()->getInstRecord(curTick(),
113 cpu.getContext(inst->id.threadId),
114 inst->staticInst, inst->pc, static_inst);
118 if (inst->traceData)
119 inst->traceData->setFetchSeq(inst->id.execSeqNum);
151 MinorDynInstPtr inst = insts_in->insts[decode_info.inputIndex]; local
153 if (inst
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H A Dscoreboard.hh89 /** The execute sequence number of the most recent inst to generate this
114 * numResults counts. If mark_unpredictable is true, the inst's
117 void markupInstDests(MinorDynInstPtr inst, Cycles retire_time,
121 * must match mark_unpredictable for the same inst. */
122 void clearInstDests(MinorDynInstPtr inst, bool clear_unpredictable);
124 /** Returns the exec sequence number of the most recent inst on
125 * which the given inst depends. Useful for determining which
126 * inst must actually be committed before a dependent inst
128 InstSeqNum execSeqNumToWaitFor(MinorDynInstPtr inst,
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H A Ddyn_inst.cc118 operator <<(std::ostream &os, const MinorDynInst &inst) argument
120 os << inst.id << " pc: 0x"
121 << std::hex << inst.pc.instAddr() << std::dec << " (";
123 if (inst.isFault())
124 os << "fault: \"" << inst.fault->name() << '"';
125 else if (inst.translationFault != NoFault)
126 os << "translation fault: \"" << inst.translationFault->name() << '"';
127 else if (inst.staticInst)
128 os << inst.staticInst->getName();
228 MINORINST(&named_object, "id=%s addr=0x%x inst
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H A Dexecute.hh141 DrainCurrentInst, /* Draining to end of inst/macroop */
142 DrainHaltFetch, /* Halting Fetch after completing current inst */
218 * Also handles branch prediction information within the inst. */
219 void tryToBranch(MinorDynInstPtr inst, Fault fault, BranchData &branch);
224 MinorDynInstPtr inst, const TheISA::PCState &target,
232 void handleMemResponse(MinorDynInstPtr inst,
247 bool executeMemRefInst(MinorDynInstPtr inst, BranchData &branch,
269 void doInstCommitAccounting(MinorDynInstPtr inst);
294 bool commitInst(MinorDynInstPtr inst, bool early_memory_issue,
335 bool instIsRightStream(MinorDynInstPtr inst);
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H A Dfunc_unit.cc110 inst->reportData(os);
203 FUPipeline::findTiming(const StaticInstPtr &inst) argument
207 TheISA::ExtMachInst mach_inst = inst->machInst;
220 if (timing.provides(inst->opClass()) &&
226 i, timing.description, inst->disassemble(0), mach_inst,
227 typeid(inst).name());
235 "No extra timing info. found for inst: %s"
237 inst->disassemble(0), mach_inst);
/gem5/util/
H A Do3-pipeview.py159 def queue_inst(outfile, inst, cycle_time, width, color, timestamps, store_completions):
161 l_copy = copy.deepcopy(inst)
191 def print_inst(outfile, inst, cycle_time, width, color, timestamps, store_completions):
228 base_tick = (inst['fetch'] / time_width) * time_width
232 last_event_time = max(inst['fetch'], inst['decode'],inst['rename'],
233 inst['dispatch'],inst['issue'], inst['complet
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/gem5/src/cpu/checker/
H A Dcpu_impl.hh100 DynInstPtr inst; local
107 inst = instList.front();
109 verify(inst); // verify the instructions
110 inst = NULL;
129 DynInstPtr inst; local
159 inst = instList.front();
173 inst = completed_inst;
183 if (inst->isSerializeAfter() && !instList.empty()) {
188 unverifiedInst = inst;
189 inst
459 validateInst(const DynInstPtr &inst) argument
480 validateExecution(const DynInstPtr &inst) argument
598 copyResult(const DynInstPtr &inst, const InstResult& mismatch_val, int start_idx) argument
675 dumpAndExit(const DynInstPtr &inst) argument
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/gem5/src/arch/sparc/
H A Dstacktrace.hh51 trace(ThreadContext *tc, const StaticInstPtr &inst) argument
/gem5/src/arch/alpha/
H A Dstacktrace.cc126 StackTrace::StackTrace(ThreadContext *_tc, const StaticInstPtr &inst) argument
129 trace(_tc, inst);
237 StackTrace::decodeStack(MachInst inst, int &disp) argument
265 if ((inst & mem_mask) == lda_pattern)
266 disp = -sext<16>(inst & lda_disp_mask);
267 else if ((inst & intop_mask) == addq_pattern)
268 disp = -int((inst & intop_disp_mask) >> intop_disp_shift);
269 else if ((inst & intop_mask) == subq_pattern)
270 disp = int((inst & intop_disp_mask) >> intop_disp_shift);
278 StackTrace::decodeSave(MachInst inst, in argument
314 MachInst inst = tc->getVirtProxy().read<MachInst>(pc); local
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H A Ddecoder.hh67 moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) argument
69 ext_inst = inst;
/gem5/src/arch/generic/
H A Ddebugfaults.hh57 advancePC(ThreadContext *tc, const StaticInstPtr &inst) argument
59 if (inst) {
61 inst->advancePC(pc);
77 invoke(ThreadContext *tc, const StaticInstPtr &inst =
81 advancePC(tc, inst);
109 invoke(ThreadContext *tc, const StaticInstPtr &inst =
116 advancePC(tc, inst);
/gem5/src/cpu/o3/
H A Ddecode_impl.hh306 DefaultDecode<Impl>::squash(const DynInstPtr &inst, ThreadID tid) argument
309 "prediction detected at decode.\n", tid, inst->seqNum);
314 toFetch->decodeInfo[tid].mispredictInst = inst;
316 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
317 toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
318 toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching();
319 toFetch->decodeInfo[tid].squashInst = inst;
324 InstSeqNum squash_seq_num = inst->seqNum;
408 DynInstPtr inst = NULL; local
411 inst
677 DynInstPtr inst = std::move(insts_to_decode.front()); local
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H A Drename_impl.hh118 .desc("count of cycles rename stalled for serializing inst")
644 DynInstPtr inst = insts_to_rename.front(); local
650 if (inst->isLoad()) {
659 if (inst->isStore() || inst->isAtomic()) {
674 tid, inst->seqNum, inst->pcState());
677 if (inst->isSquashed()) {
681 tid, inst->seqNum, inst
805 DynInstPtr inst = NULL; local
842 const DynInstPtr &inst = fromDecode->insts[i]; local
1066 renameSrcRegs(const DynInstPtr &inst, ThreadID tid) argument
1133 renameDestRegs(const DynInstPtr &inst, ThreadID tid) argument
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/gem5/src/arch/power/
H A Ddecoder.hh68 moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) argument
70 emi = inst;
H A Dstacktrace.cc73 StackTrace::StackTrace(ThreadContext *_tc, const StaticInstPtr &inst) argument
98 StackTrace::decodeStack(MachInst inst, int &disp) argument
105 StackTrace::decodeSave(MachInst inst, int &reg, int &disp) argument
/gem5/src/arch/mips/
H A Ddecoder.hh69 moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) argument
71 emi = inst;
H A Dfaults.hh105 void invoke(ThreadContext * tc, const StaticInstPtr &inst =
137 void invoke(ThreadContext * tc, const StaticInstPtr &inst =
145 void invoke(ThreadContext * tc, const StaticInstPtr &inst =
152 void invoke(ThreadContext * tc, const StaticInstPtr &inst =
165 invoke(ThreadContext * tc, const StaticInstPtr &inst =
168 MipsFault<CoprocessorUnusableFault>::invoke(tc, inst);
200 invoke(ThreadContext * tc, const StaticInstPtr &inst =
203 MipsFault<T>::invoke(tc, inst);
253 invoke(ThreadContext * tc, const StaticInstPtr &inst =
262 AddressFault<T>::invoke(tc, inst);
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/gem5/src/cpu/
H A Dprofile.hh76 ProfileNode *consume(ThreadContext *tc, const StaticInstPtr &inst);
84 FunctionProfile::consume(ThreadContext *tc, const StaticInstPtr &inst) argument
86 if (!trace.trace(tc, inst))
/gem5/src/cpu/pred/
H A Dbpred_unit.cc172 BPredUnit::predict(const StaticInstPtr &inst, const InstSeqNum &seqNum, argument
189 if (inst->isUncondCtrl()) {
215 bp_history, indirect_history, tid, inst);
219 if (inst->isReturn()) {
240 if (inst->isCall()) {
254 if (inst->isDirectCtrl() || !iPred) {
271 if (!inst->isCall() && !inst->isReturn()) {
277 } else if (inst->isCall() && !inst
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H A Dbpred_unit.hh89 * @param inst The branch instruction.
94 bool predict(const StaticInstPtr &inst, const InstSeqNum &seqNum,
178 * @param inst Static instruction information
185 const StaticInstPtr & inst = StaticInst::nullStaticInstPtr,
207 const StaticInstPtr & inst)
212 inst(inst)
266 const StaticInstPtr inst; member in struct:BPredUnit::PredictorHistory
204 PredictorHistory(const InstSeqNum &seq_num, Addr instPC, bool pred_taken, void *bp_history, void *indirect_history, ThreadID _tid, const StaticInstPtr & inst) argument
/gem5/src/arch/x86/
H A Dstacktrace.cc119 StackTrace::StackTrace(ThreadContext *_tc, const StaticInstPtr &inst) argument
122 trace(_tc, inst);
141 StackTrace::decodeStack(MachInst inst, int &disp) argument
148 StackTrace::decodeSave(MachInst inst, int &reg, int &disp) argument
167 MachInst inst = tc->getVirtProxy().read<MachInst>(pc); local
170 if (decodeStack(inst, disp)) {
176 } else if (decodeSave(inst, reg, disp)) {

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