Lines Matching refs:inst
306 DefaultDecode<Impl>::squash(const DynInstPtr &inst, ThreadID tid)
309 "prediction detected at decode.\n", tid, inst->seqNum);
314 toFetch->decodeInfo[tid].mispredictInst = inst;
316 toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum;
317 toFetch->decodeInfo[tid].nextPC = inst->branchTarget();
318 toFetch->decodeInfo[tid].branchTaken = inst->pcState().branching();
319 toFetch->decodeInfo[tid].squashInst = inst;
324 InstSeqNum squash_seq_num = inst->seqNum;
408 DynInstPtr inst = NULL;
411 inst = insts[tid].front();
415 assert(tid == inst->threadNumber);
417 skidBuffer[tid].push(inst);
420 inst->threadNumber, inst->seqNum, inst->pcState(), skidBuffer[tid].size());
677 DynInstPtr inst = std::move(insts_to_decode.front());
682 "PC %s\n", tid, inst->seqNum, inst->pcState());
684 if (inst->isSquashed()) {
687 tid, inst->seqNum, inst->pcState());
700 if (inst->numSrcRegs() == 0) {
701 inst->setCanIssue();
707 toRename->insts[toRenameIndex] = inst;
716 inst->decodeTick = curTick() - inst->fetchTick;
722 if (inst->readPredTaken() && !inst->isControl()) {
729 squash(inst, inst->threadNumber);
737 if (inst->isDirectCtrl() &&
738 (inst->isUncondCtrl() || inst->readPredTaken()))
742 if (!(inst->branchTarget() == inst->readPredTarg())) {
747 squash(inst, inst->threadNumber);
748 TheISA::PCState target = inst->branchTarget();
753 tid, inst->seqNum, target);
755 inst->setPredTarg(target);