Searched refs:SimObject (Results 101 - 125 of 357) sorted by relevance

1234567891011>>

/gem5/src/mem/ruby/structures/
H A DRubyCache.py33 from m5.SimObject import SimObject
35 class RubyCache(SimObject):
/gem5/src/cpu/testers/directedtest/
H A DRubyDirectedTester.py29 from m5.SimObject import SimObject
35 class DirectedGenerator(SimObject):
H A DDirectedGenerator.hh37 class DirectedGenerator : public SimObject
H A DDirectedGenerator.cc35 : SimObject(p),
/gem5/src/cpu/minor/
H A Dfunc_unit.hh61 class MinorOpClass : public SimObject
68 SimObject(params),
74 class MinorOpClassSet : public SimObject
95 class MinorFUTiming: public SimObject
149 class MinorFU : public SimObject
171 SimObject(params),
181 class MinorFUPool : public SimObject
188 SimObject(params),
/gem5/src/arch/power/
H A Dinterrupts.hh43 class Interrupts : public SimObject
57 Interrupts(Params * p) : SimObject(p), cpu(NULL)
/gem5/src/arch/arm/tracers/
H A DTarmacTrace.py39 from m5.SimObject import SimObject
/gem5/src/dev/arm/
H A DVirtIOMMIO.py40 from m5.SimObject import SimObject
/gem5/src/dev/pci/
H A DCopyEngine.py29 from m5.SimObject import SimObject
/gem5/src/sim/
H A Demul_driver.hh52 class EmulatedDriver : public SimObject
62 : SimObject(p), filename(p->filename)
H A Dsub_system.hh59 class SubSystem : public SimObject
H A Dredirect_path.hh45 class RedirectPath : public SimObject
/gem5/src/cpu/
H A Dintr_control_noisa.cc37 : SimObject(p), sys(p->sys)
H A Dfunc_unit.hh51 class OpDesc : public SimObject
59 : SimObject(p), opClass(p->opClass), opLat(p->opLat),
63 class FUDesc : public SimObject
70 : SimObject(p), opDescList(p->opList), number(p->count) {};
H A Dintr_control.hh42 class IntrControl : public SimObject
/gem5/src/dev/net/
H A Detherdump.hh47 class EtherDump : public SimObject
/gem5/src/dev/
H A Dplatform.hh52 class Platform : public SimObject
/gem5/src/dev/storage/
H A Dsimple_disk.hh47 class SimpleDisk : public SimObject
/gem5/src/learning_gem5/part2/
H A Dgoodbye_object.hh39 class GoodbyeObject : public SimObject
/gem5/src/cpu/testers/traffic_gen/
H A Dexit_gen.hh59 ExitGen(SimObject &obj, MasterID master_id, Tick _duration)
H A Didle_gen.hh64 IdleGen(SimObject &obj, MasterID master_id, Tick _duration)
/gem5/src/mem/qos/
H A Dpolicy.cc45 : SimObject(p)
/gem5/util/systemc/systemc_within_gem5/systemc_simple_object/
H A Dfeeder.hh49 class Feeder : public SimObject
/gem5/src/cpu/kvm/
H A DX86KvmCPU.py30 from m5.SimObject import *
/gem5/src/python/m5/
H A D__init__.py48 from . import SimObject

Completed in 18 milliseconds

1234567891011>>