1# Copyright (c) 2018 ARM Limited
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24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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35#
36# Authors: Giacomo Gabrielli
37#          Giacomo Travaglini
38
39from m5.SimObject import SimObject
40from m5.params import *
41from m5.objects.InstTracer import InstTracer
42
43class TarmacParser(InstTracer):
44    type = 'TarmacParser'
45    cxx_class = 'Trace::TarmacParser'
46    cxx_header = "arch/arm/tracers/tarmac_parser.hh"
47
48    path_to_trace = Param.String("tarmac.log", "path to TARMAC trace")
49
50    start_pc = Param.Int(
51        0x0, "tracing starts when the PC gets this value; ignored if 0x0")
52
53    exit_on_diff = Param.Bool(False,
54        "stop simulation after first mismatch is detected")
55
56    exit_on_insn_diff = Param.Bool(False,
57        "stop simulation after first mismatch on PC or opcode is detected")
58
59    mem_wr_check = Param.Bool(False,
60        "enable check of memory write accesses")
61
62    cpu_id = Param.Bool(False,
63        "true if trace format includes the CPU id")
64
65    ignore_mem_addr = Param.AddrRange(AddrRange(0, size=0),
66        "Range of unverifiable memory addresses")
67
68class TarmacTracer(InstTracer):
69    type = 'TarmacTracer'
70    cxx_class = 'Trace::TarmacTracer'
71    cxx_header = "arch/arm/tracers/tarmac_tracer.hh"
72
73    start_tick = Param.Tick(0,
74        "tracing starts when the tick time gets this value")
75
76    end_tick = Param.Tick(MaxTick,
77        "tracing ends when the tick time gets this value")
78