Searched refs:MachInst (Results 51 - 69 of 69) sorted by relevance

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/gem5/src/cpu/
H A Dthread_context.hh94 typedef TheISA::MachInst MachInst; typedef in class:ThreadContext
H A Dbase.hh278 // Mask to align PCs to MachInst sized boundaries
279 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
H A Dsimple_thread.hh98 typedef TheISA::MachInst MachInst; typedef in class:SimpleThread
/gem5/src/cpu/o3/
H A Dfetch.hh88 typedef TheISA::MachInst MachInst; typedef in class:DefaultFetch
299 * either next PC+=MachInst or a branch target.
H A Ddyn_inst.hh67 typedef TheISA::MachInst MachInst; typedef in class:BaseO3DynInst
H A Dfetch_impl.hh124 instSize = sizeof(TheISA::MachInst);
1256 TheISA::MachInst *cacheInsts =
1257 reinterpret_cast<TheISA::MachInst *>(fetchBuffer[tid]);
1288 MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]);
/gem5/src/cpu/minor/
H A Dfetch1.cc94 if ((lineSnap % sizeof(TheISA::MachInst)) != 0) {
96 "of sizeof(TheISA::MachInst) (%d)\n", name_,
97 sizeof(TheISA::MachInst));
101 (maxLineWidth % sizeof(TheISA::MachInst)) == 0))
104 " sizeof(TheISA::MachInst)"
106 name_, sizeof(TheISA::MachInst), lineSnap);
155 /* Use a lower, sizeof(MachInst) aligned address for the fetch */
202 ((Addr) (1 << sizeof(TheISA::MachInst)) - 1);
552 /* Set the lineBase, which is a sizeof(MachInst) aligned address <=
H A Dfetch2.cc329 /* Set the inputIndex to be the MachInst-aligned offset
379 TheISA::MachInst inst_word;
383 *(reinterpret_cast<TheISA::MachInst *>
390 DPRINTF(Fetch, "Offering MachInst to decoder addr: 0x%x\n",
395 * instructions longer than sizeof(MachInst) */
471 fetch_info.inputIndex += sizeof(TheISA::MachInst);
/gem5/src/arch/arm/
H A Dtypes.hh54 typedef uint32_t MachInst; typedef in namespace:ArmISA
215 class PCState : public GenericISA::UPCState<MachInst>
219 typedef GenericISA::UPCState<MachInst> Base;
/gem5/src/arch/x86/
H A Ddecoder.cc157 offset = origPC % sizeof(MachInst);
164 if (offset == sizeof(MachInst))
707 const int chunkSize = sizeof(MachInst);
724 MachInst maskVal = mask(size * 8) << (start * 8);
/gem5/src/cpu/checker/
H A Dcpu_impl.hh242 MachInst machInst;
249 sizeof(MachInst), 0, masterId, fetch_PC,
252 mem_req->setVirt(0, fetch_PC, sizeof(MachInst),
312 //MachInst at the current pc.
319 fetchOffset += sizeof(TheISA::MachInst);
H A Dcpu.hh90 typedef TheISA::MachInst MachInst; typedef in class:CheckerCPU
/gem5/src/arch/sparc/
H A Dfaults.cc478 NPC = PC + sizeof(MachInst);
486 NPC = PC + sizeof(MachInst);
496 NPC = PC + sizeof(MachInst);
554 pc.nnpc(NPC + sizeof(MachInst));
597 pc.nnpc(NPC + sizeof(MachInst));
H A Dtlb.cc434 if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) &&
/gem5/src/base/
H A Dremote_gdb.cc748 removeHardBreak(bkpt, sizeof(TheISA::MachInst));
756 insertHardBreak(bkpt, sizeof(TheISA::MachInst));
835 return len == sizeof(MachInst);
/gem5/src/arch/arm/insts/
H A Dstatic_inst.hh532 MachInst
535 return static_cast<MachInst>(machInst & (mask(instSize() * 8)));
/gem5/src/arch/alpha/
H A Dfaults.cc163 MachInst machInst = inst->machInst;
/gem5/src/cpu/simple/
H A Dbase.cc480 req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH,
529 //fetch beyond the MachInst at the current pc.
536 t_info.fetchOffset += sizeof(MachInst);
/gem5/src/gpu-compute/
H A Dhsail_code.cc178 TheGpuISA::MachInst machInst = { instPtr, obj };

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