Searched refs:MachInst (Results 51 - 69 of 69) sorted by relevance
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/gem5/src/cpu/ |
H A D | thread_context.hh | 94 typedef TheISA::MachInst MachInst; typedef in class:ThreadContext
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H A D | base.hh | 278 // Mask to align PCs to MachInst sized boundaries 279 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
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H A D | simple_thread.hh | 98 typedef TheISA::MachInst MachInst; typedef in class:SimpleThread
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/gem5/src/cpu/o3/ |
H A D | fetch.hh | 88 typedef TheISA::MachInst MachInst; typedef in class:DefaultFetch 299 * either next PC+=MachInst or a branch target.
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H A D | dyn_inst.hh | 67 typedef TheISA::MachInst MachInst; typedef in class:BaseO3DynInst
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H A D | fetch_impl.hh | 124 instSize = sizeof(TheISA::MachInst); 1256 TheISA::MachInst *cacheInsts = 1257 reinterpret_cast<TheISA::MachInst *>(fetchBuffer[tid]); 1288 MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]);
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/gem5/src/cpu/minor/ |
H A D | fetch1.cc | 94 if ((lineSnap % sizeof(TheISA::MachInst)) != 0) { 96 "of sizeof(TheISA::MachInst) (%d)\n", name_, 97 sizeof(TheISA::MachInst)); 101 (maxLineWidth % sizeof(TheISA::MachInst)) == 0)) 104 " sizeof(TheISA::MachInst)" 106 name_, sizeof(TheISA::MachInst), lineSnap); 155 /* Use a lower, sizeof(MachInst) aligned address for the fetch */ 202 ((Addr) (1 << sizeof(TheISA::MachInst)) - 1); 552 /* Set the lineBase, which is a sizeof(MachInst) aligned address <=
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H A D | fetch2.cc | 329 /* Set the inputIndex to be the MachInst-aligned offset 379 TheISA::MachInst inst_word; 383 *(reinterpret_cast<TheISA::MachInst *> 390 DPRINTF(Fetch, "Offering MachInst to decoder addr: 0x%x\n", 395 * instructions longer than sizeof(MachInst) */ 471 fetch_info.inputIndex += sizeof(TheISA::MachInst);
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/gem5/src/arch/arm/ |
H A D | types.hh | 54 typedef uint32_t MachInst; typedef in namespace:ArmISA 215 class PCState : public GenericISA::UPCState<MachInst> 219 typedef GenericISA::UPCState<MachInst> Base;
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/gem5/src/arch/x86/ |
H A D | decoder.cc | 157 offset = origPC % sizeof(MachInst); 164 if (offset == sizeof(MachInst)) 707 const int chunkSize = sizeof(MachInst); 724 MachInst maskVal = mask(size * 8) << (start * 8);
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/gem5/src/cpu/checker/ |
H A D | cpu_impl.hh | 242 MachInst machInst; 249 sizeof(MachInst), 0, masterId, fetch_PC, 252 mem_req->setVirt(0, fetch_PC, sizeof(MachInst), 312 //MachInst at the current pc. 319 fetchOffset += sizeof(TheISA::MachInst);
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H A D | cpu.hh | 90 typedef TheISA::MachInst MachInst; typedef in class:CheckerCPU
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/gem5/src/arch/sparc/ |
H A D | faults.cc | 478 NPC = PC + sizeof(MachInst); 486 NPC = PC + sizeof(MachInst); 496 NPC = PC + sizeof(MachInst); 554 pc.nnpc(NPC + sizeof(MachInst)); 597 pc.nnpc(NPC + sizeof(MachInst));
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H A D | tlb.cc | 434 if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) &&
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/gem5/src/base/ |
H A D | remote_gdb.cc | 748 removeHardBreak(bkpt, sizeof(TheISA::MachInst)); 756 insertHardBreak(bkpt, sizeof(TheISA::MachInst)); 835 return len == sizeof(MachInst);
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/gem5/src/arch/arm/insts/ |
H A D | static_inst.hh | 532 MachInst 535 return static_cast<MachInst>(machInst & (mask(instSize() * 8)));
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/gem5/src/arch/alpha/ |
H A D | faults.cc | 163 MachInst machInst = inst->machInst;
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/gem5/src/cpu/simple/ |
H A D | base.cc | 480 req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, 529 //fetch beyond the MachInst at the current pc. 536 t_info.fetchOffset += sizeof(MachInst);
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/gem5/src/gpu-compute/ |
H A D | hsail_code.cc | 178 TheGpuISA::MachInst machInst = { instPtr, obj };
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