Searched refs:BaseTLB (Results 26 - 50 of 75) sorted by relevance
123
| /gem5/src/arch/arm/ |
| H A D | isa.cc | 1663 BaseTLB::Mode mode = BaseTLB::Read;
1670 mode = BaseTLB::Read;
1675 mode = BaseTLB::Write;
1680 mode = BaseTLB::Read;
1685 mode = BaseTLB::Write;
1692 mode = BaseTLB::Read;
1699 mode = BaseTLB::Write;
1706 mode = BaseTLB::Read;
1713 mode = BaseTLB
[all...] |
| H A D | stage2_lookup.cc | 82 Stage2LookUp::mergeTe(const RequestPtr &req, BaseTLB::Mode mode)
180 ThreadContext *tc, BaseTLB::Mode mode)
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| H A D | tlb.hh | 81 BaseTLB::Mode mode,
97 Addr is_priv, BaseTLB::Mode mode,
102 class TLB : public BaseTLB
219 void takeOverFrom(BaseTLB *otlb) override;
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| /gem5/src/cpu/minor/ |
| H A D | fetch1.hh | 102 public BaseTLB::Translation, /* For TLB lookups */
157 /** BaseTLB::Translation interface */
167 ThreadContext *tc, BaseTLB::Mode mode);
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| H A D | lsq.hh | 121 public BaseTLB::Translation, /* For TLB lookups */
188 /** BaseTLB::Translation interface */
283 ThreadContext *tc, BaseTLB::Mode mode)
344 ThreadContext *tc, BaseTLB::Mode mode);
417 ThreadContext *tc, BaseTLB::Mode mode);
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| /gem5/src/cpu/ |
| H A D | simple_thread.hh | 131 BaseTLB *itb;
132 BaseTLB *dtb;
139 BaseTLB *_itb, BaseTLB *_dtb, TheISA::ISA *_isa,
143 Process *_process, BaseTLB *_itb, BaseTLB *_dtb,
200 BaseTLB *getITBPtr() override { return itb; }
202 BaseTLB *getDTBPtr() override { return dtb; }
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| H A D | thread_context.hh | 64 class BaseTLB;
137 virtual BaseTLB *getITBPtr() = 0;
139 virtual BaseTLB *getDTBPtr() = 0;
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| /gem5/src/arch/sparc/ |
| H A D | tlb.hh | 52 class TLB : public BaseTLB
161 void takeOverFrom(BaseTLB *otlb) override {}
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| /gem5/src/gpu-compute/ |
| H A D | shader.cc | 236 BaseTLB::Mode trans_mode;
239 trans_mode = BaseTLB::Read;
241 trans_mode = BaseTLB::Write;
384 Shader::functionalTLBAccess(PacketPtr pkt, int cu_id, BaseTLB::Mode mode)
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| H A D | tlb_coalescer.hh | 57 class BaseTLB;
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| H A D | fetch_unit.cc | 164 new TheISA::GpuTLB::TranslationState(BaseTLB::Execute,
191 new TheISA::GpuTLB::TranslationState(BaseTLB::Execute,
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| H A D | gpu_tlb.hh | 59 class BaseTLB;
98 typedef enum BaseTLB::Mode Mode;
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| /gem5/src/arch/x86/ |
| H A D | faults.hh | 322 PageFault(Addr _addr, bool present, BaseTLB::Mode mode,
328 code.write = (mode == BaseTLB::Write);
331 code.fetch = (mode == BaseTLB::Execute);
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| H A D | pagetable_walker.cc | 70 Walker::start(ThreadContext * _tc, BaseTLB::Translation *_translation,
71 const RequestPtr &_req, BaseTLB::Mode _mode)
96 BaseTLB::Mode _mode)
181 BaseTLB::Mode _mode, bool _isTiming)
297 bool badNX = pte.nx && mode == BaseTLB::Execute && enableNX;
734 if (mode == BaseTLB::Execute && !enableNX)
735 mode = BaseTLB::Read;
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| H A D | remote_gdb.cc | 79 BaseTLB::Read);
88 BaseTLB::Read);
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| /gem5/src/cpu/o3/ |
| H A D | fetch.hh | 115 class FetchTranslation : public BaseTLB::Translation
131 BaseTLB::Mode mode)
133 assert(mode == BaseTLB::Execute);
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| /gem5/src/cpu/simple/ |
| H A D | timing.cc | 430 BaseTLB::Mode mode = BaseTLB::Read;
508 BaseTLB::Mode mode = BaseTLB::Write;
576 BaseTLB::Mode mode = BaseTLB::Write;
642 state->mode == BaseTLB::Read);
645 state->data, state->mode == BaseTLB::Read);
685 &fetchTranslation, BaseTLB::Execute);
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| H A D | timing.hh | 109 class FetchTranslation : public BaseTLB::Translation
128 BaseTLB::Mode mode)
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| H A D | atomic.cc | 402 BaseTLB::Read);
493 BaseTLB::Write);
603 BaseTLB::Write);
680 BaseTLB::Execute);
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| /gem5/src/arch/mips/ |
| H A D | tlb.cc | 64 : BaseTLB(p), size(p->size), nlu(0)
230 BaseTLB::regStats();
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| /gem5/src/arch/power/ |
| H A D | tlb.cc | 68 : BaseTLB(p), size(p->size), nlu(0)
227 BaseTLB::regStats();
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| /gem5/src/cpu/checker/ |
| H A D | cpu.cc | 201 fault = dtb->translateFunctional(mem_req, tc, BaseTLB::Read);
285 fault = dtb->translateFunctional(mem_req, tc, BaseTLB::Write);
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| H A D | cpu.hh | 65 class BaseTLB;
137 BaseTLB *itb;
138 BaseTLB *dtb;
160 BaseTLB* getITBPtr() { return itb; }
161 BaseTLB* getDTBPtr() { return dtb; }
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| /gem5/src/mem/cache/prefetch/ |
| H A D | queued.cc | 73 QueuedPrefetcher::DeferredPacket::startTranslation(BaseTLB *tlb)
79 tlb->translateTiming(translationRequest, tc, this, BaseTLB::Read);
85 const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode)
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| /gem5/src/arch/riscv/ |
| H A D | tlb.cc | 66 : BaseTLB(p), size(p->size), nlu(0)
232 BaseTLB::regStats();
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