Searched hist:56 (Results 351 - 375 of 501) sorted by relevance
/gem5/tests/long/se/70.twolf/ref/arm/linux/o3-timing/ | ||
H A D | stats.txt | diff 9978:81d7551dd3be Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller. |
/gem5/tests/long/se/70.twolf/ref/x86/linux/o3-timing/ | ||
H A D | stats.txt | diff 9978:81d7551dd3be Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller. |
/gem5/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/ | ||
H A D | stats.txt | diff 9978:81d7551dd3be Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller. |
/gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing/ | ||
H A D | stats.txt | diff 9978:81d7551dd3be Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller. |
/gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/ | ||
H A D | stats.txt | diff 9978:81d7551dd3be Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller. |
/gem5/tests/quick/se/00.hello/ref/mips/linux/o3-timing/ | ||
H A D | stats.txt | diff 9978:81d7551dd3be Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller. |
/gem5/tests/quick/se/00.hello/ref/power/linux/o3-timing/ | ||
H A D | stats.txt | diff 9978:81d7551dd3be Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller. |
/gem5/tests/quick/se/00.hello/ref/x86/linux/o3-timing/ | ||
H A D | stats.txt | diff 9978:81d7551dd3be Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller. |
/gem5/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/ | ||
H A D | stats.txt | diff 9978:81d7551dd3be Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller. |
/gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/ | ||
H A D | stats.txt | diff 9978:81d7551dd3be Fri Nov 01 11:56:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats to match DRAM controller changes This patch encompasses all the stats updates needed to reflect the changes to the DRAM controller. |
/gem5/src/arch/x86/ | ||
H A D | SConscript | diff 4159:a3cc632b33d8 Mon Mar 05 12:56:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Add some new source files. |
H A D | faults.cc | diff 6049:595b5016f6d5 Sun Apr 19 05:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement the STARTUP IPI. |
/gem5/src/systemc/core/ | ||
H A D | sc_main.cc | diff 13212:4729f211fbae Sat Sep 15 00:56:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Warn if sc_stop is called more than once. Change-Id: Ief88b9af0119ba4b007f79905db2522b5f95b820 Reviewed-on: https://gem5-review.googlesource.com/c/12811 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
/gem5/src/arch/alpha/isa/ | ||
H A D | branch.isa | diff 9552:460cf901acba Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for overloaded virtual functions A derived function with a different signature than a base class function will result in the base class function of the same name being hidden. The parameter list and return type for the member function in the derived class must match those of the member function in the base class, otherwise the function in the derived class will hide the function in the base class and no polymorphic behaviour will occur. This patch addresses these warnings by ensuring a unique function name to avoid (unintentionally) hiding any functions. |
/gem5/src/arch/arm/isa/templates/ | ||
H A D | mem.isa | diff 8444:56de1f9320df Sun Jul 03 01:35:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem. readBytes and writeBytes had the word "bytes" in their names because they accessed blobs of bytes. This distinguished them from the read and write functions which handled higher level data types. Because those functions don't exist any more, this change renames readBytes and writeBytes to more general names, readMem and writeMem, which reflect the fact that they are how you read and write memory. This also makes their names more consistent with the register reading/writing functions, although those are still read and set for some reason. |
/gem5/src/arch/mips/isa/formats/ | ||
H A D | branch.isa | diff 9552:460cf901acba Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for overloaded virtual functions A derived function with a different signature than a base class function will result in the base class function of the same name being hidden. The parameter list and return type for the member function in the derived class must match those of the member function in the base class, otherwise the function in the derived class will hide the function in the base class and no polymorphic behaviour will occur. This patch addresses these warnings by ensuring a unique function name to avoid (unintentionally) hiding any functions. |
H A D | fp.isa | diff 9554:406fbcf60223 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for missing declarations This patch enables warnings for missing declarations. To avoid issues with SWIG-generated code, the warning is only applied to non-SWIG code. |
/gem5/src/cpu/testers/rubytest/ | ||
H A D | Check.cc | diff 9542:683991c46ac8 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> mem: Add predecessor to SenderState base class This patch adds a predecessor field to the SenderState base class to make the process of linking them up more uniform, and enable a traversal of the stack without knowing the specific type of the subclasses. There are a number of simplifications done as part of changing the SenderState, particularly in the RubyTest. |
/gem5/src/dev/arm/ | ||
H A D | pl111.cc | diff 9806:3f262c18ad5d Thu Jul 11 22:56:00 EDT 2013 Steve Reinhardt <stever@gmail.com> dev/arm: get rid of AmbaDev namespace It was confusing having an AmbaDev namespace along with an AmbaDevice class. The namespace stuff is now moved in to a new base AmbaDevice class, which is a mixin for classes AmbaPioDevice (the former AmbaDevice) and AmbaDmaDevice to provide the readId function as an inherited member function. Committed by: Nilay Vaish <nilay@cs.wisc.edu> |
/gem5/configs/example/ | ||
H A D | ruby_mem_test.py | diff 9120:48eeef8a0997 Thu Jul 12 00:56:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> Mem: Make SimpleMemory single ported This patch changes the simple memory to have a single slave port rather than a vector port. The simple memory makes no attempts at modelling the contention between multiple ports, and any such multiplexing and demultiplexing could be done in a bus (or crossbar) outside the memory controller. This scenario also matches with the ongoing work on a SimpleDRAM model, which will be a single-ported single-channel controller that can be used in conjunction with a bus (or crossbar) to create a multi-port multi-channel controller. There are only very few regressions that make use of the vector port, and these are all for functional accesses only. To facilitate these cases, memtest and memtest-ruby have been updated to also have a "functional" bus to perform the (de)multiplexing of the functional memory accesses. |
/gem5/configs/common/ | ||
H A D | CpuConfig.py | diff 12941:24771c7aee2e Tue Aug 28 06:56:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> config: Move KVM CPU checking to CpuConfig helper module Both se.py and fs.py need to check if a CPU is a KVM CPU. This is somewhat involved since CPUs can be disabled at compile time. Enable better code reuse by moving it to the CpuConfig module. Change-Id: I47b1512ecb62e757399a407a0e41be83b9f83be3 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12418 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
/gem5/src/arch/mips/ | ||
H A D | utility.hh | diff 4194:af4f6022394b Fri Mar 09 16:56:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> implement ipi stufff for SPARC src/arch/alpha/utility.hh: src/arch/mips/utility.hh: src/arch/sparc/utility.hh: src/arch/x86/utility.hh: add hook for system to startup the cpu or not... in the case of FS sparc, only the first cpu would get spunup.. the rest sit in an idle state until they get an ipi src/arch/sparc/isa/decoder.isa: handle writable bits of strandstatus register in miscregfile src/arch/sparc/miscregfile.hh: some constants for the strand status register src/arch/sparc/ua2005.cc: properly implement the strand status register src/dev/sparc/iob.cc: implement ipi generation properly src/sim/system.cc: call into the ISA to start the CPU (or not) |
H A D | process.hh | diff 9552:460cf901acba Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for overloaded virtual functions A derived function with a different signature than a base class function will result in the base class function of the same name being hidden. The parameter list and return type for the member function in the derived class must match those of the member function in the base class, otherwise the function in the derived class will hide the function in the base class and no polymorphic behaviour will occur. This patch addresses these warnings by ensuring a unique function name to avoid (unintentionally) hiding any functions. |
/gem5/src/arch/sparc/isa/ | ||
H A D | decoder.isa | diff 4194:af4f6022394b Fri Mar 09 16:56:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> implement ipi stufff for SPARC src/arch/alpha/utility.hh: src/arch/mips/utility.hh: src/arch/sparc/utility.hh: src/arch/x86/utility.hh: add hook for system to startup the cpu or not... in the case of FS sparc, only the first cpu would get spunup.. the rest sit in an idle state until they get an ipi src/arch/sparc/isa/decoder.isa: handle writable bits of strandstatus register in miscregfile src/arch/sparc/miscregfile.hh: some constants for the strand status register src/arch/sparc/ua2005.cc: properly implement the strand status register src/dev/sparc/iob.cc: implement ipi generation properly src/sim/system.cc: call into the ISA to start the CPU (or not) diff 3821:07d1f7105924 Mon Dec 04 19:56:00 EST 2006 Gabe Black <gblack@eecs.umich.edu> Merge zizzer:/bk/sparcfs into zower.eecs.umich.edu:/eecshome/m5/newmemmid diff 3525:613ea72b766c Fri Nov 03 10:56:00 EST 2006 Gabe Black <gblack@eecs.umich.edu> Add the syscall number as the second parameter for the trap fault. This could be improved and syscalls could be called from the trap's invoke method. diff 2996:56a278b5dbfa Tue Aug 15 19:17:00 EDT 2006 Gabe Black <gblack@eecs.umich.edu> Tweaks to Ali's changes |
/gem5/src/arch/sparc/ | ||
H A D | process.hh | diff 9552:460cf901acba Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for overloaded virtual functions A derived function with a different signature than a base class function will result in the base class function of the same name being hidden. The parameter list and return type for the member function in the derived class must match those of the member function in the base class, otherwise the function in the derived class will hide the function in the base class and no polymorphic behaviour will occur. This patch addresses these warnings by ensuring a unique function name to avoid (unintentionally) hiding any functions. |
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