17119Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27119Sgblack@eecs.umich.edu 312110SRekai.GonzalezAlberquilla@arm.com// Copyright (c) 2010, 2012, 2014, 2016 ARM Limited 47120Sgblack@eecs.umich.edu// All rights reserved 57120Sgblack@eecs.umich.edu// 67120Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77120Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87120Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97120Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107120Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117120Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127120Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137120Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147120Sgblack@eecs.umich.edu// 157119Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Florida State University 167119Sgblack@eecs.umich.edu// All rights reserved. 177119Sgblack@eecs.umich.edu// 187119Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 197119Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 207119Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 217119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 227119Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 237119Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 247119Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 257119Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 267119Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 277119Sgblack@eecs.umich.edu// this software without specific prior written permission. 287119Sgblack@eecs.umich.edu// 297119Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307119Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 317119Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 327119Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 337119Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 347119Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 357119Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 367119Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 377119Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 387119Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 397119Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 407119Sgblack@eecs.umich.edu// 417119Sgblack@eecs.umich.edu// Authors: Stephen Hines 427119Sgblack@eecs.umich.edu 437119Sgblack@eecs.umich.edu 447646Sgene.wu@arm.comdef template PanicExecute {{ 4512234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 467646Sgene.wu@arm.com Trace::InstRecord *traceData) const 477646Sgene.wu@arm.com { 487646Sgene.wu@arm.com panic("Execute function executed when it shouldn't be!\n"); 497646Sgene.wu@arm.com return NoFault; 507646Sgene.wu@arm.com } 517646Sgene.wu@arm.com}}; 527646Sgene.wu@arm.com 537646Sgene.wu@arm.comdef template PanicInitiateAcc {{ 5412234Sgabeblack@google.com Fault %(class_name)s::initiateAcc(ExecContext *xc, 557646Sgene.wu@arm.com Trace::InstRecord *traceData) const 567646Sgene.wu@arm.com { 577646Sgene.wu@arm.com panic("InitiateAcc function executed when it shouldn't be!\n"); 587646Sgene.wu@arm.com return NoFault; 597646Sgene.wu@arm.com } 607646Sgene.wu@arm.com}}; 617646Sgene.wu@arm.com 627646Sgene.wu@arm.comdef template PanicCompleteAcc {{ 6312234Sgabeblack@google.com Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, 647646Sgene.wu@arm.com Trace::InstRecord *traceData) const 657646Sgene.wu@arm.com { 667646Sgene.wu@arm.com panic("CompleteAcc function executed when it shouldn't be!\n"); 677646Sgene.wu@arm.com return NoFault; 687646Sgene.wu@arm.com } 697646Sgene.wu@arm.com}}; 707646Sgene.wu@arm.com 717646Sgene.wu@arm.com 727205Sgblack@eecs.umich.edudef template SwapExecute {{ 7312234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 747205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 757205Sgblack@eecs.umich.edu { 767205Sgblack@eecs.umich.edu Addr EA; 777205Sgblack@eecs.umich.edu Fault fault = NoFault; 787205Sgblack@eecs.umich.edu 797205Sgblack@eecs.umich.edu %(op_decl)s; 807205Sgblack@eecs.umich.edu uint64_t memData = 0; 817205Sgblack@eecs.umich.edu %(op_rd)s; 827205Sgblack@eecs.umich.edu %(ea_code)s; 837205Sgblack@eecs.umich.edu 847205Sgblack@eecs.umich.edu if (%(predicate_test)s) 857205Sgblack@eecs.umich.edu { 867205Sgblack@eecs.umich.edu %(preacc_code)s; 877205Sgblack@eecs.umich.edu 887205Sgblack@eecs.umich.edu if (fault == NoFault) { 898442Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 908442Sgblack@eecs.umich.edu &memData); 917205Sgblack@eecs.umich.edu } 927205Sgblack@eecs.umich.edu 937205Sgblack@eecs.umich.edu if (fault == NoFault) { 947205Sgblack@eecs.umich.edu %(postacc_code)s; 957205Sgblack@eecs.umich.edu } 967205Sgblack@eecs.umich.edu 977205Sgblack@eecs.umich.edu if (fault == NoFault) { 987205Sgblack@eecs.umich.edu %(op_wb)s; 997205Sgblack@eecs.umich.edu } 1007597Sminkyu.jeong@arm.com } else { 1017597Sminkyu.jeong@arm.com xc->setPredicate(false); 1027205Sgblack@eecs.umich.edu } 1037205Sgblack@eecs.umich.edu 1047205Sgblack@eecs.umich.edu return fault; 1057205Sgblack@eecs.umich.edu } 1067205Sgblack@eecs.umich.edu}}; 1077205Sgblack@eecs.umich.edu 1087205Sgblack@eecs.umich.edudef template SwapInitiateAcc {{ 10912234Sgabeblack@google.com Fault %(class_name)s::initiateAcc(ExecContext *xc, 1107205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1117205Sgblack@eecs.umich.edu { 1127205Sgblack@eecs.umich.edu Addr EA; 1137205Sgblack@eecs.umich.edu Fault fault = NoFault; 1147205Sgblack@eecs.umich.edu 1157205Sgblack@eecs.umich.edu %(op_decl)s; 1167205Sgblack@eecs.umich.edu uint64_t memData = 0; 1177205Sgblack@eecs.umich.edu %(op_rd)s; 1187205Sgblack@eecs.umich.edu %(ea_code)s; 1197205Sgblack@eecs.umich.edu 1207205Sgblack@eecs.umich.edu if (%(predicate_test)s) 1217205Sgblack@eecs.umich.edu { 1227205Sgblack@eecs.umich.edu %(preacc_code)s; 1237205Sgblack@eecs.umich.edu 1247205Sgblack@eecs.umich.edu if (fault == NoFault) { 1258442Sgblack@eecs.umich.edu fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 1268442Sgblack@eecs.umich.edu &memData); 1277205Sgblack@eecs.umich.edu } 1287597Sminkyu.jeong@arm.com } else { 1297597Sminkyu.jeong@arm.com xc->setPredicate(false); 1307205Sgblack@eecs.umich.edu } 1317205Sgblack@eecs.umich.edu 1327205Sgblack@eecs.umich.edu return fault; 1337205Sgblack@eecs.umich.edu } 1347205Sgblack@eecs.umich.edu}}; 1357205Sgblack@eecs.umich.edu 1367205Sgblack@eecs.umich.edudef template SwapCompleteAcc {{ 13712234Sgabeblack@google.com Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, 1387205Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1397205Sgblack@eecs.umich.edu { 1407205Sgblack@eecs.umich.edu Fault fault = NoFault; 1417205Sgblack@eecs.umich.edu 1427205Sgblack@eecs.umich.edu %(op_decl)s; 1437205Sgblack@eecs.umich.edu %(op_rd)s; 1447205Sgblack@eecs.umich.edu 1457205Sgblack@eecs.umich.edu if (%(predicate_test)s) 1467205Sgblack@eecs.umich.edu { 1477205Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 1488442Sgblack@eecs.umich.edu getMem(pkt, Mem, traceData); 1498442Sgblack@eecs.umich.edu uint64_t memData = Mem; 1507205Sgblack@eecs.umich.edu 1517205Sgblack@eecs.umich.edu %(postacc_code)s; 1527205Sgblack@eecs.umich.edu 1537205Sgblack@eecs.umich.edu if (fault == NoFault) { 1547205Sgblack@eecs.umich.edu %(op_wb)s; 1557205Sgblack@eecs.umich.edu } 1567205Sgblack@eecs.umich.edu } 1577205Sgblack@eecs.umich.edu 1587205Sgblack@eecs.umich.edu return fault; 1597205Sgblack@eecs.umich.edu } 1607205Sgblack@eecs.umich.edu}}; 1617205Sgblack@eecs.umich.edu 1627119Sgblack@eecs.umich.edudef template LoadExecute {{ 16312234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 1647119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1657119Sgblack@eecs.umich.edu { 1667119Sgblack@eecs.umich.edu Addr EA; 1677119Sgblack@eecs.umich.edu Fault fault = NoFault; 1687119Sgblack@eecs.umich.edu 1697119Sgblack@eecs.umich.edu %(op_decl)s; 1707119Sgblack@eecs.umich.edu %(op_rd)s; 1717119Sgblack@eecs.umich.edu %(ea_code)s; 1727119Sgblack@eecs.umich.edu 1737119Sgblack@eecs.umich.edu if (%(predicate_test)s) 1747119Sgblack@eecs.umich.edu { 1757119Sgblack@eecs.umich.edu if (fault == NoFault) { 1768442Sgblack@eecs.umich.edu fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); 1777119Sgblack@eecs.umich.edu %(memacc_code)s; 1787119Sgblack@eecs.umich.edu } 1797119Sgblack@eecs.umich.edu 1807119Sgblack@eecs.umich.edu if (fault == NoFault) { 1817119Sgblack@eecs.umich.edu %(op_wb)s; 1827119Sgblack@eecs.umich.edu } 1837597Sminkyu.jeong@arm.com } else { 1847597Sminkyu.jeong@arm.com xc->setPredicate(false); 1857119Sgblack@eecs.umich.edu } 1867119Sgblack@eecs.umich.edu 1877119Sgblack@eecs.umich.edu return fault; 1887119Sgblack@eecs.umich.edu } 1897119Sgblack@eecs.umich.edu}}; 1907119Sgblack@eecs.umich.edu 1917639Sgblack@eecs.umich.edudef template NeonLoadExecute {{ 1927639Sgblack@eecs.umich.edu template <class Element> 1937639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::execute( 19412234Sgabeblack@google.com ExecContext *xc, Trace::InstRecord *traceData) const 1957639Sgblack@eecs.umich.edu { 1967639Sgblack@eecs.umich.edu Addr EA; 1977639Sgblack@eecs.umich.edu Fault fault = NoFault; 1987639Sgblack@eecs.umich.edu 1997639Sgblack@eecs.umich.edu %(op_decl)s; 2007639Sgblack@eecs.umich.edu %(mem_decl)s; 2017639Sgblack@eecs.umich.edu %(op_rd)s; 2027639Sgblack@eecs.umich.edu %(ea_code)s; 2037639Sgblack@eecs.umich.edu 2047639Sgblack@eecs.umich.edu MemUnion memUnion; 2057639Sgblack@eecs.umich.edu uint8_t *dataPtr = memUnion.bytes; 2067639Sgblack@eecs.umich.edu 2077639Sgblack@eecs.umich.edu if (%(predicate_test)s) 2087639Sgblack@eecs.umich.edu { 2097639Sgblack@eecs.umich.edu if (fault == NoFault) { 2108444Sgblack@eecs.umich.edu fault = xc->readMem(EA, dataPtr, %(size)d, memAccessFlags); 2117639Sgblack@eecs.umich.edu %(memacc_code)s; 2127639Sgblack@eecs.umich.edu } 2137639Sgblack@eecs.umich.edu 2147639Sgblack@eecs.umich.edu if (fault == NoFault) { 2157639Sgblack@eecs.umich.edu %(op_wb)s; 2167639Sgblack@eecs.umich.edu } 2178072SGiacomo.Gabrielli@arm.com } else { 2188072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 2197639Sgblack@eecs.umich.edu } 2207639Sgblack@eecs.umich.edu 2217639Sgblack@eecs.umich.edu return fault; 2227639Sgblack@eecs.umich.edu } 2237639Sgblack@eecs.umich.edu}}; 2247639Sgblack@eecs.umich.edu 2257120Sgblack@eecs.umich.edudef template StoreExecute {{ 22612234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 2277120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2287120Sgblack@eecs.umich.edu { 2297120Sgblack@eecs.umich.edu Addr EA; 2307120Sgblack@eecs.umich.edu Fault fault = NoFault; 2317120Sgblack@eecs.umich.edu 2327120Sgblack@eecs.umich.edu %(op_decl)s; 2337120Sgblack@eecs.umich.edu %(op_rd)s; 2347120Sgblack@eecs.umich.edu %(ea_code)s; 2357120Sgblack@eecs.umich.edu 2367120Sgblack@eecs.umich.edu if (%(predicate_test)s) 2377120Sgblack@eecs.umich.edu { 2387120Sgblack@eecs.umich.edu if (fault == NoFault) { 2397120Sgblack@eecs.umich.edu %(memacc_code)s; 2407120Sgblack@eecs.umich.edu } 2417120Sgblack@eecs.umich.edu 2427120Sgblack@eecs.umich.edu if (fault == NoFault) { 2438442Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, 2448442Sgblack@eecs.umich.edu memAccessFlags, NULL); 2457120Sgblack@eecs.umich.edu } 2467120Sgblack@eecs.umich.edu 2477120Sgblack@eecs.umich.edu if (fault == NoFault) { 2487120Sgblack@eecs.umich.edu %(op_wb)s; 2497120Sgblack@eecs.umich.edu } 2507597Sminkyu.jeong@arm.com } else { 2517597Sminkyu.jeong@arm.com xc->setPredicate(false); 2527120Sgblack@eecs.umich.edu } 2537120Sgblack@eecs.umich.edu 2547120Sgblack@eecs.umich.edu return fault; 2557120Sgblack@eecs.umich.edu } 2567120Sgblack@eecs.umich.edu}}; 2577120Sgblack@eecs.umich.edu 2587639Sgblack@eecs.umich.edudef template NeonStoreExecute {{ 2597639Sgblack@eecs.umich.edu template <class Element> 2607639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::execute( 26112234Sgabeblack@google.com ExecContext *xc, Trace::InstRecord *traceData) const 2627639Sgblack@eecs.umich.edu { 2637639Sgblack@eecs.umich.edu Addr EA; 2647639Sgblack@eecs.umich.edu Fault fault = NoFault; 2657639Sgblack@eecs.umich.edu 2667639Sgblack@eecs.umich.edu %(op_decl)s; 2677639Sgblack@eecs.umich.edu %(mem_decl)s; 2687639Sgblack@eecs.umich.edu %(op_rd)s; 2697639Sgblack@eecs.umich.edu %(ea_code)s; 2707639Sgblack@eecs.umich.edu 2717639Sgblack@eecs.umich.edu MemUnion memUnion; 2727639Sgblack@eecs.umich.edu uint8_t *dataPtr = memUnion.bytes; 2737639Sgblack@eecs.umich.edu 2747639Sgblack@eecs.umich.edu if (%(predicate_test)s) 2757639Sgblack@eecs.umich.edu { 2767639Sgblack@eecs.umich.edu if (fault == NoFault) { 2777639Sgblack@eecs.umich.edu %(memacc_code)s; 2787639Sgblack@eecs.umich.edu } 2797639Sgblack@eecs.umich.edu 2807639Sgblack@eecs.umich.edu if (fault == NoFault) { 2818444Sgblack@eecs.umich.edu fault = xc->writeMem(dataPtr, %(size)d, EA, 2828444Sgblack@eecs.umich.edu memAccessFlags, NULL); 2837639Sgblack@eecs.umich.edu } 2847639Sgblack@eecs.umich.edu 2857639Sgblack@eecs.umich.edu if (fault == NoFault) { 2867639Sgblack@eecs.umich.edu %(op_wb)s; 2877639Sgblack@eecs.umich.edu } 2888072SGiacomo.Gabrielli@arm.com } else { 2898072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 2907639Sgblack@eecs.umich.edu } 2917639Sgblack@eecs.umich.edu 2927639Sgblack@eecs.umich.edu return fault; 2937639Sgblack@eecs.umich.edu } 2947639Sgblack@eecs.umich.edu}}; 2957639Sgblack@eecs.umich.edu 2967303Sgblack@eecs.umich.edudef template StoreExExecute {{ 29712234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 2987303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 2997303Sgblack@eecs.umich.edu { 3007303Sgblack@eecs.umich.edu Addr EA; 3017303Sgblack@eecs.umich.edu Fault fault = NoFault; 3027303Sgblack@eecs.umich.edu 3037303Sgblack@eecs.umich.edu %(op_decl)s; 3047303Sgblack@eecs.umich.edu %(op_rd)s; 3057303Sgblack@eecs.umich.edu %(ea_code)s; 3067303Sgblack@eecs.umich.edu 3077303Sgblack@eecs.umich.edu if (%(predicate_test)s) 3087303Sgblack@eecs.umich.edu { 3097303Sgblack@eecs.umich.edu if (fault == NoFault) { 3107303Sgblack@eecs.umich.edu %(memacc_code)s; 3117303Sgblack@eecs.umich.edu } 3127303Sgblack@eecs.umich.edu 3137303Sgblack@eecs.umich.edu uint64_t writeResult; 3147303Sgblack@eecs.umich.edu 3157303Sgblack@eecs.umich.edu if (fault == NoFault) { 3168442Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, 3178442Sgblack@eecs.umich.edu &writeResult); 3187303Sgblack@eecs.umich.edu } 3197303Sgblack@eecs.umich.edu 3207303Sgblack@eecs.umich.edu if (fault == NoFault) { 3217303Sgblack@eecs.umich.edu %(postacc_code)s; 3227303Sgblack@eecs.umich.edu } 3237303Sgblack@eecs.umich.edu 3247303Sgblack@eecs.umich.edu if (fault == NoFault) { 3257303Sgblack@eecs.umich.edu %(op_wb)s; 3267303Sgblack@eecs.umich.edu } 3277597Sminkyu.jeong@arm.com } else { 3287597Sminkyu.jeong@arm.com xc->setPredicate(false); 3297303Sgblack@eecs.umich.edu } 3307303Sgblack@eecs.umich.edu 3317303Sgblack@eecs.umich.edu return fault; 3327303Sgblack@eecs.umich.edu } 3337303Sgblack@eecs.umich.edu}}; 3347303Sgblack@eecs.umich.edu 3357303Sgblack@eecs.umich.edudef template StoreExInitiateAcc {{ 33612234Sgabeblack@google.com Fault %(class_name)s::initiateAcc(ExecContext *xc, 3377303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3387303Sgblack@eecs.umich.edu { 3397303Sgblack@eecs.umich.edu Addr EA; 3407303Sgblack@eecs.umich.edu Fault fault = NoFault; 3417303Sgblack@eecs.umich.edu 3427303Sgblack@eecs.umich.edu %(op_decl)s; 3437303Sgblack@eecs.umich.edu %(op_rd)s; 3447303Sgblack@eecs.umich.edu %(ea_code)s; 3457303Sgblack@eecs.umich.edu 3467303Sgblack@eecs.umich.edu if (%(predicate_test)s) 3477303Sgblack@eecs.umich.edu { 3487303Sgblack@eecs.umich.edu if (fault == NoFault) { 3497303Sgblack@eecs.umich.edu %(memacc_code)s; 3507303Sgblack@eecs.umich.edu } 3517303Sgblack@eecs.umich.edu 3527303Sgblack@eecs.umich.edu if (fault == NoFault) { 3538442Sgblack@eecs.umich.edu fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 3548442Sgblack@eecs.umich.edu NULL); 3557303Sgblack@eecs.umich.edu } 3567597Sminkyu.jeong@arm.com } else { 3577597Sminkyu.jeong@arm.com xc->setPredicate(false); 3587303Sgblack@eecs.umich.edu } 3597408Sgblack@eecs.umich.edu 3607303Sgblack@eecs.umich.edu return fault; 3617303Sgblack@eecs.umich.edu } 3627303Sgblack@eecs.umich.edu}}; 3637303Sgblack@eecs.umich.edu 3647120Sgblack@eecs.umich.edudef template StoreInitiateAcc {{ 36512234Sgabeblack@google.com Fault %(class_name)s::initiateAcc(ExecContext *xc, 3667120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 3677120Sgblack@eecs.umich.edu { 3687120Sgblack@eecs.umich.edu Addr EA; 3697120Sgblack@eecs.umich.edu Fault fault = NoFault; 3707120Sgblack@eecs.umich.edu 3717120Sgblack@eecs.umich.edu %(op_decl)s; 3727120Sgblack@eecs.umich.edu %(op_rd)s; 3737120Sgblack@eecs.umich.edu %(ea_code)s; 3747120Sgblack@eecs.umich.edu 3757120Sgblack@eecs.umich.edu if (%(predicate_test)s) 3767120Sgblack@eecs.umich.edu { 3777120Sgblack@eecs.umich.edu if (fault == NoFault) { 3787120Sgblack@eecs.umich.edu %(memacc_code)s; 3797120Sgblack@eecs.umich.edu } 3807120Sgblack@eecs.umich.edu 3817120Sgblack@eecs.umich.edu if (fault == NoFault) { 3828442Sgblack@eecs.umich.edu fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, 3838442Sgblack@eecs.umich.edu NULL); 3847120Sgblack@eecs.umich.edu } 3857597Sminkyu.jeong@arm.com } else { 3867597Sminkyu.jeong@arm.com xc->setPredicate(false); 3877120Sgblack@eecs.umich.edu } 3887120Sgblack@eecs.umich.edu 3897120Sgblack@eecs.umich.edu return fault; 3907120Sgblack@eecs.umich.edu } 3917120Sgblack@eecs.umich.edu}}; 3927120Sgblack@eecs.umich.edu 3937639Sgblack@eecs.umich.edudef template NeonStoreInitiateAcc {{ 3947639Sgblack@eecs.umich.edu template <class Element> 3957639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::initiateAcc( 39612234Sgabeblack@google.com ExecContext *xc, Trace::InstRecord *traceData) const 3977639Sgblack@eecs.umich.edu { 3987639Sgblack@eecs.umich.edu Addr EA; 3997639Sgblack@eecs.umich.edu Fault fault = NoFault; 4007639Sgblack@eecs.umich.edu 4017639Sgblack@eecs.umich.edu %(op_decl)s; 4027639Sgblack@eecs.umich.edu %(mem_decl)s; 4037639Sgblack@eecs.umich.edu %(op_rd)s; 4047639Sgblack@eecs.umich.edu %(ea_code)s; 4057639Sgblack@eecs.umich.edu 4067639Sgblack@eecs.umich.edu if (%(predicate_test)s) 4077639Sgblack@eecs.umich.edu { 4087639Sgblack@eecs.umich.edu MemUnion memUnion; 4097639Sgblack@eecs.umich.edu if (fault == NoFault) { 4107639Sgblack@eecs.umich.edu %(memacc_code)s; 4117639Sgblack@eecs.umich.edu } 4127639Sgblack@eecs.umich.edu 4137639Sgblack@eecs.umich.edu if (fault == NoFault) { 4148444Sgblack@eecs.umich.edu fault = xc->writeMem(memUnion.bytes, %(size)d, EA, 4158444Sgblack@eecs.umich.edu memAccessFlags, NULL); 4167639Sgblack@eecs.umich.edu } 4178072SGiacomo.Gabrielli@arm.com } else { 4188072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 4197639Sgblack@eecs.umich.edu } 4207639Sgblack@eecs.umich.edu 4217639Sgblack@eecs.umich.edu return fault; 4227639Sgblack@eecs.umich.edu } 4237639Sgblack@eecs.umich.edu}}; 4247639Sgblack@eecs.umich.edu 4257119Sgblack@eecs.umich.edudef template LoadInitiateAcc {{ 42612234Sgabeblack@google.com Fault %(class_name)s::initiateAcc(ExecContext *xc, 4277119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 4287119Sgblack@eecs.umich.edu { 4297119Sgblack@eecs.umich.edu Addr EA; 4307119Sgblack@eecs.umich.edu Fault fault = NoFault; 4317119Sgblack@eecs.umich.edu 4327119Sgblack@eecs.umich.edu %(op_src_decl)s; 4337119Sgblack@eecs.umich.edu %(op_rd)s; 4347119Sgblack@eecs.umich.edu %(ea_code)s; 4357119Sgblack@eecs.umich.edu 4367119Sgblack@eecs.umich.edu if (%(predicate_test)s) 4377119Sgblack@eecs.umich.edu { 4387119Sgblack@eecs.umich.edu if (fault == NoFault) { 43911303Ssteve.reinhardt@amd.com fault = initiateMemRead(xc, traceData, EA, Mem, 44011303Ssteve.reinhardt@amd.com memAccessFlags); 4417119Sgblack@eecs.umich.edu } 4427597Sminkyu.jeong@arm.com } else { 4437597Sminkyu.jeong@arm.com xc->setPredicate(false); 4447119Sgblack@eecs.umich.edu } 4457119Sgblack@eecs.umich.edu 4467119Sgblack@eecs.umich.edu return fault; 4477119Sgblack@eecs.umich.edu } 4487119Sgblack@eecs.umich.edu}}; 4497119Sgblack@eecs.umich.edu 4507639Sgblack@eecs.umich.edudef template NeonLoadInitiateAcc {{ 4517639Sgblack@eecs.umich.edu template <class Element> 4527639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::initiateAcc( 45312234Sgabeblack@google.com ExecContext *xc, Trace::InstRecord *traceData) const 4547639Sgblack@eecs.umich.edu { 4557639Sgblack@eecs.umich.edu Addr EA; 4567639Sgblack@eecs.umich.edu Fault fault = NoFault; 4577639Sgblack@eecs.umich.edu 4588207SAli.Saidi@ARM.com %(op_decl)s; 4598207SAli.Saidi@ARM.com %(mem_decl)s; 4607639Sgblack@eecs.umich.edu %(op_rd)s; 4617639Sgblack@eecs.umich.edu %(ea_code)s; 4627639Sgblack@eecs.umich.edu 4637639Sgblack@eecs.umich.edu if (%(predicate_test)s) 4647639Sgblack@eecs.umich.edu { 4657639Sgblack@eecs.umich.edu if (fault == NoFault) { 46611303Ssteve.reinhardt@amd.com fault = xc->initiateMemRead(EA, %(size)d, memAccessFlags); 4677639Sgblack@eecs.umich.edu } 4688072SGiacomo.Gabrielli@arm.com } else { 4698072SGiacomo.Gabrielli@arm.com xc->setPredicate(false); 4707639Sgblack@eecs.umich.edu } 4717639Sgblack@eecs.umich.edu 4727639Sgblack@eecs.umich.edu return fault; 4737639Sgblack@eecs.umich.edu } 4747639Sgblack@eecs.umich.edu}}; 4757639Sgblack@eecs.umich.edu 4767119Sgblack@eecs.umich.edudef template LoadCompleteAcc {{ 47712234Sgabeblack@google.com Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, 4787119Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 4797119Sgblack@eecs.umich.edu { 4807119Sgblack@eecs.umich.edu Fault fault = NoFault; 4817119Sgblack@eecs.umich.edu 4827119Sgblack@eecs.umich.edu %(op_decl)s; 4837119Sgblack@eecs.umich.edu %(op_rd)s; 4847119Sgblack@eecs.umich.edu 4857119Sgblack@eecs.umich.edu if (%(predicate_test)s) 4867119Sgblack@eecs.umich.edu { 4877119Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 4888442Sgblack@eecs.umich.edu getMem(pkt, Mem, traceData); 4897119Sgblack@eecs.umich.edu 4907119Sgblack@eecs.umich.edu if (fault == NoFault) { 4917119Sgblack@eecs.umich.edu %(memacc_code)s; 4927119Sgblack@eecs.umich.edu } 4937119Sgblack@eecs.umich.edu 4947119Sgblack@eecs.umich.edu if (fault == NoFault) { 4957119Sgblack@eecs.umich.edu %(op_wb)s; 4967119Sgblack@eecs.umich.edu } 4977119Sgblack@eecs.umich.edu } 4987119Sgblack@eecs.umich.edu 4997119Sgblack@eecs.umich.edu return fault; 5007119Sgblack@eecs.umich.edu } 5017119Sgblack@eecs.umich.edu}}; 5027119Sgblack@eecs.umich.edu 5037639Sgblack@eecs.umich.edudef template NeonLoadCompleteAcc {{ 5047639Sgblack@eecs.umich.edu template <class Element> 5057639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::completeAcc( 50612234Sgabeblack@google.com PacketPtr pkt, ExecContext *xc, 5077639Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5087639Sgblack@eecs.umich.edu { 5097639Sgblack@eecs.umich.edu Fault fault = NoFault; 5107639Sgblack@eecs.umich.edu 5117639Sgblack@eecs.umich.edu %(mem_decl)s; 5127639Sgblack@eecs.umich.edu %(op_decl)s; 5137639Sgblack@eecs.umich.edu %(op_rd)s; 5147639Sgblack@eecs.umich.edu 5157639Sgblack@eecs.umich.edu if (%(predicate_test)s) 5167639Sgblack@eecs.umich.edu { 5177639Sgblack@eecs.umich.edu // ARM instructions will not have a pkt if the predicate is false 5187639Sgblack@eecs.umich.edu MemUnion &memUnion = *(MemUnion *)pkt->getPtr<uint8_t>(); 5197639Sgblack@eecs.umich.edu 5207639Sgblack@eecs.umich.edu if (fault == NoFault) { 5217639Sgblack@eecs.umich.edu %(memacc_code)s; 5227639Sgblack@eecs.umich.edu } 5237639Sgblack@eecs.umich.edu 5247639Sgblack@eecs.umich.edu if (fault == NoFault) { 5257639Sgblack@eecs.umich.edu %(op_wb)s; 5267639Sgblack@eecs.umich.edu } 5277639Sgblack@eecs.umich.edu } 5287639Sgblack@eecs.umich.edu 5297639Sgblack@eecs.umich.edu return fault; 5307639Sgblack@eecs.umich.edu } 5317639Sgblack@eecs.umich.edu}}; 5327639Sgblack@eecs.umich.edu 5337120Sgblack@eecs.umich.edudef template StoreCompleteAcc {{ 53412234Sgabeblack@google.com Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, 5357120Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5367120Sgblack@eecs.umich.edu { 5377712Sgblack@eecs.umich.edu return NoFault; 5387120Sgblack@eecs.umich.edu } 5397120Sgblack@eecs.umich.edu}}; 5407120Sgblack@eecs.umich.edu 5417639Sgblack@eecs.umich.edudef template NeonStoreCompleteAcc {{ 5427639Sgblack@eecs.umich.edu template <class Element> 5437639Sgblack@eecs.umich.edu Fault %(class_name)s<Element>::completeAcc( 54412234Sgabeblack@google.com PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const 5457639Sgblack@eecs.umich.edu { 5467712Sgblack@eecs.umich.edu return NoFault; 5477639Sgblack@eecs.umich.edu } 5487639Sgblack@eecs.umich.edu}}; 5497639Sgblack@eecs.umich.edu 5507303Sgblack@eecs.umich.edudef template StoreExCompleteAcc {{ 55112234Sgabeblack@google.com Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, 5527303Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 5537303Sgblack@eecs.umich.edu { 5547303Sgblack@eecs.umich.edu Fault fault = NoFault; 5557303Sgblack@eecs.umich.edu 5567303Sgblack@eecs.umich.edu %(op_decl)s; 5577303Sgblack@eecs.umich.edu %(op_rd)s; 5587303Sgblack@eecs.umich.edu 5597303Sgblack@eecs.umich.edu if (%(predicate_test)s) 5607303Sgblack@eecs.umich.edu { 5617303Sgblack@eecs.umich.edu uint64_t writeResult = pkt->req->getExtraData(); 5627303Sgblack@eecs.umich.edu %(postacc_code)s; 5637303Sgblack@eecs.umich.edu 5647303Sgblack@eecs.umich.edu if (fault == NoFault) { 5657303Sgblack@eecs.umich.edu %(op_wb)s; 5667303Sgblack@eecs.umich.edu } 5677303Sgblack@eecs.umich.edu } 5687303Sgblack@eecs.umich.edu 5697303Sgblack@eecs.umich.edu return fault; 5707303Sgblack@eecs.umich.edu } 5717303Sgblack@eecs.umich.edu}}; 5727303Sgblack@eecs.umich.edu 5737291Sgblack@eecs.umich.edudef template RfeDeclare {{ 5747291Sgblack@eecs.umich.edu /** 5757291Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 5767291Sgblack@eecs.umich.edu */ 5777291Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 5787291Sgblack@eecs.umich.edu { 5797291Sgblack@eecs.umich.edu public: 5807291Sgblack@eecs.umich.edu 5817291Sgblack@eecs.umich.edu /// Constructor. 5827291Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 5837291Sgblack@eecs.umich.edu uint32_t _base, int _mode, bool _wb); 5847291Sgblack@eecs.umich.edu 58512616Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const override; 58612616Sgabeblack@google.com Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; 58712616Sgabeblack@google.com Fault completeAcc(PacketPtr, ExecContext *, 58812616Sgabeblack@google.com Trace::InstRecord *) const override; 5897291Sgblack@eecs.umich.edu }; 5907291Sgblack@eecs.umich.edu}}; 5917291Sgblack@eecs.umich.edu 5927312Sgblack@eecs.umich.edudef template SrsDeclare {{ 5937312Sgblack@eecs.umich.edu /** 5947312Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 5957312Sgblack@eecs.umich.edu */ 5967312Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 5977312Sgblack@eecs.umich.edu { 5987312Sgblack@eecs.umich.edu public: 5997312Sgblack@eecs.umich.edu 6007312Sgblack@eecs.umich.edu /// Constructor. 6017312Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6027312Sgblack@eecs.umich.edu uint32_t _regMode, int _mode, bool _wb); 6037312Sgblack@eecs.umich.edu 60412616Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const override; 60512616Sgabeblack@google.com Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; 60612616Sgabeblack@google.com Fault completeAcc(PacketPtr, ExecContext *, 60712616Sgabeblack@google.com Trace::InstRecord *) const override; 6087312Sgblack@eecs.umich.edu }; 6097312Sgblack@eecs.umich.edu}}; 6107312Sgblack@eecs.umich.edu 6117205Sgblack@eecs.umich.edudef template SwapDeclare {{ 6127205Sgblack@eecs.umich.edu /** 6137205Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6147205Sgblack@eecs.umich.edu */ 6157205Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6167205Sgblack@eecs.umich.edu { 6177205Sgblack@eecs.umich.edu public: 6187205Sgblack@eecs.umich.edu 6197205Sgblack@eecs.umich.edu /// Constructor. 6207205Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6217205Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base); 6227205Sgblack@eecs.umich.edu 62312616Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const override; 62412616Sgabeblack@google.com Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; 62512616Sgabeblack@google.com Fault completeAcc(PacketPtr, ExecContext *, 62612616Sgabeblack@google.com Trace::InstRecord *) const override; 6277205Sgblack@eecs.umich.edu }; 6287205Sgblack@eecs.umich.edu}}; 6297205Sgblack@eecs.umich.edu 6307279Sgblack@eecs.umich.edudef template LoadStoreDImmDeclare {{ 6317279Sgblack@eecs.umich.edu /** 6327279Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6337279Sgblack@eecs.umich.edu */ 6347279Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6357279Sgblack@eecs.umich.edu { 6367279Sgblack@eecs.umich.edu public: 6377279Sgblack@eecs.umich.edu 6387279Sgblack@eecs.umich.edu /// Constructor. 6397279Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6407279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 6417279Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm); 6427279Sgblack@eecs.umich.edu 64312616Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const override; 64412616Sgabeblack@google.com Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; 64512616Sgabeblack@google.com Fault completeAcc(PacketPtr, ExecContext *, 64612616Sgabeblack@google.com Trace::InstRecord *) const override; 6477279Sgblack@eecs.umich.edu }; 6487279Sgblack@eecs.umich.edu}}; 6497279Sgblack@eecs.umich.edu 6507303Sgblack@eecs.umich.edudef template StoreExDImmDeclare {{ 6517303Sgblack@eecs.umich.edu /** 6527303Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6537303Sgblack@eecs.umich.edu */ 6547303Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6557303Sgblack@eecs.umich.edu { 6567303Sgblack@eecs.umich.edu public: 6577303Sgblack@eecs.umich.edu 6587303Sgblack@eecs.umich.edu /// Constructor. 6597303Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6607303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _dest2, 6617303Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm); 6627303Sgblack@eecs.umich.edu 66312616Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const override; 66412616Sgabeblack@google.com Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; 66512616Sgabeblack@google.com Fault completeAcc(PacketPtr, ExecContext *, 66612616Sgabeblack@google.com Trace::InstRecord *) const override; 6677303Sgblack@eecs.umich.edu }; 6687303Sgblack@eecs.umich.edu}}; 6697303Sgblack@eecs.umich.edu 6707119Sgblack@eecs.umich.edudef template LoadStoreImmDeclare {{ 6717119Sgblack@eecs.umich.edu /** 6727119Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6737119Sgblack@eecs.umich.edu */ 6747119Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 6757119Sgblack@eecs.umich.edu { 6767119Sgblack@eecs.umich.edu public: 6777119Sgblack@eecs.umich.edu 6787119Sgblack@eecs.umich.edu /// Constructor. 6797119Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 6807119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 6817119Sgblack@eecs.umich.edu 68212616Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const override; 68312616Sgabeblack@google.com Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; 68412616Sgabeblack@google.com Fault completeAcc(PacketPtr, ExecContext *, 68512616Sgabeblack@google.com Trace::InstRecord *) const override; 68610037SARM gem5 Developers 68712616Sgabeblack@google.com void 68812616Sgabeblack@google.com annotateFault(ArmFault *fault) override 68912616Sgabeblack@google.com { 69010037SARM gem5 Developers %(fa_code)s 69110037SARM gem5 Developers } 6927119Sgblack@eecs.umich.edu }; 6937119Sgblack@eecs.umich.edu}}; 6947119Sgblack@eecs.umich.edu 6957303Sgblack@eecs.umich.edudef template StoreExImmDeclare {{ 6967303Sgblack@eecs.umich.edu /** 6977303Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 6987303Sgblack@eecs.umich.edu */ 6997303Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7007303Sgblack@eecs.umich.edu { 7017303Sgblack@eecs.umich.edu public: 7027303Sgblack@eecs.umich.edu 7037303Sgblack@eecs.umich.edu /// Constructor. 7047303Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7057303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _base, 7067303Sgblack@eecs.umich.edu bool _add, int32_t _imm); 7077303Sgblack@eecs.umich.edu 70812616Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const override; 70912616Sgabeblack@google.com Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; 71012616Sgabeblack@google.com Fault completeAcc(PacketPtr, ExecContext *, 71112616Sgabeblack@google.com Trace::InstRecord *) const override; 7127303Sgblack@eecs.umich.edu }; 7137303Sgblack@eecs.umich.edu}}; 7147303Sgblack@eecs.umich.edu 7157646Sgene.wu@arm.comdef template StoreDRegDeclare {{ 7167279Sgblack@eecs.umich.edu /** 7177279Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7187279Sgblack@eecs.umich.edu */ 7197279Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7207279Sgblack@eecs.umich.edu { 7217279Sgblack@eecs.umich.edu public: 7227279Sgblack@eecs.umich.edu 7237279Sgblack@eecs.umich.edu /// Constructor. 7247279Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7257279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 7267279Sgblack@eecs.umich.edu uint32_t _base, bool _add, 7277279Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 7287279Sgblack@eecs.umich.edu uint32_t _index); 7297279Sgblack@eecs.umich.edu 73012616Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const override; 73112616Sgabeblack@google.com Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; 73212616Sgabeblack@google.com Fault completeAcc(PacketPtr, ExecContext *, 73312616Sgabeblack@google.com Trace::InstRecord *) const override; 7347279Sgblack@eecs.umich.edu }; 7357279Sgblack@eecs.umich.edu}}; 7367279Sgblack@eecs.umich.edu 7377646Sgene.wu@arm.comdef template StoreRegDeclare {{ 7387119Sgblack@eecs.umich.edu /** 7397119Sgblack@eecs.umich.edu * Static instruction class for "%(mnemonic)s". 7407119Sgblack@eecs.umich.edu */ 7417119Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 7427119Sgblack@eecs.umich.edu { 7437119Sgblack@eecs.umich.edu public: 7447119Sgblack@eecs.umich.edu 7457119Sgblack@eecs.umich.edu /// Constructor. 7467119Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst machInst, 7477119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 7487119Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, 7497119Sgblack@eecs.umich.edu uint32_t _index); 7507119Sgblack@eecs.umich.edu 75112616Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const override; 75212616Sgabeblack@google.com Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; 75312616Sgabeblack@google.com Fault completeAcc(PacketPtr, ExecContext *, 75412616Sgabeblack@google.com Trace::InstRecord *) const override; 75510037SARM gem5 Developers 75612616Sgabeblack@google.com void 75712616Sgabeblack@google.com annotateFault(ArmFault *fault) override 75812616Sgabeblack@google.com { 75910037SARM gem5 Developers %(fa_code)s 76010037SARM gem5 Developers } 7617119Sgblack@eecs.umich.edu }; 7627119Sgblack@eecs.umich.edu}}; 7637119Sgblack@eecs.umich.edu 7647646Sgene.wu@arm.comdef template LoadDRegDeclare {{ 7657646Sgene.wu@arm.com /** 7667646Sgene.wu@arm.com * Static instruction class for "%(mnemonic)s". 7677646Sgene.wu@arm.com */ 7687646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 7697646Sgene.wu@arm.com { 7707646Sgene.wu@arm.com public: 7717646Sgene.wu@arm.com 7727646Sgene.wu@arm.com /// Constructor. 7737646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 7747646Sgene.wu@arm.com uint32_t _dest, uint32_t _dest2, 7757646Sgene.wu@arm.com uint32_t _base, bool _add, 7767646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, 7777646Sgene.wu@arm.com uint32_t _index); 7787646Sgene.wu@arm.com 77912616Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const override; 78012616Sgabeblack@google.com Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; 78112616Sgabeblack@google.com Fault completeAcc(PacketPtr, ExecContext *, 78212616Sgabeblack@google.com Trace::InstRecord *) const override; 7837646Sgene.wu@arm.com }; 7847646Sgene.wu@arm.com}}; 7857646Sgene.wu@arm.com 7867646Sgene.wu@arm.comdef template LoadRegDeclare {{ 7877646Sgene.wu@arm.com /** 7887646Sgene.wu@arm.com * Static instruction class for "%(mnemonic)s". 7897646Sgene.wu@arm.com */ 7907646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 7917646Sgene.wu@arm.com { 7927646Sgene.wu@arm.com public: 7937646Sgene.wu@arm.com 7947646Sgene.wu@arm.com /// Constructor. 7957646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 7967646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, 7977646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, 7987646Sgene.wu@arm.com uint32_t _index); 7997646Sgene.wu@arm.com 80012616Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const override; 80112616Sgabeblack@google.com Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; 80212616Sgabeblack@google.com Fault completeAcc(PacketPtr, ExecContext *, 80312616Sgabeblack@google.com Trace::InstRecord *) const override; 80410037SARM gem5 Developers 80512616Sgabeblack@google.com void 80612616Sgabeblack@google.com annotateFault(ArmFault *fault) override 80712616Sgabeblack@google.com { 80810037SARM gem5 Developers %(fa_code)s 80910037SARM gem5 Developers } 8107646Sgene.wu@arm.com }; 8117646Sgene.wu@arm.com}}; 8127646Sgene.wu@arm.com 8137646Sgene.wu@arm.comdef template LoadImmDeclare {{ 8147646Sgene.wu@arm.com /** 8157646Sgene.wu@arm.com * Static instruction class for "%(mnemonic)s". 8167646Sgene.wu@arm.com */ 8177646Sgene.wu@arm.com class %(class_name)s : public %(base_class)s 8187646Sgene.wu@arm.com { 8197646Sgene.wu@arm.com public: 8207646Sgene.wu@arm.com 8217646Sgene.wu@arm.com /// Constructor. 8227646Sgene.wu@arm.com %(class_name)s(ExtMachInst machInst, 8237646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); 8247646Sgene.wu@arm.com 82512616Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const override; 82612616Sgabeblack@google.com Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; 82712616Sgabeblack@google.com Fault completeAcc(PacketPtr, ExecContext *, 82812616Sgabeblack@google.com Trace::InstRecord *) const override; 82910037SARM gem5 Developers 83012616Sgabeblack@google.com void 83112616Sgabeblack@google.com annotateFault(ArmFault *fault) override 83212616Sgabeblack@google.com { 83310037SARM gem5 Developers %(fa_code)s 83410037SARM gem5 Developers } 8357646Sgene.wu@arm.com }; 8367646Sgene.wu@arm.com}}; 8377646Sgene.wu@arm.com 8387291Sgblack@eecs.umich.edudef template RfeConstructor {{ 83910184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 8408140SMatt.Horsnell@arm.com uint32_t _base, int _mode, bool _wb) 8418140SMatt.Horsnell@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8428140SMatt.Horsnell@arm.com (IntRegIndex)_base, (AddrMode)_mode, _wb) 8437291Sgblack@eecs.umich.edu { 8447291Sgblack@eecs.umich.edu %(constructor)s; 8457848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 8467848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 8477848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 8487848SAli.Saidi@ARM.com } 8497848SAli.Saidi@ARM.com } 8507646Sgene.wu@arm.com#if %(use_uops)d 8518140SMatt.Horsnell@arm.com uops = new StaticInstPtr[1 + %(use_wb)d + %(use_pc)d]; 8528140SMatt.Horsnell@arm.com int uopIdx = 0; 8538140SMatt.Horsnell@arm.com uops[uopIdx] = new %(acc_name)s(machInst, _base, _mode, _wb); 8548140SMatt.Horsnell@arm.com uops[uopIdx]->setDelayedCommit(); 8558140SMatt.Horsnell@arm.com#if %(use_wb)d 8568140SMatt.Horsnell@arm.com uops[++uopIdx] = new %(wb_decl)s; 8578140SMatt.Horsnell@arm.com uops[uopIdx]->setDelayedCommit(); 8588140SMatt.Horsnell@arm.com#endif 8598140SMatt.Horsnell@arm.com#if %(use_pc)d 8608140SMatt.Horsnell@arm.com uops[++uopIdx] = new %(pc_decl)s; 8618140SMatt.Horsnell@arm.com#endif 86210666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 8638140SMatt.Horsnell@arm.com uops[uopIdx]->setLastMicroop(); 8647646Sgene.wu@arm.com#endif 8657291Sgblack@eecs.umich.edu } 8667291Sgblack@eecs.umich.edu}}; 8677291Sgblack@eecs.umich.edu 8687312Sgblack@eecs.umich.edudef template SrsConstructor {{ 86910184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 8707312Sgblack@eecs.umich.edu uint32_t _regMode, int _mode, bool _wb) 8717312Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8727312Sgblack@eecs.umich.edu (OperatingMode)_regMode, (AddrMode)_mode, _wb) 8737312Sgblack@eecs.umich.edu { 8747312Sgblack@eecs.umich.edu %(constructor)s; 8757848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 8767848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 8777848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 8787848SAli.Saidi@ARM.com } 8797848SAli.Saidi@ARM.com } 8807646Sgene.wu@arm.com#if %(use_uops)d 8817646Sgene.wu@arm.com assert(numMicroops >= 2); 8827646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 8837646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _regMode, _mode, _wb); 8847724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 88510666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 8867646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 8877646Sgene.wu@arm.com uops[1]->setLastMicroop(); 8887646Sgene.wu@arm.com#endif 8897312Sgblack@eecs.umich.edu } 8907312Sgblack@eecs.umich.edu}}; 8917312Sgblack@eecs.umich.edu 8927205Sgblack@eecs.umich.edudef template SwapConstructor {{ 89310184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 8947205Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _op1, uint32_t _base) 8957205Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 8967205Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) 8977205Sgblack@eecs.umich.edu { 8987205Sgblack@eecs.umich.edu %(constructor)s; 8997848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9007848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9017848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9027848SAli.Saidi@ARM.com } 9037848SAli.Saidi@ARM.com } 9047205Sgblack@eecs.umich.edu } 9057205Sgblack@eecs.umich.edu}}; 9067205Sgblack@eecs.umich.edu 9077279Sgblack@eecs.umich.edudef template LoadStoreDImmConstructor {{ 90810184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 9097279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, 9107279Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm) 9117279Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9127279Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 9137279Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 9147279Sgblack@eecs.umich.edu { 9157279Sgblack@eecs.umich.edu %(constructor)s; 9167848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9177848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9187848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9197848SAli.Saidi@ARM.com } 9207848SAli.Saidi@ARM.com } 9217646Sgene.wu@arm.com#if %(use_uops)d 9227646Sgene.wu@arm.com assert(numMicroops >= 2); 9237646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 9247646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _imm); 92510666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 9267724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 9277646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 9287646Sgene.wu@arm.com uops[1]->setLastMicroop(); 9297646Sgene.wu@arm.com#endif 9307279Sgblack@eecs.umich.edu } 9317279Sgblack@eecs.umich.edu}}; 9327279Sgblack@eecs.umich.edu 9337303Sgblack@eecs.umich.edudef template StoreExDImmConstructor {{ 93410184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 9357303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _dest2, 9367303Sgblack@eecs.umich.edu uint32_t _base, bool _add, int32_t _imm) 9377303Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9387303Sgblack@eecs.umich.edu (IntRegIndex)_result, 9397303Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 9407303Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 9417303Sgblack@eecs.umich.edu { 9427303Sgblack@eecs.umich.edu %(constructor)s; 9437848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9447848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9457848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9467848SAli.Saidi@ARM.com } 9477848SAli.Saidi@ARM.com } 9487646Sgene.wu@arm.com#if %(use_uops)d 9497646Sgene.wu@arm.com assert(numMicroops >= 2); 9507646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 9517646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _result, _dest, _dest2, 9527646Sgene.wu@arm.com _base, _add, _imm); 9537724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 95410666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 9557646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 9567646Sgene.wu@arm.com uops[1]->setLastMicroop(); 9577646Sgene.wu@arm.com#endif 9587303Sgblack@eecs.umich.edu } 9597303Sgblack@eecs.umich.edu}}; 9607303Sgblack@eecs.umich.edu 9617119Sgblack@eecs.umich.edudef template LoadStoreImmConstructor {{ 96210184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 9637119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 9647119Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9657119Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 9667119Sgblack@eecs.umich.edu { 9677119Sgblack@eecs.umich.edu %(constructor)s; 9687848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9697848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9707848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9717848SAli.Saidi@ARM.com } 9727848SAli.Saidi@ARM.com } 9737646Sgene.wu@arm.com#if %(use_uops)d 9747646Sgene.wu@arm.com assert(numMicroops >= 2); 9757646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 9767646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); 9777724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 97810666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 9797646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 9807646Sgene.wu@arm.com uops[1]->setLastMicroop(); 9817646Sgene.wu@arm.com#endif 9827119Sgblack@eecs.umich.edu } 9837119Sgblack@eecs.umich.edu}}; 9847119Sgblack@eecs.umich.edu 9857303Sgblack@eecs.umich.edudef template StoreExImmConstructor {{ 98610184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 9877303Sgblack@eecs.umich.edu uint32_t _result, uint32_t _dest, uint32_t _base, 9887303Sgblack@eecs.umich.edu bool _add, int32_t _imm) 9897303Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 9907303Sgblack@eecs.umich.edu (IntRegIndex)_result, (IntRegIndex)_dest, 9917303Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, _imm) 9927303Sgblack@eecs.umich.edu { 9937303Sgblack@eecs.umich.edu %(constructor)s; 9947848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 9957848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 9967848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 9977848SAli.Saidi@ARM.com } 9987848SAli.Saidi@ARM.com } 9997646Sgene.wu@arm.com#if %(use_uops)d 10007646Sgene.wu@arm.com assert(numMicroops >= 2); 10017646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10027646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _result, _dest, 10037646Sgene.wu@arm.com _base, _add, _imm); 10047724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 100510666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 10067646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10077646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10087646Sgene.wu@arm.com#endif 10097303Sgblack@eecs.umich.edu } 10107303Sgblack@eecs.umich.edu}}; 10117303Sgblack@eecs.umich.edu 10127646Sgene.wu@arm.comdef template StoreDRegConstructor {{ 101310184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 10147279Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 10157279Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 10167279Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10177279Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_dest2, 10187279Sgblack@eecs.umich.edu (IntRegIndex)_base, _add, 10197279Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 10207279Sgblack@eecs.umich.edu (IntRegIndex)_index) 10217279Sgblack@eecs.umich.edu { 10227279Sgblack@eecs.umich.edu %(constructor)s; 10237848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 10247848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 10257848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10267848SAli.Saidi@ARM.com } 10277848SAli.Saidi@ARM.com } 10287646Sgene.wu@arm.com#if %(use_uops)d 10297646Sgene.wu@arm.com assert(numMicroops >= 2); 10307646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10317646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 10327646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 10337724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 103410666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 10357646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10367646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10377646Sgene.wu@arm.com#endif 10387279Sgblack@eecs.umich.edu } 10397279Sgblack@eecs.umich.edu}}; 10407279Sgblack@eecs.umich.edu 10417646Sgene.wu@arm.comdef template StoreRegConstructor {{ 104210184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 10437119Sgblack@eecs.umich.edu uint32_t _dest, uint32_t _base, bool _add, 10447119Sgblack@eecs.umich.edu int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 10457119Sgblack@eecs.umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10467119Sgblack@eecs.umich.edu (IntRegIndex)_dest, (IntRegIndex)_base, _add, 10477119Sgblack@eecs.umich.edu _shiftAmt, (ArmShiftType)_shiftType, 10487119Sgblack@eecs.umich.edu (IntRegIndex)_index) 10497119Sgblack@eecs.umich.edu { 10507119Sgblack@eecs.umich.edu %(constructor)s; 10517848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 10527848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 10537848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10547848SAli.Saidi@ARM.com } 10557848SAli.Saidi@ARM.com } 10567646Sgene.wu@arm.com#if %(use_uops)d 10577646Sgene.wu@arm.com assert(numMicroops >= 2); 10587646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10597646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, 10607646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 10617724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 106210666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 10637646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 10647646Sgene.wu@arm.com uops[1]->setLastMicroop(); 10657646Sgene.wu@arm.com#endif 10667119Sgblack@eecs.umich.edu } 10677119Sgblack@eecs.umich.edu}}; 10687646Sgene.wu@arm.com 10697646Sgene.wu@arm.comdef template LoadDRegConstructor {{ 107010184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 10717646Sgene.wu@arm.com uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, 10727646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 10737646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 10747646Sgene.wu@arm.com (IntRegIndex)_dest, (IntRegIndex)_dest2, 10757646Sgene.wu@arm.com (IntRegIndex)_base, _add, 10767646Sgene.wu@arm.com _shiftAmt, (ArmShiftType)_shiftType, 10777646Sgene.wu@arm.com (IntRegIndex)_index) 10787646Sgene.wu@arm.com { 10797646Sgene.wu@arm.com %(constructor)s; 10807848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 10817848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 10827848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 10837848SAli.Saidi@ARM.com } 10847848SAli.Saidi@ARM.com } 10857646Sgene.wu@arm.com#if %(use_uops)d 10867646Sgene.wu@arm.com assert(numMicroops >= 2); 10877646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 10887646Sgene.wu@arm.com if ((_dest == _index) || (_dest2 == _index)) { 10897646Sgene.wu@arm.com IntRegIndex wbIndexReg = INTREG_UREG0; 10907646Sgene.wu@arm.com uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index); 10917724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 109210666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 10937646Sgene.wu@arm.com uops[1] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 10947646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 10957724SAli.Saidi@ARM.com uops[1]->setDelayedCommit(); 10967646Sgene.wu@arm.com uops[2] = new %(wb_decl)s; 10977646Sgene.wu@arm.com uops[2]->setLastMicroop(); 10987646Sgene.wu@arm.com } else { 10997646Sgene.wu@arm.com IntRegIndex wbIndexReg = index; 11007646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, 11017646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11027724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 110310666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 11047646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 11057646Sgene.wu@arm.com uops[1]->setLastMicroop(); 11067646Sgene.wu@arm.com } 11077646Sgene.wu@arm.com#endif 11087646Sgene.wu@arm.com } 11097646Sgene.wu@arm.com}}; 11107646Sgene.wu@arm.com 11117646Sgene.wu@arm.comdef template LoadRegConstructor {{ 111210184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 11137646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, 11147646Sgene.wu@arm.com int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) 11157646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 11167646Sgene.wu@arm.com (IntRegIndex)_dest, (IntRegIndex)_base, _add, 11177646Sgene.wu@arm.com _shiftAmt, (ArmShiftType)_shiftType, 11187646Sgene.wu@arm.com (IntRegIndex)_index) 11197646Sgene.wu@arm.com { 11207646Sgene.wu@arm.com %(constructor)s; 11218607Sgblack@eecs.umich.edu bool conditional M5_VAR_USED = false; 11227848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 11238203SAli.Saidi@ARM.com conditional = true; 11247848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 11257848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 11267848SAli.Saidi@ARM.com } 11277848SAli.Saidi@ARM.com } 11287646Sgene.wu@arm.com#if %(use_uops)d 11297646Sgene.wu@arm.com assert(numMicroops >= 2); 11307646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 113112110SRekai.GonzalezAlberquilla@arm.com if (_dest == INTREG_PC && !isFloating() && !isVector()) { 11327646Sgene.wu@arm.com IntRegIndex wbIndexReg = index; 11337646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 11347646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11357724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 113610666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 11377646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 11387724SAli.Saidi@ARM.com uops[1]->setDelayedCommit(); 11397646Sgene.wu@arm.com uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); 11408203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsControl); 11418203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsIndirectControl); 11428203SAli.Saidi@ARM.com if (conditional) 11438203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsCondControl); 11448203SAli.Saidi@ARM.com else 11458203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsUncondControl); 11467646Sgene.wu@arm.com uops[2]->setLastMicroop(); 11477646Sgene.wu@arm.com } else if(_dest == _index) { 11487646Sgene.wu@arm.com IntRegIndex wbIndexReg = INTREG_UREG0; 11497646Sgene.wu@arm.com uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index); 11507724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 115110666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 11527646Sgene.wu@arm.com uops[1] = new %(acc_name)s(machInst, _dest, _base, _add, 11537646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11547724SAli.Saidi@ARM.com uops[1]->setDelayedCommit(); 11557646Sgene.wu@arm.com uops[2] = new %(wb_decl)s; 11567646Sgene.wu@arm.com uops[2]->setLastMicroop(); 11577646Sgene.wu@arm.com } else { 11587646Sgene.wu@arm.com IntRegIndex wbIndexReg = index; 11597646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, 11607646Sgene.wu@arm.com _shiftAmt, _shiftType, _index); 11617724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 116210666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 11637646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 11647646Sgene.wu@arm.com uops[1]->setLastMicroop(); 11657646Sgene.wu@arm.com 11667646Sgene.wu@arm.com } 11679250SAli.Saidi@ARM.com#else 116812110SRekai.GonzalezAlberquilla@arm.com if (_dest == INTREG_PC && !isFloating() && !isVector()) { 11699250SAli.Saidi@ARM.com flags[IsControl] = true; 11709250SAli.Saidi@ARM.com flags[IsIndirectControl] = true; 11719250SAli.Saidi@ARM.com if (conditional) 11729250SAli.Saidi@ARM.com flags[IsCondControl] = true; 11739250SAli.Saidi@ARM.com else 11749250SAli.Saidi@ARM.com flags[IsUncondControl] = true; 11759250SAli.Saidi@ARM.com } 11767646Sgene.wu@arm.com#endif 11777646Sgene.wu@arm.com } 11787646Sgene.wu@arm.com}}; 11797646Sgene.wu@arm.com 11807646Sgene.wu@arm.comdef template LoadImmConstructor {{ 118110184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst, 11827646Sgene.wu@arm.com uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) 11837646Sgene.wu@arm.com : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 11847646Sgene.wu@arm.com (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) 11857646Sgene.wu@arm.com { 11867646Sgene.wu@arm.com %(constructor)s; 11878607Sgblack@eecs.umich.edu bool conditional M5_VAR_USED = false; 11887848SAli.Saidi@ARM.com if (!(condCode == COND_AL || condCode == COND_UC)) { 11898203SAli.Saidi@ARM.com conditional = true; 11907848SAli.Saidi@ARM.com for (int x = 0; x < _numDestRegs; x++) { 11917848SAli.Saidi@ARM.com _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 11927848SAli.Saidi@ARM.com } 11937848SAli.Saidi@ARM.com } 11947646Sgene.wu@arm.com#if %(use_uops)d 11957646Sgene.wu@arm.com assert(numMicroops >= 2); 11967646Sgene.wu@arm.com uops = new StaticInstPtr[numMicroops]; 119712110SRekai.GonzalezAlberquilla@arm.com if (_dest == INTREG_PC && !isFloating() && !isVector()) { 11987646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add, 11997646Sgene.wu@arm.com _imm); 12007724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 120110666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 12027646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 12037724SAli.Saidi@ARM.com uops[1]->setDelayedCommit(); 12047646Sgene.wu@arm.com uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0); 12058203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsControl); 12068203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsIndirectControl); 120710199SAndrew.Bardsley@arm.com /* Also set flags on the macroop so that pre-microop decomposition 120810199SAndrew.Bardsley@arm.com branch prediction can work */ 120910199SAndrew.Bardsley@arm.com setFlag(StaticInst::IsControl); 121010199SAndrew.Bardsley@arm.com setFlag(StaticInst::IsIndirectControl); 121110199SAndrew.Bardsley@arm.com if (conditional) { 12128203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsCondControl); 121310199SAndrew.Bardsley@arm.com setFlag(StaticInst::IsCondControl); 121410199SAndrew.Bardsley@arm.com } else { 12158203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsUncondControl); 121610199SAndrew.Bardsley@arm.com setFlag(StaticInst::IsUncondControl); 121710199SAndrew.Bardsley@arm.com } 121810199SAndrew.Bardsley@arm.com if (_base == INTREG_SP && _add && _imm == 4 && %(is_ras_pop)s) { 12198203SAli.Saidi@ARM.com uops[2]->setFlag(StaticInst::IsReturn); 122010199SAndrew.Bardsley@arm.com setFlag(StaticInst::IsReturn); 122110199SAndrew.Bardsley@arm.com } 12227646Sgene.wu@arm.com uops[2]->setLastMicroop(); 12237646Sgene.wu@arm.com } else { 12247646Sgene.wu@arm.com uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm); 12257724SAli.Saidi@ARM.com uops[0]->setDelayedCommit(); 122610666SAli.Saidi@ARM.com uops[0]->setFirstMicroop(); 12277646Sgene.wu@arm.com uops[1] = new %(wb_decl)s; 12287646Sgene.wu@arm.com uops[1]->setLastMicroop(); 12297646Sgene.wu@arm.com } 12309250SAli.Saidi@ARM.com#else 123112110SRekai.GonzalezAlberquilla@arm.com if (_dest == INTREG_PC && !isFloating() && !isVector()) { 12329250SAli.Saidi@ARM.com flags[IsControl] = true; 12339250SAli.Saidi@ARM.com flags[IsIndirectControl] = true; 12349250SAli.Saidi@ARM.com if (conditional) 12359250SAli.Saidi@ARM.com flags[IsCondControl] = true; 12369250SAli.Saidi@ARM.com else 12379250SAli.Saidi@ARM.com flags[IsUncondControl] = true; 12389250SAli.Saidi@ARM.com } 12397646Sgene.wu@arm.com#endif 12407646Sgene.wu@arm.com } 12417646Sgene.wu@arm.com}}; 12427646Sgene.wu@arm.com 1243