Searched hist:5 (Results 426 - 450 of 1055) sorted by relevance

<<11121314151617181920>>

/gem5/src/sim/
H A Dinsttracer.hhdiff 13610:5d5404ac6288 Tue Oct 16 11:04:00 EDT 2018 Giacomo Gabrielli <giacomo.gabrielli@arm.com> arch,cpu: Add vector predicate registers

Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector
Extension (SVE), introduce the notion of a predicate register file.
This changeset adds this feature across architectures and CPU models.

Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13715
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
diff 10935:acd48ddd725f Tue Jul 28 02:58:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> revert 5af8f40d8f2c
diff 10934:5af8f40d8f2c Sun Jul 26 11:21:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> cpu: implements vector registers

This adds a vector register type. The type is defined as a std::array of a
fixed number of uint64_ts. The isa_parser.py has been modified to parse vector
register operands and generate the required code. Different cpus have vector
register files now.
/gem5/src/arch/arm/insts/
H A Dmisc.ccdiff 10037:5cac77888310 Fri Jan 24 16:29:00 EST 2014 ARM gem5 Developers arm: Add support for ARMv8 (AArch64 & AArch32)

Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black
diff 7426:5da64155a605 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Get rid of the binary dumping function in utility.hh.
diff 7261:5ed14bce7261 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Rename the RevOp base class to something more generic.
/gem5/src/arch/arm/isa/insts/
H A Dneon.isadiff 10037:5cac77888310 Fri Jan 24 16:29:00 EST 2014 ARM gem5 Developers arm: Add support for ARMv8 (AArch64 & AArch32)

Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black
diff 9517:5ffb5e5c93b4 Fri Feb 15 17:40:00 EST 2013 Ali Saidi <Ali.Saidi@ARM.com> arm: fix some fp comparisons that worked by accident.

The explict tests in the follwing fp comparison operations were
incorrect as they checked for only signaling NaNs and not quite-NaNs
as well. When compiled with gcc, the comparison generates a fp exception
that causes the FE_INVALID flag to be set and we check for it, so even
though the check was incorrect, the correct exception was set. With clang
this behavior seems to not occur. The checks are updated to test for nans and
the behavior is now correct with both clang and gcc.
diff 8607:5fb918115c07 Mon Oct 31 04:09:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> GCC: Get everything working with gcc 4.6.1.

And by "everything" I mean all the quick regressions.
H A Dstr.isadiff 12219:5c42cf79d862 Wed Jul 12 08:49:00 EDT 2017 Nikos Nikoleris <nikos.nikoleris@arm.com> arch-arm: Signal an event when executing store exclusives

When a store exclusive is executed, whether it is successful or not,
the exclusives monitor is cleared and therefore we need to signal an
event for the PE.

Change-Id: I383c88c769c0ac5f5d36c4b5d39c9681134d3a20
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4480
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
diff 10037:5cac77888310 Fri Jan 24 16:29:00 EST 2014 ARM gem5 Developers arm: Add support for ARMv8 (AArch64 & AArch32)

Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black
diff 8303:5a95f1d2494e Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Further break up condition code into NZ, C, V bits.

Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.
H A Dmult.isadiff 8303:5a95f1d2494e Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Further break up condition code into NZ, C, V bits.

Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.
/gem5/src/mem/slicc/ast/
H A DIfStatementAST.pydiff 7839:9e556fb25900 Mon Jan 17 19:46:00 EST 2011 Nilay Vaish<nilay@cs.wisc.edu> Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.

I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.

Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.

Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.

All the protocols have been modified to conform with the new interface.
H A DIsValidPtrExprAST.py7839:9e556fb25900 Mon Jan 17 19:46:00 EST 2011 Nilay Vaish<nilay@cs.wisc.edu> Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.

I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.

Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.

Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.

All the protocols have been modified to conform with the new interface.
H A DTypeDeclAST.pydiff 7839:9e556fb25900 Mon Jan 17 19:46:00 EST 2011 Nilay Vaish<nilay@cs.wisc.edu> Change interface between coherence protocols and CacheMemory
The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.

I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.

Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.

Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.

All the protocols have been modified to conform with the new interface.
/gem5/configs/boot/
H A Dnat-netperf-maerts-client.rcS1196:5e20797f314a Tue Nov 16 22:43:00 EST 2004 Lisa Hsu <hsul@eecs.umich.edu> add support for NAT under netperf stream, maerts, and spec-surge.

configs/boot/spec-surge-client.rcS:
configs/boot/surge-client.rcS:
fix this rcS - don't sleep, instead wait for the server to tell you it's done.
configs/boot/spec-surge-server.rcS:
configs/boot/surge-server.rcS:
notify the client you're done starting the server.
H A Dnat-netperf-server.rcS1196:5e20797f314a Tue Nov 16 22:43:00 EST 2004 Lisa Hsu <hsul@eecs.umich.edu> add support for NAT under netperf stream, maerts, and spec-surge.

configs/boot/spec-surge-client.rcS:
configs/boot/surge-client.rcS:
fix this rcS - don't sleep, instead wait for the server to tell you it's done.
configs/boot/spec-surge-server.rcS:
configs/boot/surge-server.rcS:
notify the client you're done starting the server.
H A Dnat-netperf-stream-client.rcS1196:5e20797f314a Tue Nov 16 22:43:00 EST 2004 Lisa Hsu <hsul@eecs.umich.edu> add support for NAT under netperf stream, maerts, and spec-surge.

configs/boot/spec-surge-client.rcS:
configs/boot/surge-client.rcS:
fix this rcS - don't sleep, instead wait for the server to tell you it's done.
configs/boot/spec-surge-server.rcS:
configs/boot/surge-server.rcS:
notify the client you're done starting the server.
H A Dnat-spec-surge-client.rcS1196:5e20797f314a Tue Nov 16 22:43:00 EST 2004 Lisa Hsu <hsul@eecs.umich.edu> add support for NAT under netperf stream, maerts, and spec-surge.

configs/boot/spec-surge-client.rcS:
configs/boot/surge-client.rcS:
fix this rcS - don't sleep, instead wait for the server to tell you it's done.
configs/boot/spec-surge-server.rcS:
configs/boot/surge-server.rcS:
notify the client you're done starting the server.
H A Dnat-spec-surge-server.rcS1196:5e20797f314a Tue Nov 16 22:43:00 EST 2004 Lisa Hsu <hsul@eecs.umich.edu> add support for NAT under netperf stream, maerts, and spec-surge.

configs/boot/spec-surge-client.rcS:
configs/boot/surge-client.rcS:
fix this rcS - don't sleep, instead wait for the server to tell you it's done.
configs/boot/spec-surge-server.rcS:
configs/boot/surge-server.rcS:
notify the client you're done starting the server.
H A Dnatbox-netperf.rcS1196:5e20797f314a Tue Nov 16 22:43:00 EST 2004 Lisa Hsu <hsul@eecs.umich.edu> add support for NAT under netperf stream, maerts, and spec-surge.

configs/boot/spec-surge-client.rcS:
configs/boot/surge-client.rcS:
fix this rcS - don't sleep, instead wait for the server to tell you it's done.
configs/boot/spec-surge-server.rcS:
configs/boot/surge-server.rcS:
notify the client you're done starting the server.
H A Dnatbox-spec-surge.rcS1196:5e20797f314a Tue Nov 16 22:43:00 EST 2004 Lisa Hsu <hsul@eecs.umich.edu> add support for NAT under netperf stream, maerts, and spec-surge.

configs/boot/spec-surge-client.rcS:
configs/boot/surge-client.rcS:
fix this rcS - don't sleep, instead wait for the server to tell you it's done.
configs/boot/spec-surge-server.rcS:
configs/boot/surge-server.rcS:
notify the client you're done starting the server.
H A Dspec-surge-server.rcSdiff 1196:5e20797f314a Tue Nov 16 22:43:00 EST 2004 Lisa Hsu <hsul@eecs.umich.edu> add support for NAT under netperf stream, maerts, and spec-surge.

configs/boot/spec-surge-client.rcS:
configs/boot/surge-client.rcS:
fix this rcS - don't sleep, instead wait for the server to tell you it's done.
configs/boot/spec-surge-server.rcS:
configs/boot/surge-server.rcS:
notify the client you're done starting the server.
H A Dsurge-client.rcSdiff 1196:5e20797f314a Tue Nov 16 22:43:00 EST 2004 Lisa Hsu <hsul@eecs.umich.edu> add support for NAT under netperf stream, maerts, and spec-surge.

configs/boot/spec-surge-client.rcS:
configs/boot/surge-client.rcS:
fix this rcS - don't sleep, instead wait for the server to tell you it's done.
configs/boot/spec-surge-server.rcS:
configs/boot/surge-server.rcS:
notify the client you're done starting the server.
H A Dsurge-server.rcSdiff 1196:5e20797f314a Tue Nov 16 22:43:00 EST 2004 Lisa Hsu <hsul@eecs.umich.edu> add support for NAT under netperf stream, maerts, and spec-surge.

configs/boot/spec-surge-client.rcS:
configs/boot/surge-client.rcS:
fix this rcS - don't sleep, instead wait for the server to tell you it's done.
configs/boot/spec-surge-server.rcS:
configs/boot/surge-server.rcS:
notify the client you're done starting the server.
/gem5/src/arch/sparc/isa/
H A Dbitfields.isadiff 7799:5d0f62927d75 Mon Dec 20 16:24:00 EST 2010 Gabe Black <gblack@eecs.umich.edu> Style: Replace some tabs with spaces.
/gem5/src/arch/x86/isa/
H A Dmain.isadiff 4348:5c21bdb46e6d Fri Apr 06 12:55:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Move the instruction specialization stuff out of the microassembler file, and added some comments to main.isa
/gem5/src/arch/x86/isa/microops/
H A Dmicroops.isadiff 4338:24d31b35bcf9 Wed Apr 04 19:35:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> The process of going from an instruction definition to an instruction to be returned by the decoder has been fleshed out more. The following steps describe how an instruction implementation becomes a StaticInst.

1. Microops are created. These are StaticInsts use templates to provide a basic form of polymorphism without having to make the microassembler smarter.
2. An instruction class is created which has a "templated" microcode program as it's docstring. The template parameters are refernced with ^ following by a number.
3. An instruction in the decoder references an instruction template using it's mnemonic. The parameters to it's format end up replacing the placeholders. These parameters describe a source for an operand which could be memory, a register, or an immediate. It it's a register, the register index is used. If it's memory, eventually a load/store will be pre/postpended to the instruction template and it's destination register will be used in place of the ^. If it's an immediate, the immediate is used. Some operand types, specifically those that come from the ModRM byte, need to be decoded further into memory vs. register versions. This is accomplished by making the decode_block text for these instructions another case statement based off ModRM.
4. Once all of the template parameters have been handled, the instruction goes throw the microcode assembler which resolves labels and creates a list of python op objects. If an operand is a register, it uses a % prefix, an immediate uses $, and a label uses @. If the operand is just letters, numbers, and underscores, it can appear immediately after the prefix. If it's not, it can be encolsed in non nested {}s.
5. If there is a single "op" object (which corresponds to a single microop) the decoder is set up to return it directly. If not, a macroop wrapper is created around it.

In the future, I'm considering seperating the operand type specialization from the template substitution step. A problem this introduces is that either the template arguments need to be kept around for the specialization step, or they need to be re-extracted. Re-extraction might be the way to go so that the operand formats can be coded directly into the micro assembler template without having to pass them in as parameters. I don't know if that's actually useful, though.

src/arch/x86/isa/decoder/one_byte_opcodes.isa:
src/arch/x86/isa/microasm.isa:
src/arch/x86/isa/microops/microops.isa:
src/arch/x86/isa/operands.isa:
src/arch/x86/isa/microops/base.isa:
Implemented polymorphic microops and changed around the microcode assembler syntax.
/gem5/util/
H A Dtracediffdiff 3080:5e384f5480af Mon Aug 28 12:48:00 EDT 2006 Steve Reinhardt <stever@eecs.umich.edu> Fix command for new options processing.
/gem5/src/dev/alpha/
H A Dbackdoor.hhdiff 9235:5aa4896ed55a Wed Sep 19 06:15:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> AddrRange: Transition from Range<T> to AddrRange

This patch takes the final plunge and transitions from the templated
Range class to the more specific AddrRange. In doing so it changes the
obvious Range<Addr> to AddrRange, and also bumps the range_map to be
AddrRangeMap.

In addition to the obvious changes, including the removal of redundant
includes, this patch also does some house keeping in preparing for the
introduction of address interleaving support in the ranges. The Range
class is also stripped of all the functionality that is never used.
H A Dtsunami_cchip.hhdiff 9235:5aa4896ed55a Wed Sep 19 06:15:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> AddrRange: Transition from Range<T> to AddrRange

This patch takes the final plunge and transitions from the templated
Range class to the more specific AddrRange. In doing so it changes the
obvious Range<Addr> to AddrRange, and also bumps the range_map to be
AddrRangeMap.

In addition to the obvious changes, including the removal of redundant
includes, this patch also does some house keeping in preparing for the
introduction of address interleaving support in the ranges. The Range
class is also stripped of all the functionality that is never used.
/gem5/src/dev/arm/
H A Damba_device.hhdiff 9235:5aa4896ed55a Wed Sep 19 06:15:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> AddrRange: Transition from Range<T> to AddrRange

This patch takes the final plunge and transitions from the templated
Range class to the more specific AddrRange. In doing so it changes the
obvious Range<Addr> to AddrRange, and also bumps the range_map to be
AddrRangeMap.

In addition to the obvious changes, including the removal of redundant
includes, this patch also does some house keeping in preparing for the
introduction of address interleaving support in the ranges. The Range
class is also stripped of all the functionality that is never used.

Completed in 93 milliseconds

<<11121314151617181920>>