arch-arm: Replace occ of opModeToEL(currOpMode/cpsr) with currEL

Change-Id: I739a9be03ea5caa63540c62fd110eee86a058c4c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20252
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Implement LoadAcquire/StoreRelease in AArch32

This patch is implementing LoadAcquire/StoreRelease instructions in
AArch32, which were added in ARMv8-A only and where not present in
ARMv7.

Change-Id: I5e26459971d0b183a955cd7b0c9c7eaffef453be
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15817
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: IsStoreConditional flag set depending on flavor

This patch is aligning A32 with A64 where the IsStoreConditional flag
doesn't have to be specified manually in the instruction implementation,
but will be automatically added to any exclusive store.

Change-Id: Id02ed6fc2beeca6d125017393714a7c6eb3d8a33
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15816
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: BadMode checking if corresponding EL is implemented

The old utility function called badMode was only checking if the mode
passed as an argument was a recognized mode. It was not checking if the
corresponding mode/EL was implemented. That function has been renamed to
unknownMode and a new badMode has been introduced. This is used by the
cpsrWriteByInstruction function. In this way any try to change the
execution mode won't succeed if the mode hasn't been implemented.

Change-Id: Ibfe385c5465b904acc0d2eb9647710891d72c9df
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11196
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Signal an event when executing store exclusives

When a store exclusive is executed, whether it is successful or not,
the exclusives monitor is cleared and therefore we need to signal an
event for the PE.

Change-Id: I383c88c769c0ac5f5d36c4b5d39c9681134d3a20
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4480
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arm: Add support for ARMv8 (AArch64 & AArch32)

Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black

ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.

By using an underscore, the "." is still available and can unambiguously be
used to refer to members of a structure if an operand is a structure, class,
etc. This change mostly just replaces the appropriate "."s with "_"s, but
there were also a few places where the ISA descriptions where handling the
extensions themselves and had their own regular expressions to update. The
regular expressions in the isa parser were updated as well. It also now
looks for one of the defined type extensions specifically after connecting "_"
where before it would look for any sequence of characters after a "."
following an operand name and try to use it as the extension. This helps to
disambiguate cases where a "_" may legitimately be part of an operand name but
not separate the name from the type suffix.

Because leaving the "_" and suffix on the variable name still leaves a valid
C++ identifier and all extensions need to be consistent in a given context, I
considered leaving them on as a breadcrumb that would show what the intended
type was for that operand. Unfortunately the operands can be referred to in
code templates, the Mem operand in particular, and since the exact type of Mem
can be different for different uses of the same template, that broke things.

ARM: Construct the predicate test register for more instruction programatically.

If one of the condition codes isn't being used in the execution we should only
read it if the instruction might be dependent on it. With the preeceding changes
there are several more cases where we should dynamically pick instead of assuming
as we did before.

ARM: Further break up condition code into NZ, C, V bits.

Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.

ARM: Break up condition codes into normal flags, saturation, and simd.

This change splits out the condcodes from being one monolithic register
into three blocks that are updated independently. This allows CPUs
to not have to do RMW operations on the flags registers for instructions
that don't write all flags.

ARM: Previous change didn't end up setting instFlags, this does.

ARM: Mark store conditionals as such.

ARM: Fix SRS instruction to micro-code memory operation and register update.

Previously the SRS instruction attempted to writeback in initiateAcc() which
worked until a recent change, but was incorrect.

ARM: Use fewer micro-ops for register update loads if possible.

Allow some loads that update the base register to use just two micro-ops. three
micro-ops are only used if the destination register matches the offset register
or the PC is the destination regsiter. If the PC is updated it needs to be
the last micro-op otherwise O3 will mispredict.

ARM: Fix VFP enabled checks for mem instructions

ARM: Exclusive accesses must be double word aligned

ARM: Clean up the ISA desc portion of the ARM memory instructions.

ARM: Implement the ARM TLB/Tablewalker. Needs performance improvements.

ARM: Implement the vstr instruction.

ARM: Implement the SRS instruction.

ARM: Implement the strex instructions.

ARM: Respect the E bit of the CPSR when doing loads and stores.

ARM: Implement the V7 version of alignment checking.

ARM: Explicitly keep track of the second destination for double loads/stores.

ARM: Remove the special naming for the new memory instructions.
These are the only memory instructions now.

ARM: Pull double memory instructions out of the decoder.

ARM: Define the store instructions from outside the decoder.