str.isa revision 7296:27c60324ec4d
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Redistribution and use in source and binary forms, with or without 16// modification, are permitted provided that the following conditions are 17// met: redistributions of source code must retain the above copyright 18// notice, this list of conditions and the following disclaimer; 19// redistributions in binary form must reproduce the above copyright 20// notice, this list of conditions and the following disclaimer in the 21// documentation and/or other materials provided with the distribution; 22// neither the name of the copyright holders nor the names of its 23// contributors may be used to endorse or promote products derived from 24// this software without specific prior written permission. 25// 26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37// 38// Authors: Gabe Black 39 40let {{ 41 42 header_output = "" 43 decoder_output = "" 44 exec_output = "" 45 46 def storeImmClassName(post, add, writeback, \ 47 size=4, sign=False, user=False): 48 return memClassName("STORE_IMM", post, add, writeback, 49 size, sign, user) 50 51 def storeRegClassName(post, add, writeback, \ 52 size=4, sign=False, user=False): 53 return memClassName("STORE_REG", post, add, writeback, 54 size, sign, user) 55 56 def storeDoubleImmClassName(post, add, writeback): 57 return memClassName("STORE_IMMD", post, add, writeback, 58 4, False, False) 59 60 def storeDoubleRegClassName(post, add, writeback): 61 return memClassName("STORE_REGD", post, add, writeback, 62 4, False, False) 63 64 def emitStore(name, Name, imm, eaCode, accCode, \ 65 memFlags, instFlags, base, double=False): 66 global header_output, decoder_output, exec_output 67 68 (newHeader, 69 newDecoder, 70 newExec) = loadStoreBase(name, Name, imm, 71 eaCode, accCode, 72 memFlags, instFlags, double, 73 base, execTemplateBase = 'Store') 74 75 header_output += newHeader 76 decoder_output += newDecoder 77 exec_output += newExec 78 79 def buildImmStore(mnem, post, add, writeback, \ 80 size=4, sign=False, user=False): 81 name = mnem 82 Name = storeImmClassName(post, add, writeback, \ 83 size, sign, user) 84 85 if add: 86 op = " +" 87 else: 88 op = " -" 89 90 offset = op + " imm" 91 eaCode = "EA = Base" 92 if not post: 93 eaCode += offset 94 eaCode += ";" 95 96 accCode = "Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);" % \ 97 { "suffix" : buildMemSuffix(sign, size) } 98 if writeback: 99 accCode += "Base = Base %s;\n" % offset 100 base = buildMemBase("MemoryImm", post, writeback) 101 102 emitStore(name, Name, True, eaCode, accCode, \ 103 ["ArmISA::TLB::MustBeOne", \ 104 "ArmISA::TLB::AllowUnaligned", \ 105 "%d" % (size - 1)], [], base) 106 107 def buildRegStore(mnem, post, add, writeback, \ 108 size=4, sign=False, user=False): 109 name = mnem 110 Name = storeRegClassName(post, add, writeback, 111 size, sign, user) 112 113 if add: 114 op = " +" 115 else: 116 op = " -" 117 118 offset = op + " shift_rm_imm(Index, shiftAmt," + \ 119 " shiftType, CondCodes<29:>)" 120 eaCode = "EA = Base" 121 if not post: 122 eaCode += offset 123 eaCode += ";" 124 125 accCode = "Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);" % \ 126 { "suffix" : buildMemSuffix(sign, size) } 127 if writeback: 128 accCode += "Base = Base %s;\n" % offset 129 base = buildMemBase("MemoryReg", post, writeback) 130 131 emitStore(name, Name, False, eaCode, accCode, \ 132 ["ArmISA::TLB::MustBeOne", \ 133 "ArmISA::TLB::AllowUnaligned", \ 134 "%d" % (size - 1)], [], base) 135 136 def buildDoubleImmStore(mnem, post, add, writeback): 137 name = mnem 138 Name = storeDoubleImmClassName(post, add, writeback) 139 140 if add: 141 op = " +" 142 else: 143 op = " -" 144 145 offset = op + " imm" 146 eaCode = "EA = Base" 147 if not post: 148 eaCode += offset 149 eaCode += ";" 150 151 accCode = ''' 152 CPSR cpsr = Cpsr; 153 Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) | 154 ((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32); 155 ''' 156 if writeback: 157 accCode += "Base = Base %s;\n" % offset 158 base = buildMemBase("MemoryDImm", post, writeback) 159 160 emitStore(name, Name, True, eaCode, accCode, \ 161 ["ArmISA::TLB::MustBeOne", 162 "ArmISA::TLB::AlignWord"], [], base, double=True) 163 164 def buildDoubleRegStore(mnem, post, add, writeback): 165 name = mnem 166 Name = storeDoubleRegClassName(post, add, writeback) 167 168 if add: 169 op = " +" 170 else: 171 op = " -" 172 173 offset = op + " shift_rm_imm(Index, shiftAmt," + \ 174 " shiftType, CondCodes<29:>)" 175 eaCode = "EA = Base" 176 if not post: 177 eaCode += offset 178 eaCode += ";" 179 180 accCode = ''' 181 CPSR cpsr = Cpsr; 182 Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) | 183 ((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32); 184 ''' 185 if writeback: 186 accCode += "Base = Base %s;\n" % offset 187 base = buildMemBase("MemoryDReg", post, writeback) 188 189 emitStore(name, Name, False, eaCode, accCode, \ 190 ["ArmISA::TLB::MustBeOne", \ 191 "ArmISA::TLB::AlignWord"], [], base, double=True) 192 193 def buildStores(mnem, size=4, sign=False, user=False): 194 buildImmStore(mnem, True, True, True, size, sign, user) 195 buildRegStore(mnem, True, True, True, size, sign, user) 196 buildImmStore(mnem, True, False, True, size, sign, user) 197 buildRegStore(mnem, True, False, True, size, sign, user) 198 buildImmStore(mnem, False, True, True, size, sign, user) 199 buildRegStore(mnem, False, True, True, size, sign, user) 200 buildImmStore(mnem, False, False, True, size, sign, user) 201 buildRegStore(mnem, False, False, True, size, sign, user) 202 buildImmStore(mnem, False, True, False, size, sign, user) 203 buildRegStore(mnem, False, True, False, size, sign, user) 204 buildImmStore(mnem, False, False, False, size, sign, user) 205 buildRegStore(mnem, False, False, False, size, sign, user) 206 207 def buildDoubleStores(mnem): 208 buildDoubleImmStore(mnem, True, True, True) 209 buildDoubleRegStore(mnem, True, True, True) 210 buildDoubleImmStore(mnem, True, False, True) 211 buildDoubleRegStore(mnem, True, False, True) 212 buildDoubleImmStore(mnem, False, True, True) 213 buildDoubleRegStore(mnem, False, True, True) 214 buildDoubleImmStore(mnem, False, False, True) 215 buildDoubleRegStore(mnem, False, False, True) 216 buildDoubleImmStore(mnem, False, True, False) 217 buildDoubleRegStore(mnem, False, True, False) 218 buildDoubleImmStore(mnem, False, False, False) 219 buildDoubleRegStore(mnem, False, False, False) 220 221 buildStores("str") 222 buildStores("strt", user=True) 223 buildStores("strb", size=1) 224 buildStores("strbt", size=1, user=True) 225 buildStores("strh", size=2) 226 buildStores("strht", size=2, user=True) 227 228 buildDoubleStores("strd") 229}}; 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