str.isa revision 7746:79adfecb2b8a 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2010 ARM Limited
4// All rights reserved
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40let {{
41
42    header_output = ""
43    decoder_output = ""
44    exec_output = ""
45
46    class StoreInst(LoadStoreInst):
47        execBase = 'Store'
48
49        def __init__(self, mnem, post, add, writeback, size=4,
50                     sign=False, user=False, flavor="normal"):
51            super(StoreInst, self).__init__()
52
53            self.name = mnem
54            self.post = post
55            self.add = add
56            self.writeback = writeback
57            self.size = size
58            self.sign = sign
59            self.user = user
60            self.flavor = flavor
61
62            if self.add:
63                self.op = " +"
64            else:
65                self.op = " -"
66
67            self.memFlags = ["ArmISA::TLB::MustBeOne"]
68            self.codeBlobs = { "postacc_code" : "" }
69
70        def emitHelper(self, base = 'Memory', wbDecl = None):
71
72            global header_output, decoder_output, exec_output
73
74            codeBlobs = self.codeBlobs
75            codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
76            (newHeader,
77             newDecoder,
78             newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
79                                           self.memFlags, [], base, wbDecl)
80
81            header_output += newHeader
82            decoder_output += newDecoder
83            exec_output += newExec
84
85    class SrsInst(LoadStoreInst):
86        execBase = 'Store'
87        decConstBase = 'Srs'
88
89        def __init__(self, mnem, post, add, writeback):
90            super(SrsInst, self).__init__()
91            self.name = mnem
92            self.post = post
93            self.add = add
94            self.writeback = writeback
95
96            self.Name = "SRS_" + storeImmClassName(post, add, writeback, 8)
97
98        def emit(self):
99            offset = 0
100            if self.post != self.add:
101                offset += 4
102            if not self.add:
103                offset -= 8
104
105            eaCode = "EA = SpMode + %d;" % offset
106
107            wbDiff = -8
108            if self.add:
109                wbDiff = 8
110            accCode = '''
111            CPSR cpsr = Cpsr;
112            Mem.ud = (uint64_t)cSwap(LR.uw, cpsr.e) |
113                     ((uint64_t)cSwap(Spsr.uw, cpsr.e) << 32);
114            '''
115
116            global header_output, decoder_output, exec_output
117
118            codeBlobs = { "ea_code": eaCode,
119                          "memacc_code": accCode,
120                          "postacc_code": "" }
121            codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
122
123            wbDecl = None
124            if self.writeback:
125                wbDecl = '''MicroAddiUop(machInst,
126                              intRegInMode((OperatingMode)regMode, INTREG_SP),
127                              intRegInMode((OperatingMode)regMode, INTREG_SP),
128                              %d);''' % wbDiff
129
130            (newHeader,
131             newDecoder,
132             newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
133                 ["ArmISA::TLB::AlignWord", "ArmISA::TLB::MustBeOne"], [],
134                 'SrsOp', wbDecl)
135
136            header_output += newHeader
137            decoder_output += newDecoder
138            exec_output += newExec
139
140    class StoreImmInst(StoreInst):
141        def __init__(self, *args, **kargs):
142            super(StoreImmInst, self).__init__(*args, **kargs)
143            self.offset = self.op + " imm"
144
145            if self.add:
146                self.wbDecl = "MicroAddiUop(machInst, base, base, imm);"
147            else:
148                self.wbDecl = "MicroSubiUop(machInst, base, base, imm);"
149
150    class StoreRegInst(StoreInst):
151        def __init__(self, *args, **kargs):
152            super(StoreRegInst, self).__init__(*args, **kargs)
153            self.offset = self.op + " shift_rm_imm(Index, shiftAmt," + \
154                                    " shiftType, CondCodes<29:>)"
155            if self.add:
156                 self.wbDecl = '''
157                     MicroAddUop(machInst, base, base, index, shiftAmt, shiftType);
158                 '''
159            else:
160                 self.wbDecl = '''
161                     MicroSubUop(machInst, base, base, index, shiftAmt, shiftType);
162                 '''
163
164    class StoreSingle(StoreInst):
165        def __init__(self, *args, **kargs):
166            super(StoreSingle, self).__init__(*args, **kargs)
167
168            # Build the default class name
169            self.Name = self.nameFunc(self.post, self.add, self.writeback,
170                                      self.size, self.sign, self.user)
171
172            # Add memory request flags where necessary
173            self.memFlags.append("%d" % (self.size - 1))
174            if self.user:
175                self.memFlags.append("ArmISA::TLB::UserMode")
176
177            if self.flavor == "exclusive":
178                self.memFlags.append("Request::LLSC")
179            elif self.flavor != "fp":
180                self.memFlags.append("ArmISA::TLB::AllowUnaligned")
181
182            # Disambiguate the class name for different flavors of stores
183            if self.flavor != "normal":
184                self.Name = "%s_%s" % (self.name.upper(), self.Name)
185
186        def emit(self):
187            # Address computation
188            eaCode = "EA = Base"
189            if not self.post:
190                eaCode += self.offset
191            eaCode += ";"
192
193            if self.flavor == "fp":
194                eaCode += vfpEnabledCheckCode
195
196            self.codeBlobs["ea_code"] = eaCode
197
198            # Code that actually handles the access
199            if self.flavor == "fp":
200                accCode = 'Mem%(suffix)s = cSwap(FpDest.uw, ((CPSR)Cpsr).e);'
201            else:
202                accCode = \
203                    'Mem%(suffix)s = cSwap(Dest%(suffix)s, ((CPSR)Cpsr).e);'
204            accCode = accCode % \
205                { "suffix" : buildMemSuffix(self.sign, self.size) }
206
207            self.codeBlobs["memacc_code"] = accCode
208
209            # Push it out to the output files
210            base = buildMemBase(self.basePrefix, self.post, self.writeback)
211            wbDecl = None
212            if self.writeback:
213                wbDecl = self.wbDecl
214            self.emitHelper(base, wbDecl)
215
216    def storeImmClassName(post, add, writeback, size=4, sign=False, user=False):
217        return memClassName("STORE_IMM", post, add, writeback, size, sign, user)
218
219    class StoreImmEx(StoreImmInst, StoreSingle):
220        execBase = 'StoreEx'
221        decConstBase = 'StoreExImm'
222        basePrefix = 'MemoryExImm'
223        nameFunc = staticmethod(storeImmClassName)
224
225        def __init__(self, *args, **kargs):
226            super(StoreImmEx, self).__init__(*args, **kargs)
227            self.codeBlobs["postacc_code"] = "Result = !writeResult;"
228
229    class StoreImm(StoreImmInst, StoreSingle):
230        decConstBase = 'LoadStoreImm'
231        basePrefix = 'MemoryImm'
232        nameFunc = staticmethod(storeImmClassName)
233
234    def storeRegClassName(post, add, writeback, size=4, sign=False, user=False):
235        return memClassName("STORE_REG", post, add, writeback, size, sign, user)
236
237    class StoreReg(StoreRegInst, StoreSingle):
238        decConstBase = 'StoreReg'
239        basePrefix = 'MemoryReg'
240        nameFunc = staticmethod(storeRegClassName)
241
242    class StoreDouble(StoreInst):
243        def __init__(self, *args, **kargs):
244            super(StoreDouble, self).__init__(*args, **kargs)
245
246            # Build the default class name
247            self.Name = self.nameFunc(self.post, self.add, self.writeback)
248
249            # Add memory request flags where necessary
250            if self.flavor == "exclusive":
251                self.memFlags.append("Request::LLSC")
252                self.memFlags.append("ArmISA::TLB::AlignDoubleWord")
253            else:
254                self.memFlags.append("ArmISA::TLB::AlignWord")
255
256            # Disambiguate the class name for different flavors of stores
257            if self.flavor != "normal":
258                self.Name = "%s_%s" % (self.name.upper(), self.Name)
259
260        def emit(self):
261            # Address computation code
262            eaCode = "EA = Base"
263            if not self.post:
264                eaCode += self.offset
265            eaCode += ";"
266
267            if self.flavor == "fp":
268                eaCode += vfpEnabledCheckCode
269
270            self.codeBlobs["ea_code"] = eaCode
271
272            # Code that actually handles the access
273            if self.flavor == "fp":
274                accCode = '''
275                uint64_t swappedMem  = (uint64_t)FpDest.uw |
276                                       ((uint64_t)FpDest2.uw << 32);
277                Mem.ud = cSwap(swappedMem, ((CPSR)Cpsr).e);
278                '''
279            else:
280                accCode = '''
281                CPSR cpsr = Cpsr;
282                Mem.ud = (uint64_t)cSwap(Dest.uw, cpsr.e) |
283                         ((uint64_t)cSwap(Dest2.uw, cpsr.e) << 32);
284                '''
285
286            self.codeBlobs["memacc_code"] = accCode
287
288            # Push it out to the output files
289            base = buildMemBase(self.basePrefix, self.post, self.writeback)
290            wbDecl = None
291            if self.writeback:
292                wbDecl = self.wbDecl
293            self.emitHelper(base, wbDecl)
294
295    def storeDoubleImmClassName(post, add, writeback):
296        return memClassName("STORE_IMMD", post, add, writeback, 4, False, False)
297
298    class StoreDoubleImmEx(StoreImmInst, StoreDouble):
299        execBase = 'StoreEx'
300        decConstBase = 'StoreExDImm'
301        basePrefix = 'MemoryExDImm'
302        nameFunc = staticmethod(storeDoubleImmClassName)
303
304        def __init__(self, *args, **kargs):
305            super(StoreDoubleImmEx, self).__init__(*args, **kargs)
306            self.codeBlobs["postacc_code"] = "Result = !writeResult;"
307
308    class StoreDoubleImm(StoreImmInst, StoreDouble):
309        decConstBase = 'LoadStoreDImm'
310        basePrefix = 'MemoryDImm'
311        nameFunc = staticmethod(storeDoubleImmClassName)
312
313    def storeDoubleRegClassName(post, add, writeback):
314        return memClassName("STORE_REGD", post, add, writeback, 4, False, False)
315
316    class StoreDoubleReg(StoreRegInst, StoreDouble):
317        decConstBase = 'StoreDReg'
318        basePrefix = 'MemoryDReg'
319        nameFunc = staticmethod(storeDoubleRegClassName)
320
321    def buildStores(mnem, size=4, sign=False, user=False):
322        StoreImm(mnem, True, True, True, size, sign, user).emit()
323        StoreReg(mnem, True, True, True, size, sign, user).emit()
324        StoreImm(mnem, True, False, True, size, sign, user).emit()
325        StoreReg(mnem, True, False, True, size, sign, user).emit()
326        StoreImm(mnem, False, True, True, size, sign, user).emit()
327        StoreReg(mnem, False, True, True, size, sign, user).emit()
328        StoreImm(mnem, False, False, True, size, sign, user).emit()
329        StoreReg(mnem, False, False, True, size, sign, user).emit()
330        StoreImm(mnem, False, True, False, size, sign, user).emit()
331        StoreReg(mnem, False, True, False, size, sign, user).emit()
332        StoreImm(mnem, False, False, False, size, sign, user).emit()
333        StoreReg(mnem, False, False, False, size, sign, user).emit()
334
335    def buildDoubleStores(mnem):
336        StoreDoubleImm(mnem, True, True, True).emit()
337        StoreDoubleReg(mnem, True, True, True).emit()
338        StoreDoubleImm(mnem, True, False, True).emit()
339        StoreDoubleReg(mnem, True, False, True).emit()
340        StoreDoubleImm(mnem, False, True, True).emit()
341        StoreDoubleReg(mnem, False, True, True).emit()
342        StoreDoubleImm(mnem, False, False, True).emit()
343        StoreDoubleReg(mnem, False, False, True).emit()
344        StoreDoubleImm(mnem, False, True, False).emit()
345        StoreDoubleReg(mnem, False, True, False).emit()
346        StoreDoubleImm(mnem, False, False, False).emit()
347        StoreDoubleReg(mnem, False, False, False).emit()
348
349    def buildSrsStores(mnem):
350        SrsInst(mnem, True, True, True).emit()
351        SrsInst(mnem, True, True, False).emit()
352        SrsInst(mnem, True, False, True).emit()
353        SrsInst(mnem, True, False, False).emit()
354        SrsInst(mnem, False, True, True).emit()
355        SrsInst(mnem, False, True, False).emit()
356        SrsInst(mnem, False, False, True).emit()
357        SrsInst(mnem, False, False, False).emit()
358
359    buildStores("str")
360    buildStores("strt", user=True)
361    buildStores("strb", size=1)
362    buildStores("strbt", size=1, user=True)
363    buildStores("strh", size=2)
364    buildStores("strht", size=2, user=True)
365
366    buildSrsStores("srs")
367
368    buildDoubleStores("strd")
369
370    StoreImmEx("strex", False, True, False, size=4, flavor="exclusive").emit()
371    StoreImmEx("strexh", False, True, False, size=2, flavor="exclusive").emit()
372    StoreImmEx("strexb", False, True, False, size=1, flavor="exclusive").emit()
373    StoreDoubleImmEx("strexd", False, True, False, flavor="exclusive").emit()
374
375    StoreImm("vstr", False, True, False, size=4, flavor="fp").emit()
376    StoreImm("vstr", False, False, False, size=4, flavor="fp").emit()
377    StoreDoubleImm("vstr", False, True, False, flavor="fp").emit()
378    StoreDoubleImm("vstr", False, False, False, flavor="fp").emit()
379}};
380