17639Sgblack@eecs.umich.edu// -*- mode:c++ -*- 27639Sgblack@eecs.umich.edu 313978Sciro.santilli@arm.com// Copyright (c) 2010-2011, 2015, 2019 ARM Limited 47639Sgblack@eecs.umich.edu// All rights reserved 57639Sgblack@eecs.umich.edu// 67639Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77639Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87639Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97639Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107639Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117639Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127639Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137639Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147639Sgblack@eecs.umich.edu// 157639Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 167639Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 177639Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 187639Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 197639Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 207639Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 217639Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 227639Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 237639Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247639Sgblack@eecs.umich.edu// this software without specific prior written permission. 257639Sgblack@eecs.umich.edu// 267639Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 277639Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 287639Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 297639Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 307639Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 317639Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 327639Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 337639Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 347639Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 357639Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 367639Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 377639Sgblack@eecs.umich.edu// 387639Sgblack@eecs.umich.edu// Authors: Gabe Black 397639Sgblack@eecs.umich.edu 407639Sgblack@eecs.umich.eduoutput header {{ 417639Sgblack@eecs.umich.edu template <template <typename T> class Base> 427639Sgblack@eecs.umich.edu StaticInstPtr 437639Sgblack@eecs.umich.edu decodeNeonUThreeUReg(unsigned size, 447639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 457639Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2) 467639Sgblack@eecs.umich.edu { 477639Sgblack@eecs.umich.edu switch (size) { 487639Sgblack@eecs.umich.edu case 0: 497639Sgblack@eecs.umich.edu return new Base<uint8_t>(machInst, dest, op1, op2); 507639Sgblack@eecs.umich.edu case 1: 517639Sgblack@eecs.umich.edu return new Base<uint16_t>(machInst, dest, op1, op2); 527639Sgblack@eecs.umich.edu case 2: 537639Sgblack@eecs.umich.edu return new Base<uint32_t>(machInst, dest, op1, op2); 547639Sgblack@eecs.umich.edu case 3: 557639Sgblack@eecs.umich.edu return new Base<uint64_t>(machInst, dest, op1, op2); 567639Sgblack@eecs.umich.edu default: 577639Sgblack@eecs.umich.edu return new Unknown(machInst); 587639Sgblack@eecs.umich.edu } 597639Sgblack@eecs.umich.edu } 607639Sgblack@eecs.umich.edu 6113979Sciro.santilli@arm.com template <class BaseS, class BaseD> 6213979Sciro.santilli@arm.com StaticInstPtr 6313979Sciro.santilli@arm.com decodeNeonSizeSingleDouble(unsigned size, 6413979Sciro.santilli@arm.com ExtMachInst machInst, IntRegIndex dest, 6513979Sciro.santilli@arm.com IntRegIndex op1, IntRegIndex op2) 6613979Sciro.santilli@arm.com { 6713979Sciro.santilli@arm.com switch (size) { 6813979Sciro.santilli@arm.com case 2: 6913979Sciro.santilli@arm.com return new BaseS(machInst, dest, op1, op2); 7013979Sciro.santilli@arm.com case 3: 7113979Sciro.santilli@arm.com return new BaseD(machInst, dest, op1, op2); 7213979Sciro.santilli@arm.com default: 7313979Sciro.santilli@arm.com return new Unknown(machInst); 7413979Sciro.santilli@arm.com } 7513979Sciro.santilli@arm.com } 7613979Sciro.santilli@arm.com 777639Sgblack@eecs.umich.edu template <template <typename T> class Base> 787639Sgblack@eecs.umich.edu StaticInstPtr 797639Sgblack@eecs.umich.edu decodeNeonSThreeUReg(unsigned size, 807639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 817639Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2) 827639Sgblack@eecs.umich.edu { 837639Sgblack@eecs.umich.edu switch (size) { 847639Sgblack@eecs.umich.edu case 0: 857639Sgblack@eecs.umich.edu return new Base<int8_t>(machInst, dest, op1, op2); 867639Sgblack@eecs.umich.edu case 1: 877639Sgblack@eecs.umich.edu return new Base<int16_t>(machInst, dest, op1, op2); 887639Sgblack@eecs.umich.edu case 2: 897639Sgblack@eecs.umich.edu return new Base<int32_t>(machInst, dest, op1, op2); 907639Sgblack@eecs.umich.edu case 3: 917639Sgblack@eecs.umich.edu return new Base<int64_t>(machInst, dest, op1, op2); 927639Sgblack@eecs.umich.edu default: 937639Sgblack@eecs.umich.edu return new Unknown(machInst); 947639Sgblack@eecs.umich.edu } 957639Sgblack@eecs.umich.edu } 967639Sgblack@eecs.umich.edu 977639Sgblack@eecs.umich.edu template <template <typename T> class Base> 987639Sgblack@eecs.umich.edu StaticInstPtr 997639Sgblack@eecs.umich.edu decodeNeonUSThreeUReg(bool notSigned, unsigned size, 1007639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 1017639Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2) 1027639Sgblack@eecs.umich.edu { 1037639Sgblack@eecs.umich.edu if (notSigned) { 1047639Sgblack@eecs.umich.edu return decodeNeonUThreeUReg<Base>(size, machInst, dest, op1, op2); 1057639Sgblack@eecs.umich.edu } else { 1067639Sgblack@eecs.umich.edu return decodeNeonSThreeUReg<Base>(size, machInst, dest, op1, op2); 1077639Sgblack@eecs.umich.edu } 1087639Sgblack@eecs.umich.edu } 1097639Sgblack@eecs.umich.edu 1107639Sgblack@eecs.umich.edu template <template <typename T> class Base> 1117639Sgblack@eecs.umich.edu StaticInstPtr 1127639Sgblack@eecs.umich.edu decodeNeonUThreeUSReg(unsigned size, 11310037SARM gem5 Developers ExtMachInst machInst, IntRegIndex dest, 11410037SARM gem5 Developers IntRegIndex op1, IntRegIndex op2) 1157639Sgblack@eecs.umich.edu { 1167639Sgblack@eecs.umich.edu switch (size) { 1177639Sgblack@eecs.umich.edu case 0: 1187639Sgblack@eecs.umich.edu return new Base<uint8_t>(machInst, dest, op1, op2); 1197639Sgblack@eecs.umich.edu case 1: 1207639Sgblack@eecs.umich.edu return new Base<uint16_t>(machInst, dest, op1, op2); 1217639Sgblack@eecs.umich.edu case 2: 1227639Sgblack@eecs.umich.edu return new Base<uint32_t>(machInst, dest, op1, op2); 1237639Sgblack@eecs.umich.edu default: 1247639Sgblack@eecs.umich.edu return new Unknown(machInst); 1257639Sgblack@eecs.umich.edu } 1267639Sgblack@eecs.umich.edu } 1277639Sgblack@eecs.umich.edu 1287639Sgblack@eecs.umich.edu template <template <typename T> class Base> 1297639Sgblack@eecs.umich.edu StaticInstPtr 1307639Sgblack@eecs.umich.edu decodeNeonSThreeUSReg(unsigned size, 13110037SARM gem5 Developers ExtMachInst machInst, IntRegIndex dest, 13210037SARM gem5 Developers IntRegIndex op1, IntRegIndex op2) 1337639Sgblack@eecs.umich.edu { 1347639Sgblack@eecs.umich.edu switch (size) { 1357639Sgblack@eecs.umich.edu case 0: 1367639Sgblack@eecs.umich.edu return new Base<int8_t>(machInst, dest, op1, op2); 1377639Sgblack@eecs.umich.edu case 1: 1387639Sgblack@eecs.umich.edu return new Base<int16_t>(machInst, dest, op1, op2); 1397639Sgblack@eecs.umich.edu case 2: 1407639Sgblack@eecs.umich.edu return new Base<int32_t>(machInst, dest, op1, op2); 1417639Sgblack@eecs.umich.edu default: 1427639Sgblack@eecs.umich.edu return new Unknown(machInst); 1437639Sgblack@eecs.umich.edu } 1447639Sgblack@eecs.umich.edu } 1457639Sgblack@eecs.umich.edu 1467639Sgblack@eecs.umich.edu template <template <typename T> class Base> 1477639Sgblack@eecs.umich.edu StaticInstPtr 14810037SARM gem5 Developers decodeNeonSThreeHAndWReg(unsigned size, ExtMachInst machInst, 14910037SARM gem5 Developers IntRegIndex dest, IntRegIndex op1, 15010037SARM gem5 Developers IntRegIndex op2) 15110037SARM gem5 Developers { 15210037SARM gem5 Developers switch (size) { 15310037SARM gem5 Developers case 1: 15410037SARM gem5 Developers return new Base<int16_t>(machInst, dest, op1, op2); 15510037SARM gem5 Developers case 2: 15610037SARM gem5 Developers return new Base<int32_t>(machInst, dest, op1, op2); 15710037SARM gem5 Developers default: 15810037SARM gem5 Developers return new Unknown(machInst); 15910037SARM gem5 Developers } 16010037SARM gem5 Developers } 16110037SARM gem5 Developers 16210037SARM gem5 Developers template <template <typename T> class Base> 16310037SARM gem5 Developers StaticInstPtr 16410037SARM gem5 Developers decodeNeonSThreeImmHAndWReg(unsigned size, ExtMachInst machInst, 16510037SARM gem5 Developers IntRegIndex dest, IntRegIndex op1, 16610037SARM gem5 Developers IntRegIndex op2, uint64_t imm) 16710037SARM gem5 Developers { 16810037SARM gem5 Developers switch (size) { 16910037SARM gem5 Developers case 1: 17010037SARM gem5 Developers return new Base<int16_t>(machInst, dest, op1, op2, imm); 17110037SARM gem5 Developers case 2: 17210037SARM gem5 Developers return new Base<int32_t>(machInst, dest, op1, op2, imm); 17310037SARM gem5 Developers default: 17410037SARM gem5 Developers return new Unknown(machInst); 17510037SARM gem5 Developers } 17610037SARM gem5 Developers } 17710037SARM gem5 Developers 17810037SARM gem5 Developers template <template <typename T> class Base> 17910037SARM gem5 Developers StaticInstPtr 1807639Sgblack@eecs.umich.edu decodeNeonUSThreeUSReg(bool notSigned, unsigned size, 1817639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 1827639Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2) 1837639Sgblack@eecs.umich.edu { 1847639Sgblack@eecs.umich.edu if (notSigned) { 1857639Sgblack@eecs.umich.edu return decodeNeonUThreeUSReg<Base>( 1867639Sgblack@eecs.umich.edu size, machInst, dest, op1, op2); 1877639Sgblack@eecs.umich.edu } else { 1887639Sgblack@eecs.umich.edu return decodeNeonSThreeUSReg<Base>( 1897639Sgblack@eecs.umich.edu size, machInst, dest, op1, op2); 1907639Sgblack@eecs.umich.edu } 1917639Sgblack@eecs.umich.edu } 1927639Sgblack@eecs.umich.edu 1937639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 1947639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 1957639Sgblack@eecs.umich.edu StaticInstPtr 1967639Sgblack@eecs.umich.edu decodeNeonUThreeSReg(bool q, unsigned size, 1977639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 1987639Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2) 1997639Sgblack@eecs.umich.edu { 2007639Sgblack@eecs.umich.edu if (q) { 2017639Sgblack@eecs.umich.edu return decodeNeonUThreeUSReg<BaseQ>( 2027639Sgblack@eecs.umich.edu size, machInst, dest, op1, op2); 2037639Sgblack@eecs.umich.edu } else { 2047639Sgblack@eecs.umich.edu return decodeNeonUThreeUSReg<BaseD>( 2057639Sgblack@eecs.umich.edu size, machInst, dest, op1, op2); 2067639Sgblack@eecs.umich.edu } 2077639Sgblack@eecs.umich.edu } 2087639Sgblack@eecs.umich.edu 2097639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 2107639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 2117639Sgblack@eecs.umich.edu StaticInstPtr 2127639Sgblack@eecs.umich.edu decodeNeonSThreeSReg(bool q, unsigned size, 2137639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 2147639Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2) 2157639Sgblack@eecs.umich.edu { 2167639Sgblack@eecs.umich.edu if (q) { 2177639Sgblack@eecs.umich.edu return decodeNeonSThreeUSReg<BaseQ>( 2187639Sgblack@eecs.umich.edu size, machInst, dest, op1, op2); 2197639Sgblack@eecs.umich.edu } else { 2207639Sgblack@eecs.umich.edu return decodeNeonSThreeUSReg<BaseD>( 2217639Sgblack@eecs.umich.edu size, machInst, dest, op1, op2); 2227639Sgblack@eecs.umich.edu } 2237639Sgblack@eecs.umich.edu } 2247639Sgblack@eecs.umich.edu 2257639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 2267639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 2277639Sgblack@eecs.umich.edu StaticInstPtr 22810037SARM gem5 Developers decodeNeonSThreeXReg(bool q, unsigned size, 22910037SARM gem5 Developers ExtMachInst machInst, IntRegIndex dest, 23010037SARM gem5 Developers IntRegIndex op1, IntRegIndex op2) 23110037SARM gem5 Developers { 23210037SARM gem5 Developers if (q) { 23310037SARM gem5 Developers return decodeNeonSThreeUReg<BaseQ>( 23410037SARM gem5 Developers size, machInst, dest, op1, op2); 23510037SARM gem5 Developers } else { 23610037SARM gem5 Developers return decodeNeonSThreeUSReg<BaseD>( 23710037SARM gem5 Developers size, machInst, dest, op1, op2); 23810037SARM gem5 Developers } 23910037SARM gem5 Developers } 24010037SARM gem5 Developers 24110037SARM gem5 Developers template <template <typename T> class BaseD, 24210037SARM gem5 Developers template <typename T> class BaseQ> 24310037SARM gem5 Developers StaticInstPtr 24410037SARM gem5 Developers decodeNeonUThreeXReg(bool q, unsigned size, 24510037SARM gem5 Developers ExtMachInst machInst, IntRegIndex dest, 24610037SARM gem5 Developers IntRegIndex op1, IntRegIndex op2) 24710037SARM gem5 Developers { 24810037SARM gem5 Developers if (q) { 24910037SARM gem5 Developers return decodeNeonUThreeUReg<BaseQ>( 25010037SARM gem5 Developers size, machInst, dest, op1, op2); 25110037SARM gem5 Developers } else { 25210037SARM gem5 Developers return decodeNeonUThreeUSReg<BaseD>( 25310037SARM gem5 Developers size, machInst, dest, op1, op2); 25410037SARM gem5 Developers } 25510037SARM gem5 Developers } 25610037SARM gem5 Developers 25710037SARM gem5 Developers template <template <typename T> class BaseD, 25810037SARM gem5 Developers template <typename T> class BaseQ> 25910037SARM gem5 Developers StaticInstPtr 2607639Sgblack@eecs.umich.edu decodeNeonUSThreeSReg(bool q, bool notSigned, unsigned size, 2617639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 2627639Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2) 2637639Sgblack@eecs.umich.edu { 2647639Sgblack@eecs.umich.edu if (notSigned) { 2657639Sgblack@eecs.umich.edu return decodeNeonUThreeSReg<BaseD, BaseQ>( 2667639Sgblack@eecs.umich.edu q, size, machInst, dest, op1, op2); 2677639Sgblack@eecs.umich.edu } else { 2687639Sgblack@eecs.umich.edu return decodeNeonSThreeSReg<BaseD, BaseQ>( 2697639Sgblack@eecs.umich.edu q, size, machInst, dest, op1, op2); 2707639Sgblack@eecs.umich.edu } 2717639Sgblack@eecs.umich.edu } 2727639Sgblack@eecs.umich.edu 2737639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 2747639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 2757639Sgblack@eecs.umich.edu StaticInstPtr 2767639Sgblack@eecs.umich.edu decodeNeonUThreeReg(bool q, unsigned size, 2777639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 2787639Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2) 2797639Sgblack@eecs.umich.edu { 2807639Sgblack@eecs.umich.edu if (q) { 2817639Sgblack@eecs.umich.edu return decodeNeonUThreeUReg<BaseQ>( 2827639Sgblack@eecs.umich.edu size, machInst, dest, op1, op2); 2837639Sgblack@eecs.umich.edu } else { 2847639Sgblack@eecs.umich.edu return decodeNeonUThreeUReg<BaseD>( 2857639Sgblack@eecs.umich.edu size, machInst, dest, op1, op2); 2867639Sgblack@eecs.umich.edu } 2877639Sgblack@eecs.umich.edu } 2887639Sgblack@eecs.umich.edu 2897639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 2907639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 2917639Sgblack@eecs.umich.edu StaticInstPtr 2927639Sgblack@eecs.umich.edu decodeNeonSThreeReg(bool q, unsigned size, 2937639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 2947639Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2) 2957639Sgblack@eecs.umich.edu { 2967639Sgblack@eecs.umich.edu if (q) { 2977639Sgblack@eecs.umich.edu return decodeNeonSThreeUReg<BaseQ>( 2987639Sgblack@eecs.umich.edu size, machInst, dest, op1, op2); 2997639Sgblack@eecs.umich.edu } else { 3007639Sgblack@eecs.umich.edu return decodeNeonSThreeUReg<BaseD>( 3017639Sgblack@eecs.umich.edu size, machInst, dest, op1, op2); 3027639Sgblack@eecs.umich.edu } 3037639Sgblack@eecs.umich.edu } 3047639Sgblack@eecs.umich.edu 3057639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 3067639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 3077639Sgblack@eecs.umich.edu StaticInstPtr 3087639Sgblack@eecs.umich.edu decodeNeonUSThreeReg(bool q, bool notSigned, unsigned size, 3097639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 3107639Sgblack@eecs.umich.edu IntRegIndex op1, IntRegIndex op2) 3117639Sgblack@eecs.umich.edu { 3127639Sgblack@eecs.umich.edu if (notSigned) { 3137639Sgblack@eecs.umich.edu return decodeNeonUThreeReg<BaseD, BaseQ>( 3147639Sgblack@eecs.umich.edu q, size, machInst, dest, op1, op2); 3157639Sgblack@eecs.umich.edu } else { 3167639Sgblack@eecs.umich.edu return decodeNeonSThreeReg<BaseD, BaseQ>( 3177639Sgblack@eecs.umich.edu q, size, machInst, dest, op1, op2); 3187639Sgblack@eecs.umich.edu } 3197639Sgblack@eecs.umich.edu } 3207639Sgblack@eecs.umich.edu 3217639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 3227639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 3237639Sgblack@eecs.umich.edu StaticInstPtr 32410037SARM gem5 Developers decodeNeonUThreeFpReg(bool q, unsigned size, ExtMachInst machInst, 32510037SARM gem5 Developers IntRegIndex dest, IntRegIndex op1, IntRegIndex op2) 32610037SARM gem5 Developers { 32710037SARM gem5 Developers if (q) { 32810037SARM gem5 Developers if (size) 32910037SARM gem5 Developers return new BaseQ<uint64_t>(machInst, dest, op1, op2); 33010037SARM gem5 Developers else 33110037SARM gem5 Developers return new BaseQ<uint32_t>(machInst, dest, op1, op2); 33210037SARM gem5 Developers } else { 33310037SARM gem5 Developers if (size) 33410037SARM gem5 Developers return new Unknown(machInst); 33510037SARM gem5 Developers else 33610037SARM gem5 Developers return new BaseD<uint32_t>(machInst, dest, op1, op2); 33710037SARM gem5 Developers } 33810037SARM gem5 Developers } 33910037SARM gem5 Developers 34010037SARM gem5 Developers template <template <typename T> class Base> 34110037SARM gem5 Developers StaticInstPtr 34210037SARM gem5 Developers decodeNeonUThreeScFpReg(bool size, ExtMachInst machInst, 34310037SARM gem5 Developers IntRegIndex dest, IntRegIndex op1, IntRegIndex op2) 34410037SARM gem5 Developers { 34510037SARM gem5 Developers if (size) 34610037SARM gem5 Developers return new Base<uint64_t>(machInst, dest, op1, op2); 34710037SARM gem5 Developers else 34810037SARM gem5 Developers return new Base<uint32_t>(machInst, dest, op1, op2); 34910037SARM gem5 Developers } 35010037SARM gem5 Developers 35110037SARM gem5 Developers template <template <typename T> class Base> 35210037SARM gem5 Developers StaticInstPtr 35310037SARM gem5 Developers decodeNeonUThreeImmScFpReg(bool size, ExtMachInst machInst, 35410037SARM gem5 Developers IntRegIndex dest, IntRegIndex op1, 35510037SARM gem5 Developers IntRegIndex op2, uint64_t imm) 35610037SARM gem5 Developers { 35710037SARM gem5 Developers if (size) 35810037SARM gem5 Developers return new Base<uint64_t>(machInst, dest, op1, op2, imm); 35910037SARM gem5 Developers else 36010037SARM gem5 Developers return new Base<uint32_t>(machInst, dest, op1, op2, imm); 36110037SARM gem5 Developers } 36210037SARM gem5 Developers 36310037SARM gem5 Developers template <template <typename T> class BaseD, 36410037SARM gem5 Developers template <typename T> class BaseQ> 36510037SARM gem5 Developers StaticInstPtr 36610037SARM gem5 Developers decodeNeonUThreeImmHAndWReg(bool q, unsigned size, ExtMachInst machInst, 36710037SARM gem5 Developers IntRegIndex dest, IntRegIndex op1, 36810037SARM gem5 Developers IntRegIndex op2, uint64_t imm) 36910037SARM gem5 Developers { 37010037SARM gem5 Developers if (q) { 37110037SARM gem5 Developers switch (size) { 37210037SARM gem5 Developers case 1: 37310037SARM gem5 Developers return new BaseQ<uint16_t>(machInst, dest, op1, op2, imm); 37410037SARM gem5 Developers case 2: 37510037SARM gem5 Developers return new BaseQ<uint32_t>(machInst, dest, op1, op2, imm); 37610037SARM gem5 Developers default: 37710037SARM gem5 Developers return new Unknown(machInst); 37810037SARM gem5 Developers } 37910037SARM gem5 Developers } else { 38010037SARM gem5 Developers switch (size) { 38110037SARM gem5 Developers case 1: 38210037SARM gem5 Developers return new BaseD<uint16_t>(machInst, dest, op1, op2, imm); 38310037SARM gem5 Developers case 2: 38410037SARM gem5 Developers return new BaseD<uint32_t>(machInst, dest, op1, op2, imm); 38510037SARM gem5 Developers default: 38610037SARM gem5 Developers return new Unknown(machInst); 38710037SARM gem5 Developers } 38810037SARM gem5 Developers } 38910037SARM gem5 Developers } 39010037SARM gem5 Developers 39110037SARM gem5 Developers template <template <typename T> class BaseD, 39210037SARM gem5 Developers template <typename T> class BaseQ> 39310037SARM gem5 Developers StaticInstPtr 39410037SARM gem5 Developers decodeNeonSThreeImmHAndWReg(bool q, unsigned size, ExtMachInst machInst, 39510037SARM gem5 Developers IntRegIndex dest, IntRegIndex op1, 39610037SARM gem5 Developers IntRegIndex op2, uint64_t imm) 39710037SARM gem5 Developers { 39810037SARM gem5 Developers if (q) { 39910037SARM gem5 Developers switch (size) { 40010037SARM gem5 Developers case 1: 40110037SARM gem5 Developers return new BaseQ<int16_t>(machInst, dest, op1, op2, imm); 40210037SARM gem5 Developers case 2: 40310037SARM gem5 Developers return new BaseQ<int32_t>(machInst, dest, op1, op2, imm); 40410037SARM gem5 Developers default: 40510037SARM gem5 Developers return new Unknown(machInst); 40610037SARM gem5 Developers } 40710037SARM gem5 Developers } else { 40810037SARM gem5 Developers switch (size) { 40910037SARM gem5 Developers case 1: 41010037SARM gem5 Developers return new BaseD<int16_t>(machInst, dest, op1, op2, imm); 41110037SARM gem5 Developers case 2: 41210037SARM gem5 Developers return new BaseD<int32_t>(machInst, dest, op1, op2, imm); 41310037SARM gem5 Developers default: 41410037SARM gem5 Developers return new Unknown(machInst); 41510037SARM gem5 Developers } 41610037SARM gem5 Developers } 41710037SARM gem5 Developers } 41810037SARM gem5 Developers 41910037SARM gem5 Developers template <template <typename T> class BaseD, 42010037SARM gem5 Developers template <typename T> class BaseQ> 42110037SARM gem5 Developers StaticInstPtr 42210037SARM gem5 Developers decodeNeonUThreeImmFpReg(bool q, unsigned size, ExtMachInst machInst, 42310037SARM gem5 Developers IntRegIndex dest, IntRegIndex op1, 42410037SARM gem5 Developers IntRegIndex op2, uint64_t imm) 42510037SARM gem5 Developers { 42610037SARM gem5 Developers if (q) { 42710037SARM gem5 Developers if (size) 42810037SARM gem5 Developers return new BaseQ<uint64_t>(machInst, dest, op1, op2, imm); 42910037SARM gem5 Developers else 43010037SARM gem5 Developers return new BaseQ<uint32_t>(machInst, dest, op1, op2, imm); 43110037SARM gem5 Developers } else { 43210037SARM gem5 Developers if (size) 43310037SARM gem5 Developers return new Unknown(machInst); 43410037SARM gem5 Developers else 43510037SARM gem5 Developers return new BaseD<uint32_t>(machInst, dest, op1, op2, imm); 43610037SARM gem5 Developers } 43710037SARM gem5 Developers } 43810037SARM gem5 Developers 43910037SARM gem5 Developers template <template <typename T> class BaseD, 44010037SARM gem5 Developers template <typename T> class BaseQ> 44110037SARM gem5 Developers StaticInstPtr 4427639Sgblack@eecs.umich.edu decodeNeonUTwoShiftReg(bool q, unsigned size, 4437639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 4447639Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm) 4457639Sgblack@eecs.umich.edu { 4467639Sgblack@eecs.umich.edu if (q) { 4477639Sgblack@eecs.umich.edu switch (size) { 4487639Sgblack@eecs.umich.edu case 0: 4497639Sgblack@eecs.umich.edu return new BaseQ<uint8_t>(machInst, dest, op1, imm); 4507639Sgblack@eecs.umich.edu case 1: 4517639Sgblack@eecs.umich.edu return new BaseQ<uint16_t>(machInst, dest, op1, imm); 4527639Sgblack@eecs.umich.edu case 2: 4537639Sgblack@eecs.umich.edu return new BaseQ<uint32_t>(machInst, dest, op1, imm); 4547639Sgblack@eecs.umich.edu case 3: 4557639Sgblack@eecs.umich.edu return new BaseQ<uint64_t>(machInst, dest, op1, imm); 4567639Sgblack@eecs.umich.edu default: 4577639Sgblack@eecs.umich.edu return new Unknown(machInst); 4587639Sgblack@eecs.umich.edu } 4597639Sgblack@eecs.umich.edu } else { 4607639Sgblack@eecs.umich.edu switch (size) { 4617639Sgblack@eecs.umich.edu case 0: 4627639Sgblack@eecs.umich.edu return new BaseD<uint8_t>(machInst, dest, op1, imm); 4637639Sgblack@eecs.umich.edu case 1: 4647639Sgblack@eecs.umich.edu return new BaseD<uint16_t>(machInst, dest, op1, imm); 4657639Sgblack@eecs.umich.edu case 2: 4667639Sgblack@eecs.umich.edu return new BaseD<uint32_t>(machInst, dest, op1, imm); 4677639Sgblack@eecs.umich.edu case 3: 4687639Sgblack@eecs.umich.edu return new BaseD<uint64_t>(machInst, dest, op1, imm); 4697639Sgblack@eecs.umich.edu default: 4707639Sgblack@eecs.umich.edu return new Unknown(machInst); 4717639Sgblack@eecs.umich.edu } 4727639Sgblack@eecs.umich.edu } 4737639Sgblack@eecs.umich.edu } 4747639Sgblack@eecs.umich.edu 4757639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 4767639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 4777639Sgblack@eecs.umich.edu StaticInstPtr 4787639Sgblack@eecs.umich.edu decodeNeonSTwoShiftReg(bool q, unsigned size, 4797639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 4807639Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm) 4817639Sgblack@eecs.umich.edu { 4827639Sgblack@eecs.umich.edu if (q) { 4837639Sgblack@eecs.umich.edu switch (size) { 4847639Sgblack@eecs.umich.edu case 0: 4857639Sgblack@eecs.umich.edu return new BaseQ<int8_t>(machInst, dest, op1, imm); 4867639Sgblack@eecs.umich.edu case 1: 4877639Sgblack@eecs.umich.edu return new BaseQ<int16_t>(machInst, dest, op1, imm); 4887639Sgblack@eecs.umich.edu case 2: 4897639Sgblack@eecs.umich.edu return new BaseQ<int32_t>(machInst, dest, op1, imm); 4907639Sgblack@eecs.umich.edu case 3: 4917639Sgblack@eecs.umich.edu return new BaseQ<int64_t>(machInst, dest, op1, imm); 4927639Sgblack@eecs.umich.edu default: 4937639Sgblack@eecs.umich.edu return new Unknown(machInst); 4947639Sgblack@eecs.umich.edu } 4957639Sgblack@eecs.umich.edu } else { 4967639Sgblack@eecs.umich.edu switch (size) { 4977639Sgblack@eecs.umich.edu case 0: 4987639Sgblack@eecs.umich.edu return new BaseD<int8_t>(machInst, dest, op1, imm); 4997639Sgblack@eecs.umich.edu case 1: 5007639Sgblack@eecs.umich.edu return new BaseD<int16_t>(machInst, dest, op1, imm); 5017639Sgblack@eecs.umich.edu case 2: 5027639Sgblack@eecs.umich.edu return new BaseD<int32_t>(machInst, dest, op1, imm); 5037639Sgblack@eecs.umich.edu case 3: 5047639Sgblack@eecs.umich.edu return new BaseD<int64_t>(machInst, dest, op1, imm); 5057639Sgblack@eecs.umich.edu default: 5067639Sgblack@eecs.umich.edu return new Unknown(machInst); 5077639Sgblack@eecs.umich.edu } 5087639Sgblack@eecs.umich.edu } 5097639Sgblack@eecs.umich.edu } 5107639Sgblack@eecs.umich.edu 5117639Sgblack@eecs.umich.edu 5127639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 5137639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 5147639Sgblack@eecs.umich.edu StaticInstPtr 5157639Sgblack@eecs.umich.edu decodeNeonUSTwoShiftReg(bool q, bool notSigned, unsigned size, 5167639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 5177639Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm) 5187639Sgblack@eecs.umich.edu { 5197639Sgblack@eecs.umich.edu if (notSigned) { 5207639Sgblack@eecs.umich.edu return decodeNeonUTwoShiftReg<BaseD, BaseQ>( 5217639Sgblack@eecs.umich.edu q, size, machInst, dest, op1, imm); 5227639Sgblack@eecs.umich.edu } else { 5237639Sgblack@eecs.umich.edu return decodeNeonSTwoShiftReg<BaseD, BaseQ>( 5247639Sgblack@eecs.umich.edu q, size, machInst, dest, op1, imm); 5257639Sgblack@eecs.umich.edu } 5267639Sgblack@eecs.umich.edu } 5277639Sgblack@eecs.umich.edu 5287639Sgblack@eecs.umich.edu template <template <typename T> class Base> 5297639Sgblack@eecs.umich.edu StaticInstPtr 5307639Sgblack@eecs.umich.edu decodeNeonUTwoShiftUSReg(unsigned size, 5317639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 5327639Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm) 5337639Sgblack@eecs.umich.edu { 5347639Sgblack@eecs.umich.edu switch (size) { 5357639Sgblack@eecs.umich.edu case 0: 5367639Sgblack@eecs.umich.edu return new Base<uint8_t>(machInst, dest, op1, imm); 5377639Sgblack@eecs.umich.edu case 1: 5387639Sgblack@eecs.umich.edu return new Base<uint16_t>(machInst, dest, op1, imm); 5397639Sgblack@eecs.umich.edu case 2: 5407639Sgblack@eecs.umich.edu return new Base<uint32_t>(machInst, dest, op1, imm); 5417639Sgblack@eecs.umich.edu default: 5427639Sgblack@eecs.umich.edu return new Unknown(machInst); 5437639Sgblack@eecs.umich.edu } 5447639Sgblack@eecs.umich.edu } 5457639Sgblack@eecs.umich.edu 54610037SARM gem5 Developers template <template <typename T> class Base> 54710037SARM gem5 Developers StaticInstPtr 54810037SARM gem5 Developers decodeNeonUTwoShiftUReg(unsigned size, 54910037SARM gem5 Developers ExtMachInst machInst, IntRegIndex dest, 55010037SARM gem5 Developers IntRegIndex op1, uint64_t imm) 55110037SARM gem5 Developers { 55210037SARM gem5 Developers switch (size) { 55310037SARM gem5 Developers case 0: 55410037SARM gem5 Developers return new Base<uint8_t>(machInst, dest, op1, imm); 55510037SARM gem5 Developers case 1: 55610037SARM gem5 Developers return new Base<uint16_t>(machInst, dest, op1, imm); 55710037SARM gem5 Developers case 2: 55810037SARM gem5 Developers return new Base<uint32_t>(machInst, dest, op1, imm); 55910037SARM gem5 Developers case 3: 56010037SARM gem5 Developers return new Base<uint64_t>(machInst, dest, op1, imm); 56110037SARM gem5 Developers default: 56210037SARM gem5 Developers return new Unknown(machInst); 56310037SARM gem5 Developers } 56410037SARM gem5 Developers } 56510037SARM gem5 Developers 56610037SARM gem5 Developers template <template <typename T> class Base> 56710037SARM gem5 Developers StaticInstPtr 56810037SARM gem5 Developers decodeNeonSTwoShiftUReg(unsigned size, 56910037SARM gem5 Developers ExtMachInst machInst, IntRegIndex dest, 57010037SARM gem5 Developers IntRegIndex op1, uint64_t imm) 57110037SARM gem5 Developers { 57210037SARM gem5 Developers switch (size) { 57310037SARM gem5 Developers case 0: 57410037SARM gem5 Developers return new Base<int8_t>(machInst, dest, op1, imm); 57510037SARM gem5 Developers case 1: 57610037SARM gem5 Developers return new Base<int16_t>(machInst, dest, op1, imm); 57710037SARM gem5 Developers case 2: 57810037SARM gem5 Developers return new Base<int32_t>(machInst, dest, op1, imm); 57910037SARM gem5 Developers case 3: 58010037SARM gem5 Developers return new Base<int64_t>(machInst, dest, op1, imm); 58110037SARM gem5 Developers default: 58210037SARM gem5 Developers return new Unknown(machInst); 58310037SARM gem5 Developers } 58410037SARM gem5 Developers } 58510037SARM gem5 Developers 5867639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 5877639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 5887639Sgblack@eecs.umich.edu StaticInstPtr 5897639Sgblack@eecs.umich.edu decodeNeonUTwoShiftSReg(bool q, unsigned size, 5907639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 5917639Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm) 5927639Sgblack@eecs.umich.edu { 5937639Sgblack@eecs.umich.edu if (q) { 5947639Sgblack@eecs.umich.edu return decodeNeonUTwoShiftUSReg<BaseQ>( 5957639Sgblack@eecs.umich.edu size, machInst, dest, op1, imm); 5967639Sgblack@eecs.umich.edu } else { 5977639Sgblack@eecs.umich.edu return decodeNeonUTwoShiftUSReg<BaseD>( 5987639Sgblack@eecs.umich.edu size, machInst, dest, op1, imm); 5997639Sgblack@eecs.umich.edu } 6007639Sgblack@eecs.umich.edu } 6017639Sgblack@eecs.umich.edu 6027639Sgblack@eecs.umich.edu template <template <typename T> class Base> 6037639Sgblack@eecs.umich.edu StaticInstPtr 6047639Sgblack@eecs.umich.edu decodeNeonSTwoShiftUSReg(unsigned size, 6057639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 6067639Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm) 6077639Sgblack@eecs.umich.edu { 6087639Sgblack@eecs.umich.edu switch (size) { 6097639Sgblack@eecs.umich.edu case 0: 6107639Sgblack@eecs.umich.edu return new Base<int8_t>(machInst, dest, op1, imm); 6117639Sgblack@eecs.umich.edu case 1: 6127639Sgblack@eecs.umich.edu return new Base<int16_t>(machInst, dest, op1, imm); 6137639Sgblack@eecs.umich.edu case 2: 6147639Sgblack@eecs.umich.edu return new Base<int32_t>(machInst, dest, op1, imm); 6157639Sgblack@eecs.umich.edu default: 6167639Sgblack@eecs.umich.edu return new Unknown(machInst); 6177639Sgblack@eecs.umich.edu } 6187639Sgblack@eecs.umich.edu } 6197639Sgblack@eecs.umich.edu 6207639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 6217639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 6227639Sgblack@eecs.umich.edu StaticInstPtr 6237639Sgblack@eecs.umich.edu decodeNeonSTwoShiftSReg(bool q, unsigned size, 6247639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 6257639Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm) 6267639Sgblack@eecs.umich.edu { 6277639Sgblack@eecs.umich.edu if (q) { 6287639Sgblack@eecs.umich.edu return decodeNeonSTwoShiftUSReg<BaseQ>( 6297639Sgblack@eecs.umich.edu size, machInst, dest, op1, imm); 6307639Sgblack@eecs.umich.edu } else { 6317639Sgblack@eecs.umich.edu return decodeNeonSTwoShiftUSReg<BaseD>( 6327639Sgblack@eecs.umich.edu size, machInst, dest, op1, imm); 6337639Sgblack@eecs.umich.edu } 6347639Sgblack@eecs.umich.edu } 6357639Sgblack@eecs.umich.edu 6367639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 6377639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 6387639Sgblack@eecs.umich.edu StaticInstPtr 6397639Sgblack@eecs.umich.edu decodeNeonUSTwoShiftSReg(bool q, bool notSigned, unsigned size, 6407639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 6417639Sgblack@eecs.umich.edu IntRegIndex op1, uint64_t imm) 6427639Sgblack@eecs.umich.edu { 6437639Sgblack@eecs.umich.edu if (notSigned) { 6447639Sgblack@eecs.umich.edu return decodeNeonUTwoShiftSReg<BaseD, BaseQ>( 6457639Sgblack@eecs.umich.edu q, size, machInst, dest, op1, imm); 6467639Sgblack@eecs.umich.edu } else { 6477639Sgblack@eecs.umich.edu return decodeNeonSTwoShiftSReg<BaseD, BaseQ>( 6487639Sgblack@eecs.umich.edu q, size, machInst, dest, op1, imm); 6497639Sgblack@eecs.umich.edu } 6507639Sgblack@eecs.umich.edu } 6517639Sgblack@eecs.umich.edu 65210037SARM gem5 Developers template <template <typename T> class BaseD, 65310037SARM gem5 Developers template <typename T> class BaseQ> 65410037SARM gem5 Developers StaticInstPtr 65510037SARM gem5 Developers decodeNeonUTwoShiftXReg(bool q, unsigned size, ExtMachInst machInst, 65610037SARM gem5 Developers IntRegIndex dest, IntRegIndex op1, uint64_t imm) 65710037SARM gem5 Developers { 65810037SARM gem5 Developers if (q) { 65910037SARM gem5 Developers return decodeNeonUTwoShiftUReg<BaseQ>( 66010037SARM gem5 Developers size, machInst, dest, op1, imm); 66110037SARM gem5 Developers } else { 66210037SARM gem5 Developers return decodeNeonUTwoShiftUSReg<BaseD>( 66310037SARM gem5 Developers size, machInst, dest, op1, imm); 66410037SARM gem5 Developers } 66510037SARM gem5 Developers } 66610037SARM gem5 Developers 66710037SARM gem5 Developers template <template <typename T> class BaseD, 66810037SARM gem5 Developers template <typename T> class BaseQ> 66910037SARM gem5 Developers StaticInstPtr 67010037SARM gem5 Developers decodeNeonSTwoShiftXReg(bool q, unsigned size, ExtMachInst machInst, 67110037SARM gem5 Developers IntRegIndex dest, IntRegIndex op1, uint64_t imm) 67210037SARM gem5 Developers { 67310037SARM gem5 Developers if (q) { 67410037SARM gem5 Developers return decodeNeonSTwoShiftUReg<BaseQ>( 67510037SARM gem5 Developers size, machInst, dest, op1, imm); 67610037SARM gem5 Developers } else { 67710037SARM gem5 Developers return decodeNeonSTwoShiftUSReg<BaseD>( 67810037SARM gem5 Developers size, machInst, dest, op1, imm); 67910037SARM gem5 Developers } 68010037SARM gem5 Developers } 68110037SARM gem5 Developers 68210037SARM gem5 Developers template <template <typename T> class Base> 68310037SARM gem5 Developers StaticInstPtr 68410037SARM gem5 Developers decodeNeonUTwoShiftUFpReg(unsigned size, ExtMachInst machInst, 68510037SARM gem5 Developers IntRegIndex dest, IntRegIndex op1, uint64_t imm) 68610037SARM gem5 Developers { 68710037SARM gem5 Developers if (size) 68810037SARM gem5 Developers return new Base<uint64_t>(machInst, dest, op1, imm); 68910037SARM gem5 Developers else 69010037SARM gem5 Developers return new Base<uint32_t>(machInst, dest, op1, imm); 69110037SARM gem5 Developers } 69210037SARM gem5 Developers 69310037SARM gem5 Developers template <template <typename T> class BaseD, 69410037SARM gem5 Developers template <typename T> class BaseQ> 69510037SARM gem5 Developers StaticInstPtr 69610037SARM gem5 Developers decodeNeonUTwoShiftFpReg(bool q, unsigned size, ExtMachInst machInst, 69710037SARM gem5 Developers IntRegIndex dest, IntRegIndex op1, uint64_t imm) 69810037SARM gem5 Developers { 69910037SARM gem5 Developers if (q) { 70010037SARM gem5 Developers if (size) 70110037SARM gem5 Developers return new BaseQ<uint64_t>(machInst, dest, op1, imm); 70210037SARM gem5 Developers else 70310037SARM gem5 Developers return new BaseQ<uint32_t>(machInst, dest, op1, imm); 70410037SARM gem5 Developers } else { 70510037SARM gem5 Developers if (size) 70610037SARM gem5 Developers return new Unknown(machInst); 70710037SARM gem5 Developers else 70810037SARM gem5 Developers return new BaseD<uint32_t>(machInst, dest, op1, imm); 70910037SARM gem5 Developers } 71010037SARM gem5 Developers } 71110037SARM gem5 Developers 7127639Sgblack@eecs.umich.edu template <template <typename T> class Base> 7137639Sgblack@eecs.umich.edu StaticInstPtr 7147639Sgblack@eecs.umich.edu decodeNeonUTwoMiscUSReg(unsigned size, 7157639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 7167639Sgblack@eecs.umich.edu IntRegIndex op1) 7177639Sgblack@eecs.umich.edu { 7187639Sgblack@eecs.umich.edu switch (size) { 7197639Sgblack@eecs.umich.edu case 0: 7207639Sgblack@eecs.umich.edu return new Base<uint8_t>(machInst, dest, op1); 7217639Sgblack@eecs.umich.edu case 1: 7227639Sgblack@eecs.umich.edu return new Base<uint16_t>(machInst, dest, op1); 7237639Sgblack@eecs.umich.edu case 2: 7247639Sgblack@eecs.umich.edu return new Base<uint32_t>(machInst, dest, op1); 7257639Sgblack@eecs.umich.edu default: 7267639Sgblack@eecs.umich.edu return new Unknown(machInst); 7277639Sgblack@eecs.umich.edu } 7287639Sgblack@eecs.umich.edu } 7297639Sgblack@eecs.umich.edu 7307639Sgblack@eecs.umich.edu template <template <typename T> class Base> 7317639Sgblack@eecs.umich.edu StaticInstPtr 7327639Sgblack@eecs.umich.edu decodeNeonSTwoMiscUSReg(unsigned size, 7337639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 7347639Sgblack@eecs.umich.edu IntRegIndex op1) 7357639Sgblack@eecs.umich.edu { 7367639Sgblack@eecs.umich.edu switch (size) { 7377639Sgblack@eecs.umich.edu case 0: 7387639Sgblack@eecs.umich.edu return new Base<int8_t>(machInst, dest, op1); 7397639Sgblack@eecs.umich.edu case 1: 7407639Sgblack@eecs.umich.edu return new Base<int16_t>(machInst, dest, op1); 7417639Sgblack@eecs.umich.edu case 2: 7427639Sgblack@eecs.umich.edu return new Base<int32_t>(machInst, dest, op1); 7437639Sgblack@eecs.umich.edu default: 7447639Sgblack@eecs.umich.edu return new Unknown(machInst); 7457639Sgblack@eecs.umich.edu } 7467639Sgblack@eecs.umich.edu } 7477639Sgblack@eecs.umich.edu 7487639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 7497639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 7507639Sgblack@eecs.umich.edu StaticInstPtr 7517639Sgblack@eecs.umich.edu decodeNeonUTwoMiscSReg(bool q, unsigned size, 75210037SARM gem5 Developers ExtMachInst machInst, IntRegIndex dest, 75310037SARM gem5 Developers IntRegIndex op1) 7547639Sgblack@eecs.umich.edu { 7557639Sgblack@eecs.umich.edu if (q) { 7567639Sgblack@eecs.umich.edu return decodeNeonUTwoMiscUSReg<BaseQ>(size, machInst, dest, op1); 7577639Sgblack@eecs.umich.edu } else { 7587639Sgblack@eecs.umich.edu return decodeNeonUTwoMiscUSReg<BaseD>(size, machInst, dest, op1); 7597639Sgblack@eecs.umich.edu } 7607639Sgblack@eecs.umich.edu } 7617639Sgblack@eecs.umich.edu 7627639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 7637639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 7647639Sgblack@eecs.umich.edu StaticInstPtr 7657639Sgblack@eecs.umich.edu decodeNeonSTwoMiscSReg(bool q, unsigned size, 76610037SARM gem5 Developers ExtMachInst machInst, IntRegIndex dest, 76710037SARM gem5 Developers IntRegIndex op1) 7687639Sgblack@eecs.umich.edu { 7697639Sgblack@eecs.umich.edu if (q) { 7707639Sgblack@eecs.umich.edu return decodeNeonSTwoMiscUSReg<BaseQ>(size, machInst, dest, op1); 7717639Sgblack@eecs.umich.edu } else { 7727639Sgblack@eecs.umich.edu return decodeNeonSTwoMiscUSReg<BaseD>(size, machInst, dest, op1); 7737639Sgblack@eecs.umich.edu } 7747639Sgblack@eecs.umich.edu } 7757639Sgblack@eecs.umich.edu 7767639Sgblack@eecs.umich.edu template <template <typename T> class Base> 7777639Sgblack@eecs.umich.edu StaticInstPtr 7787639Sgblack@eecs.umich.edu decodeNeonUTwoMiscUReg(unsigned size, 7797639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 7807639Sgblack@eecs.umich.edu IntRegIndex op1) 7817639Sgblack@eecs.umich.edu { 7827639Sgblack@eecs.umich.edu switch (size) { 7837639Sgblack@eecs.umich.edu case 0: 7847639Sgblack@eecs.umich.edu return new Base<uint8_t>(machInst, dest, op1); 7857639Sgblack@eecs.umich.edu case 1: 7867639Sgblack@eecs.umich.edu return new Base<uint16_t>(machInst, dest, op1); 7877639Sgblack@eecs.umich.edu case 2: 7887639Sgblack@eecs.umich.edu return new Base<uint32_t>(machInst, dest, op1); 7897639Sgblack@eecs.umich.edu case 3: 7907639Sgblack@eecs.umich.edu return new Base<uint64_t>(machInst, dest, op1); 7917639Sgblack@eecs.umich.edu default: 7927639Sgblack@eecs.umich.edu return new Unknown(machInst); 7937639Sgblack@eecs.umich.edu } 7947639Sgblack@eecs.umich.edu } 7957639Sgblack@eecs.umich.edu 7967639Sgblack@eecs.umich.edu template <template <typename T> class Base> 7977639Sgblack@eecs.umich.edu StaticInstPtr 7987639Sgblack@eecs.umich.edu decodeNeonSTwoMiscUReg(unsigned size, 79910037SARM gem5 Developers ExtMachInst machInst, IntRegIndex dest, 80010037SARM gem5 Developers IntRegIndex op1) 8017639Sgblack@eecs.umich.edu { 8027639Sgblack@eecs.umich.edu switch (size) { 8037639Sgblack@eecs.umich.edu case 0: 8047639Sgblack@eecs.umich.edu return new Base<int8_t>(machInst, dest, op1); 8057639Sgblack@eecs.umich.edu case 1: 8067639Sgblack@eecs.umich.edu return new Base<int16_t>(machInst, dest, op1); 8077639Sgblack@eecs.umich.edu case 2: 8087639Sgblack@eecs.umich.edu return new Base<int32_t>(machInst, dest, op1); 8097639Sgblack@eecs.umich.edu case 3: 8107639Sgblack@eecs.umich.edu return new Base<int64_t>(machInst, dest, op1); 8117639Sgblack@eecs.umich.edu default: 8127639Sgblack@eecs.umich.edu return new Unknown(machInst); 8137639Sgblack@eecs.umich.edu } 8147639Sgblack@eecs.umich.edu } 8157639Sgblack@eecs.umich.edu 8167639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 8177639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 8187639Sgblack@eecs.umich.edu StaticInstPtr 8197639Sgblack@eecs.umich.edu decodeNeonSTwoMiscReg(bool q, unsigned size, 8207639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 8217639Sgblack@eecs.umich.edu IntRegIndex op1) 8227639Sgblack@eecs.umich.edu { 8237639Sgblack@eecs.umich.edu if (q) { 8247639Sgblack@eecs.umich.edu return decodeNeonSTwoMiscUReg<BaseQ>(size, machInst, dest, op1); 8257639Sgblack@eecs.umich.edu } else { 8267639Sgblack@eecs.umich.edu return decodeNeonSTwoMiscUReg<BaseD>(size, machInst, dest, op1); 8277639Sgblack@eecs.umich.edu } 8287639Sgblack@eecs.umich.edu } 8297639Sgblack@eecs.umich.edu 8307639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 8317639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 8327639Sgblack@eecs.umich.edu StaticInstPtr 8337639Sgblack@eecs.umich.edu decodeNeonUTwoMiscReg(bool q, unsigned size, 8347639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 8357639Sgblack@eecs.umich.edu IntRegIndex op1) 8367639Sgblack@eecs.umich.edu { 8377639Sgblack@eecs.umich.edu if (q) { 8387639Sgblack@eecs.umich.edu return decodeNeonUTwoMiscUReg<BaseQ>(size, machInst, dest, op1); 8397639Sgblack@eecs.umich.edu } else { 8407639Sgblack@eecs.umich.edu return decodeNeonUTwoMiscUReg<BaseD>(size, machInst, dest, op1); 8417639Sgblack@eecs.umich.edu } 8427639Sgblack@eecs.umich.edu } 8437639Sgblack@eecs.umich.edu 8447639Sgblack@eecs.umich.edu template <template <typename T> class BaseD, 8457639Sgblack@eecs.umich.edu template <typename T> class BaseQ> 8467639Sgblack@eecs.umich.edu StaticInstPtr 8477639Sgblack@eecs.umich.edu decodeNeonUSTwoMiscSReg(bool q, bool notSigned, unsigned size, 8487639Sgblack@eecs.umich.edu ExtMachInst machInst, IntRegIndex dest, 8497639Sgblack@eecs.umich.edu IntRegIndex op1) 8507639Sgblack@eecs.umich.edu { 8517639Sgblack@eecs.umich.edu if (notSigned) { 8527639Sgblack@eecs.umich.edu return decodeNeonUTwoShiftSReg<BaseD, BaseQ>( 8537639Sgblack@eecs.umich.edu q, size, machInst, dest, op1); 8547639Sgblack@eecs.umich.edu } else { 8557639Sgblack@eecs.umich.edu return decodeNeonSTwoShiftSReg<BaseD, BaseQ>( 8567639Sgblack@eecs.umich.edu q, size, machInst, dest, op1); 8577639Sgblack@eecs.umich.edu } 8587639Sgblack@eecs.umich.edu } 8597639Sgblack@eecs.umich.edu 86010037SARM gem5 Developers template <template <typename T> class BaseD, 86110037SARM gem5 Developers template <typename T> class BaseQ> 86210037SARM gem5 Developers StaticInstPtr 86310037SARM gem5 Developers decodeNeonUTwoMiscXReg(bool q, unsigned size, ExtMachInst machInst, 86410037SARM gem5 Developers IntRegIndex dest, IntRegIndex op1) 86510037SARM gem5 Developers { 86610037SARM gem5 Developers if (q) { 86710037SARM gem5 Developers return decodeNeonUTwoMiscUReg<BaseQ>(size, machInst, dest, op1); 86810037SARM gem5 Developers } else { 86910037SARM gem5 Developers return decodeNeonUTwoMiscUSReg<BaseD>(size, machInst, dest, op1); 87010037SARM gem5 Developers } 87110037SARM gem5 Developers } 87210037SARM gem5 Developers 87310037SARM gem5 Developers template <template <typename T> class BaseD, 87410037SARM gem5 Developers template <typename T> class BaseQ> 87510037SARM gem5 Developers StaticInstPtr 87610037SARM gem5 Developers decodeNeonSTwoMiscXReg(bool q, unsigned size, ExtMachInst machInst, 87710037SARM gem5 Developers IntRegIndex dest, IntRegIndex op1) 87810037SARM gem5 Developers { 87910037SARM gem5 Developers if (q) { 88010037SARM gem5 Developers return decodeNeonSTwoMiscUReg<BaseQ>(size, machInst, dest, op1); 88110037SARM gem5 Developers } else { 88210037SARM gem5 Developers return decodeNeonSTwoMiscUSReg<BaseD>(size, machInst, dest, op1); 88310037SARM gem5 Developers } 88410037SARM gem5 Developers } 88510037SARM gem5 Developers 88610037SARM gem5 Developers template <template <typename T> class BaseD, 88710037SARM gem5 Developers template <typename T> class BaseQ> 88810037SARM gem5 Developers StaticInstPtr 88910037SARM gem5 Developers decodeNeonUTwoMiscFpReg(bool q, unsigned size, ExtMachInst machInst, 89010037SARM gem5 Developers IntRegIndex dest, IntRegIndex op1) 89110037SARM gem5 Developers { 89210037SARM gem5 Developers if (q) { 89310037SARM gem5 Developers if (size) 89410037SARM gem5 Developers return new BaseQ<uint64_t>(machInst, dest, op1); 89510037SARM gem5 Developers else 89610037SARM gem5 Developers return new BaseQ<uint32_t>(machInst, dest, op1); 89710037SARM gem5 Developers } else { 89810037SARM gem5 Developers if (size) 89910037SARM gem5 Developers return new Unknown(machInst); 90010037SARM gem5 Developers else 90110037SARM gem5 Developers return new BaseD<uint32_t>(machInst, dest, op1); 90210037SARM gem5 Developers } 90310037SARM gem5 Developers } 90410037SARM gem5 Developers 90510037SARM gem5 Developers template <template <typename T> class BaseD, 90610037SARM gem5 Developers template <typename T> class BaseQ> 90710037SARM gem5 Developers StaticInstPtr 90810037SARM gem5 Developers decodeNeonUTwoMiscPwiseScFpReg(unsigned size, ExtMachInst machInst, 90910037SARM gem5 Developers IntRegIndex dest, IntRegIndex op1) 91010037SARM gem5 Developers { 91110037SARM gem5 Developers if (size) 91210037SARM gem5 Developers return new BaseQ<uint64_t>(machInst, dest, op1); 91310037SARM gem5 Developers else 91410037SARM gem5 Developers return new BaseD<uint32_t>(machInst, dest, op1); 91510037SARM gem5 Developers } 91610037SARM gem5 Developers 91710037SARM gem5 Developers template <template <typename T> class Base> 91810037SARM gem5 Developers StaticInstPtr 91910037SARM gem5 Developers decodeNeonUTwoMiscScFpReg(unsigned size, ExtMachInst machInst, 92010037SARM gem5 Developers IntRegIndex dest, IntRegIndex op1) 92110037SARM gem5 Developers { 92210037SARM gem5 Developers if (size) 92310037SARM gem5 Developers return new Base<uint64_t>(machInst, dest, op1); 92410037SARM gem5 Developers else 92510037SARM gem5 Developers return new Base<uint32_t>(machInst, dest, op1); 92610037SARM gem5 Developers } 92710037SARM gem5 Developers 92810037SARM gem5 Developers template <template <typename T> class BaseD, 92910037SARM gem5 Developers template <typename T> class BaseQ> 93010037SARM gem5 Developers StaticInstPtr 93110037SARM gem5 Developers decodeNeonUAcrossLanesReg(bool q, unsigned size, ExtMachInst machInst, 93210037SARM gem5 Developers IntRegIndex dest, IntRegIndex op1) 93310037SARM gem5 Developers { 93410037SARM gem5 Developers if (q) { 93510037SARM gem5 Developers switch (size) { 93610037SARM gem5 Developers case 0x0: 93710037SARM gem5 Developers return new BaseQ<uint8_t>(machInst, dest, op1); 93810037SARM gem5 Developers case 0x1: 93910037SARM gem5 Developers return new BaseQ<uint16_t>(machInst, dest, op1); 94010037SARM gem5 Developers case 0x2: 94110037SARM gem5 Developers return new BaseQ<uint32_t>(machInst, dest, op1); 94210037SARM gem5 Developers default: 94310037SARM gem5 Developers return new Unknown(machInst); 94410037SARM gem5 Developers } 94510037SARM gem5 Developers } else { 94610037SARM gem5 Developers switch (size) { 94710037SARM gem5 Developers case 0x0: 94810037SARM gem5 Developers return new BaseD<uint8_t>(machInst, dest, op1); 94910037SARM gem5 Developers case 0x1: 95010037SARM gem5 Developers return new BaseD<uint16_t>(machInst, dest, op1); 95110037SARM gem5 Developers default: 95210037SARM gem5 Developers return new Unknown(machInst); 95310037SARM gem5 Developers } 95410037SARM gem5 Developers } 95510037SARM gem5 Developers } 95610037SARM gem5 Developers 95710037SARM gem5 Developers template <template <typename T> class BaseD, 95810037SARM gem5 Developers template <typename T> class BaseQ, 95910037SARM gem5 Developers template <typename T> class BaseBQ> 96010037SARM gem5 Developers StaticInstPtr 96110037SARM gem5 Developers decodeNeonUAcrossLanesReg(bool q, unsigned size, ExtMachInst machInst, 96210037SARM gem5 Developers IntRegIndex dest, IntRegIndex op1) 96310037SARM gem5 Developers { 96410037SARM gem5 Developers if (q) { 96510037SARM gem5 Developers switch (size) { 96610037SARM gem5 Developers case 0x0: 96710037SARM gem5 Developers return new BaseQ<uint8_t>(machInst, dest, op1); 96810037SARM gem5 Developers case 0x1: 96910037SARM gem5 Developers return new BaseQ<uint16_t>(machInst, dest, op1); 97010037SARM gem5 Developers case 0x2: 97110037SARM gem5 Developers return new BaseBQ<uint32_t>(machInst, dest, op1); 97210037SARM gem5 Developers default: 97310037SARM gem5 Developers return new Unknown(machInst); 97410037SARM gem5 Developers } 97510037SARM gem5 Developers } else { 97610037SARM gem5 Developers switch (size) { 97710037SARM gem5 Developers case 0x0: 97810037SARM gem5 Developers return new BaseD<uint8_t>(machInst, dest, op1); 97910037SARM gem5 Developers case 0x1: 98010037SARM gem5 Developers return new BaseD<uint16_t>(machInst, dest, op1); 98110037SARM gem5 Developers default: 98210037SARM gem5 Developers return new Unknown(machInst); 98310037SARM gem5 Developers } 98410037SARM gem5 Developers } 98510037SARM gem5 Developers } 98610037SARM gem5 Developers 98710037SARM gem5 Developers template <template <typename T> class BaseD, 98810037SARM gem5 Developers template <typename T> class BaseQ> 98910037SARM gem5 Developers StaticInstPtr 99010037SARM gem5 Developers decodeNeonSAcrossLanesReg(bool q, unsigned size, ExtMachInst machInst, 99110037SARM gem5 Developers IntRegIndex dest, IntRegIndex op1) 99210037SARM gem5 Developers { 99310037SARM gem5 Developers if (q) { 99410037SARM gem5 Developers switch (size) { 99510037SARM gem5 Developers case 0x0: 99610037SARM gem5 Developers return new BaseQ<int8_t>(machInst, dest, op1); 99710037SARM gem5 Developers case 0x1: 99810037SARM gem5 Developers return new BaseQ<int16_t>(machInst, dest, op1); 99910037SARM gem5 Developers case 0x2: 100010037SARM gem5 Developers return new BaseQ<int32_t>(machInst, dest, op1); 100110037SARM gem5 Developers default: 100210037SARM gem5 Developers return new Unknown(machInst); 100310037SARM gem5 Developers } 100410037SARM gem5 Developers } else { 100510037SARM gem5 Developers switch (size) { 100610037SARM gem5 Developers case 0x0: 100710037SARM gem5 Developers return new BaseD<int8_t>(machInst, dest, op1); 100810037SARM gem5 Developers case 0x1: 100910037SARM gem5 Developers return new BaseD<int16_t>(machInst, dest, op1); 101010037SARM gem5 Developers default: 101110037SARM gem5 Developers return new Unknown(machInst); 101210037SARM gem5 Developers } 101310037SARM gem5 Developers } 101410037SARM gem5 Developers } 101510037SARM gem5 Developers 101610037SARM gem5 Developers template <template <typename T> class BaseD, 101710037SARM gem5 Developers template <typename T> class BaseQ, 101810037SARM gem5 Developers template <typename T> class BaseBQ> 101910037SARM gem5 Developers StaticInstPtr 102010037SARM gem5 Developers decodeNeonUAcrossLanesLongReg(bool q, unsigned size, ExtMachInst machInst, 102110037SARM gem5 Developers IntRegIndex dest, IntRegIndex op1) 102210037SARM gem5 Developers { 102310037SARM gem5 Developers if (q) { 102410037SARM gem5 Developers switch (size) { 102510037SARM gem5 Developers case 0x0: 102610037SARM gem5 Developers return new BaseQ<uint8_t>(machInst, dest, op1); 102710037SARM gem5 Developers case 0x1: 102810037SARM gem5 Developers return new BaseQ<uint16_t>(machInst, dest, op1); 102910037SARM gem5 Developers case 0x2: 103010037SARM gem5 Developers return new BaseBQ<uint32_t>(machInst, dest, op1); 103110037SARM gem5 Developers default: 103210037SARM gem5 Developers return new Unknown(machInst); 103310037SARM gem5 Developers } 103410037SARM gem5 Developers } else { 103510037SARM gem5 Developers switch (size) { 103610037SARM gem5 Developers case 0x0: 103710037SARM gem5 Developers return new BaseD<uint8_t>(machInst, dest, op1); 103810037SARM gem5 Developers case 0x1: 103910037SARM gem5 Developers return new BaseD<uint16_t>(machInst, dest, op1); 104010037SARM gem5 Developers default: 104110037SARM gem5 Developers return new Unknown(machInst); 104210037SARM gem5 Developers } 104310037SARM gem5 Developers } 104410037SARM gem5 Developers } 104510037SARM gem5 Developers 104610037SARM gem5 Developers template <template <typename T> class BaseD, 104710037SARM gem5 Developers template <typename T> class BaseQ, 104810037SARM gem5 Developers template <typename T> class BaseBQ> 104910037SARM gem5 Developers StaticInstPtr 105010037SARM gem5 Developers decodeNeonSAcrossLanesLongReg(bool q, unsigned size, ExtMachInst machInst, 105110037SARM gem5 Developers IntRegIndex dest, IntRegIndex op1) 105210037SARM gem5 Developers { 105310037SARM gem5 Developers if (q) { 105410037SARM gem5 Developers switch (size) { 105510037SARM gem5 Developers case 0x0: 105610037SARM gem5 Developers return new BaseQ<int8_t>(machInst, dest, op1); 105710037SARM gem5 Developers case 0x1: 105810037SARM gem5 Developers return new BaseQ<int16_t>(machInst, dest, op1); 105910037SARM gem5 Developers case 0x2: 106010037SARM gem5 Developers return new BaseBQ<int32_t>(machInst, dest, op1); 106110037SARM gem5 Developers default: 106210037SARM gem5 Developers return new Unknown(machInst); 106310037SARM gem5 Developers } 106410037SARM gem5 Developers } else { 106510037SARM gem5 Developers switch (size) { 106610037SARM gem5 Developers case 0x0: 106710037SARM gem5 Developers return new BaseD<int8_t>(machInst, dest, op1); 106810037SARM gem5 Developers case 0x1: 106910037SARM gem5 Developers return new BaseD<int16_t>(machInst, dest, op1); 107010037SARM gem5 Developers default: 107110037SARM gem5 Developers return new Unknown(machInst); 107210037SARM gem5 Developers } 107310037SARM gem5 Developers } 107410037SARM gem5 Developers } 10757639Sgblack@eecs.umich.edu}}; 10767639Sgblack@eecs.umich.edu 107710197SCurtis.Dunham@arm.comlet {{ 107810197SCurtis.Dunham@arm.com header_output = "" 107910197SCurtis.Dunham@arm.com exec_output = "" 108010197SCurtis.Dunham@arm.com 108110197SCurtis.Dunham@arm.com vcompares = ''' 10827639Sgblack@eecs.umich.edu static float 10837639Sgblack@eecs.umich.edu vcgtFunc(float op1, float op2) 10847639Sgblack@eecs.umich.edu { 10859517SAli.Saidi@ARM.com if (std::isnan(op1) || std::isnan(op2)) 10867639Sgblack@eecs.umich.edu return 2.0; 10877639Sgblack@eecs.umich.edu return (op1 > op2) ? 0.0 : 1.0; 10887639Sgblack@eecs.umich.edu } 10897639Sgblack@eecs.umich.edu 10907639Sgblack@eecs.umich.edu static float 10917639Sgblack@eecs.umich.edu vcgeFunc(float op1, float op2) 10927639Sgblack@eecs.umich.edu { 10939517SAli.Saidi@ARM.com if (std::isnan(op1) || std::isnan(op2)) 10947639Sgblack@eecs.umich.edu return 2.0; 10957639Sgblack@eecs.umich.edu return (op1 >= op2) ? 0.0 : 1.0; 10967639Sgblack@eecs.umich.edu } 10977639Sgblack@eecs.umich.edu 10987639Sgblack@eecs.umich.edu static float 10997639Sgblack@eecs.umich.edu vceqFunc(float op1, float op2) 11007639Sgblack@eecs.umich.edu { 11017639Sgblack@eecs.umich.edu if (isSnan(op1) || isSnan(op2)) 11027639Sgblack@eecs.umich.edu return 2.0; 11037639Sgblack@eecs.umich.edu return (op1 == op2) ? 0.0 : 1.0; 11047639Sgblack@eecs.umich.edu } 110510197SCurtis.Dunham@arm.com''' 110610197SCurtis.Dunham@arm.com vcomparesL = ''' 11077639Sgblack@eecs.umich.edu static float 11087639Sgblack@eecs.umich.edu vcleFunc(float op1, float op2) 11097639Sgblack@eecs.umich.edu { 11109517SAli.Saidi@ARM.com if (std::isnan(op1) || std::isnan(op2)) 11117639Sgblack@eecs.umich.edu return 2.0; 11127639Sgblack@eecs.umich.edu return (op1 <= op2) ? 0.0 : 1.0; 11137639Sgblack@eecs.umich.edu } 11147639Sgblack@eecs.umich.edu 11157639Sgblack@eecs.umich.edu static float 11167639Sgblack@eecs.umich.edu vcltFunc(float op1, float op2) 11177639Sgblack@eecs.umich.edu { 11189517SAli.Saidi@ARM.com if (std::isnan(op1) || std::isnan(op2)) 11197639Sgblack@eecs.umich.edu return 2.0; 11207639Sgblack@eecs.umich.edu return (op1 < op2) ? 0.0 : 1.0; 11217639Sgblack@eecs.umich.edu } 112210197SCurtis.Dunham@arm.com''' 112310197SCurtis.Dunham@arm.com vacomparesG = ''' 11247639Sgblack@eecs.umich.edu static float 11257639Sgblack@eecs.umich.edu vacgtFunc(float op1, float op2) 11267639Sgblack@eecs.umich.edu { 11279517SAli.Saidi@ARM.com if (std::isnan(op1) || std::isnan(op2)) 11287639Sgblack@eecs.umich.edu return 2.0; 11297639Sgblack@eecs.umich.edu return (fabsf(op1) > fabsf(op2)) ? 0.0 : 1.0; 11307639Sgblack@eecs.umich.edu } 11317639Sgblack@eecs.umich.edu 11327639Sgblack@eecs.umich.edu static float 11337639Sgblack@eecs.umich.edu vacgeFunc(float op1, float op2) 11347639Sgblack@eecs.umich.edu { 11359517SAli.Saidi@ARM.com if (std::isnan(op1) || std::isnan(op2)) 11367639Sgblack@eecs.umich.edu return 2.0; 11377639Sgblack@eecs.umich.edu return (fabsf(op1) >= fabsf(op2)) ? 0.0 : 1.0; 11387639Sgblack@eecs.umich.edu } 113910197SCurtis.Dunham@arm.com''' 11407639Sgblack@eecs.umich.edu 114110197SCurtis.Dunham@arm.com exec_output += vcompares + vacomparesG 11427639Sgblack@eecs.umich.edu 11437639Sgblack@eecs.umich.edu smallUnsignedTypes = ("uint8_t", "uint16_t", "uint32_t") 11447639Sgblack@eecs.umich.edu unsignedTypes = smallUnsignedTypes + ("uint64_t",) 11457639Sgblack@eecs.umich.edu smallSignedTypes = ("int8_t", "int16_t", "int32_t") 11467639Sgblack@eecs.umich.edu signedTypes = smallSignedTypes + ("int64_t",) 11477639Sgblack@eecs.umich.edu smallTypes = smallUnsignedTypes + smallSignedTypes 11487639Sgblack@eecs.umich.edu allTypes = unsignedTypes + signedTypes 11497639Sgblack@eecs.umich.edu 11507760SGiacomo.Gabrielli@arm.com def threeEqualRegInst(name, Name, opClass, types, rCount, op, 115113978Sciro.santilli@arm.com readDest=False, pairwise=False, 115213978Sciro.santilli@arm.com standardFpcsr=False): 11537639Sgblack@eecs.umich.edu global header_output, exec_output 11547640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 11557639Sgblack@eecs.umich.edu RegVect srcReg1, srcReg2, destReg; 11567639Sgblack@eecs.umich.edu ''' 11577639Sgblack@eecs.umich.edu for reg in range(rCount): 11587639Sgblack@eecs.umich.edu eWalkCode += ''' 11598588Sgblack@eecs.umich.edu srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 11608588Sgblack@eecs.umich.edu srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw); 11617639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 11627639Sgblack@eecs.umich.edu if readDest: 11637639Sgblack@eecs.umich.edu eWalkCode += ''' 11648588Sgblack@eecs.umich.edu destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 11657639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 11667639Sgblack@eecs.umich.edu readDestCode = '' 116713978Sciro.santilli@arm.com if standardFpcsr: 116813978Sciro.santilli@arm.com eWalkCode += ''' 116913978Sciro.santilli@arm.com FPSCR fpscr = fpStandardFPSCRValue((FPSCR)FpscrExc); 117013978Sciro.santilli@arm.com ''' 11717639Sgblack@eecs.umich.edu if readDest: 11727639Sgblack@eecs.umich.edu readDestCode = 'destElem = gtoh(destReg.elements[i]);' 11737639Sgblack@eecs.umich.edu if pairwise: 11747639Sgblack@eecs.umich.edu eWalkCode += ''' 11757639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 11767639Sgblack@eecs.umich.edu Element srcElem1 = gtoh(2 * i < eCount ? 11777639Sgblack@eecs.umich.edu srcReg1.elements[2 * i] : 11787639Sgblack@eecs.umich.edu srcReg2.elements[2 * i - eCount]); 11797639Sgblack@eecs.umich.edu Element srcElem2 = gtoh(2 * i < eCount ? 11807639Sgblack@eecs.umich.edu srcReg1.elements[2 * i + 1] : 11817639Sgblack@eecs.umich.edu srcReg2.elements[2 * i + 1 - eCount]); 11827639Sgblack@eecs.umich.edu Element destElem; 11837639Sgblack@eecs.umich.edu %(readDest)s 11847639Sgblack@eecs.umich.edu %(op)s 11857639Sgblack@eecs.umich.edu destReg.elements[i] = htog(destElem); 11867639Sgblack@eecs.umich.edu } 11877639Sgblack@eecs.umich.edu ''' % { "op" : op, "readDest" : readDestCode } 11887639Sgblack@eecs.umich.edu else: 11897639Sgblack@eecs.umich.edu eWalkCode += ''' 11907639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 11917639Sgblack@eecs.umich.edu Element srcElem1 = gtoh(srcReg1.elements[i]); 11927639Sgblack@eecs.umich.edu Element srcElem2 = gtoh(srcReg2.elements[i]); 11937639Sgblack@eecs.umich.edu Element destElem; 11947639Sgblack@eecs.umich.edu %(readDest)s 11957639Sgblack@eecs.umich.edu %(op)s 11967639Sgblack@eecs.umich.edu destReg.elements[i] = htog(destElem); 11977639Sgblack@eecs.umich.edu } 11987639Sgblack@eecs.umich.edu ''' % { "op" : op, "readDest" : readDestCode } 119913978Sciro.santilli@arm.com if standardFpcsr: 120013978Sciro.santilli@arm.com eWalkCode += ''' 120113978Sciro.santilli@arm.com FpscrExc = fpscr; 120213978Sciro.santilli@arm.com ''' 12037639Sgblack@eecs.umich.edu for reg in range(rCount): 12047639Sgblack@eecs.umich.edu eWalkCode += ''' 12058588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 12067639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 12077639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 12087639Sgblack@eecs.umich.edu "RegRegRegOp", 12097639Sgblack@eecs.umich.edu { "code": eWalkCode, 12107639Sgblack@eecs.umich.edu "r_count": rCount, 12117760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12127760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 12137639Sgblack@eecs.umich.edu header_output += NeonRegRegRegOpDeclare.subst(iop) 12147639Sgblack@eecs.umich.edu exec_output += NeonEqualRegExecute.subst(iop) 12157639Sgblack@eecs.umich.edu for type in types: 12167639Sgblack@eecs.umich.edu substDict = { "targs" : type, 12177639Sgblack@eecs.umich.edu "class_name" : Name } 12187639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 12197639Sgblack@eecs.umich.edu 12207760SGiacomo.Gabrielli@arm.com def threeEqualRegInstFp(name, Name, opClass, types, rCount, op, 12217639Sgblack@eecs.umich.edu readDest=False, pairwise=False, toInt=False): 12227639Sgblack@eecs.umich.edu global header_output, exec_output 12237640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 122413544Sgabeblack@google.com typedef float FloatVect[rCount]; 12257639Sgblack@eecs.umich.edu FloatVect srcRegs1, srcRegs2; 12267639Sgblack@eecs.umich.edu ''' 12277639Sgblack@eecs.umich.edu if toInt: 12287639Sgblack@eecs.umich.edu eWalkCode += 'RegVect destRegs;\n' 12297639Sgblack@eecs.umich.edu else: 12307639Sgblack@eecs.umich.edu eWalkCode += 'FloatVect destRegs;\n' 12317639Sgblack@eecs.umich.edu for reg in range(rCount): 12327639Sgblack@eecs.umich.edu eWalkCode += ''' 12337639Sgblack@eecs.umich.edu srcRegs1[%(reg)d] = FpOp1P%(reg)d; 12347639Sgblack@eecs.umich.edu srcRegs2[%(reg)d] = FpOp2P%(reg)d; 12357639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 12367639Sgblack@eecs.umich.edu if readDest: 12377639Sgblack@eecs.umich.edu if toInt: 12387639Sgblack@eecs.umich.edu eWalkCode += ''' 12397639Sgblack@eecs.umich.edu destRegs.regs[%(reg)d] = FpDestP%(reg)d.bits; 12407639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 12417639Sgblack@eecs.umich.edu else: 12427639Sgblack@eecs.umich.edu eWalkCode += ''' 12437639Sgblack@eecs.umich.edu destRegs[%(reg)d] = FpDestP%(reg)d; 12447639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 12457639Sgblack@eecs.umich.edu readDestCode = '' 12467639Sgblack@eecs.umich.edu if readDest: 12477639Sgblack@eecs.umich.edu readDestCode = 'destReg = destRegs[r];' 124813544Sgabeblack@google.com destType = 'float' 12497639Sgblack@eecs.umich.edu writeDest = 'destRegs[r] = destReg;' 12507639Sgblack@eecs.umich.edu if toInt: 125113544Sgabeblack@google.com destType = 'uint32_t' 12527639Sgblack@eecs.umich.edu writeDest = 'destRegs.regs[r] = destReg;' 12537639Sgblack@eecs.umich.edu if pairwise: 12547639Sgblack@eecs.umich.edu eWalkCode += ''' 12557639Sgblack@eecs.umich.edu for (unsigned r = 0; r < rCount; r++) { 125613544Sgabeblack@google.com float srcReg1 = (2 * r < rCount) ? 12577639Sgblack@eecs.umich.edu srcRegs1[2 * r] : srcRegs2[2 * r - rCount]; 125813544Sgabeblack@google.com float srcReg2 = (2 * r < rCount) ? 12597639Sgblack@eecs.umich.edu srcRegs1[2 * r + 1] : srcRegs2[2 * r + 1 - rCount]; 12607639Sgblack@eecs.umich.edu %(destType)s destReg; 12617639Sgblack@eecs.umich.edu %(readDest)s 12627639Sgblack@eecs.umich.edu %(op)s 12637639Sgblack@eecs.umich.edu %(writeDest)s 12647639Sgblack@eecs.umich.edu } 12657639Sgblack@eecs.umich.edu ''' % { "op" : op, 12667639Sgblack@eecs.umich.edu "readDest" : readDestCode, 12677639Sgblack@eecs.umich.edu "destType" : destType, 12687639Sgblack@eecs.umich.edu "writeDest" : writeDest } 12697639Sgblack@eecs.umich.edu else: 12707639Sgblack@eecs.umich.edu eWalkCode += ''' 12717639Sgblack@eecs.umich.edu for (unsigned r = 0; r < rCount; r++) { 127213544Sgabeblack@google.com float srcReg1 = srcRegs1[r]; 127313544Sgabeblack@google.com float srcReg2 = srcRegs2[r]; 12747639Sgblack@eecs.umich.edu %(destType)s destReg; 12757639Sgblack@eecs.umich.edu %(readDest)s 12767639Sgblack@eecs.umich.edu %(op)s 12777639Sgblack@eecs.umich.edu %(writeDest)s 12787639Sgblack@eecs.umich.edu } 12797639Sgblack@eecs.umich.edu ''' % { "op" : op, 12807639Sgblack@eecs.umich.edu "readDest" : readDestCode, 12817639Sgblack@eecs.umich.edu "destType" : destType, 12827639Sgblack@eecs.umich.edu "writeDest" : writeDest } 12837639Sgblack@eecs.umich.edu for reg in range(rCount): 12847639Sgblack@eecs.umich.edu if toInt: 12857639Sgblack@eecs.umich.edu eWalkCode += ''' 12868588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = destRegs.regs[%(reg)d]; 12877639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 12887639Sgblack@eecs.umich.edu else: 12897639Sgblack@eecs.umich.edu eWalkCode += ''' 12907639Sgblack@eecs.umich.edu FpDestP%(reg)d = destRegs[%(reg)d]; 12917639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 12927639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 12937639Sgblack@eecs.umich.edu "FpRegRegRegOp", 12947639Sgblack@eecs.umich.edu { "code": eWalkCode, 12957639Sgblack@eecs.umich.edu "r_count": rCount, 12967760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 12977760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 12987639Sgblack@eecs.umich.edu header_output += NeonRegRegRegOpDeclare.subst(iop) 12997639Sgblack@eecs.umich.edu exec_output += NeonEqualRegExecute.subst(iop) 13007639Sgblack@eecs.umich.edu for type in types: 13017639Sgblack@eecs.umich.edu substDict = { "targs" : type, 13027639Sgblack@eecs.umich.edu "class_name" : Name } 13037639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 13047639Sgblack@eecs.umich.edu 13057760SGiacomo.Gabrielli@arm.com def threeUnequalRegInst(name, Name, opClass, types, op, 13067639Sgblack@eecs.umich.edu bigSrc1, bigSrc2, bigDest, readDest): 13077639Sgblack@eecs.umich.edu global header_output, exec_output 13087639Sgblack@eecs.umich.edu src1Cnt = src2Cnt = destCnt = 2 13097639Sgblack@eecs.umich.edu src1Prefix = src2Prefix = destPrefix = '' 13107639Sgblack@eecs.umich.edu if bigSrc1: 13117639Sgblack@eecs.umich.edu src1Cnt = 4 13127639Sgblack@eecs.umich.edu src1Prefix = 'Big' 13137639Sgblack@eecs.umich.edu if bigSrc2: 13147639Sgblack@eecs.umich.edu src2Cnt = 4 13157639Sgblack@eecs.umich.edu src2Prefix = 'Big' 13167639Sgblack@eecs.umich.edu if bigDest: 13177639Sgblack@eecs.umich.edu destCnt = 4 13187639Sgblack@eecs.umich.edu destPrefix = 'Big' 13197640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 13207639Sgblack@eecs.umich.edu %sRegVect srcReg1; 13217639Sgblack@eecs.umich.edu %sRegVect srcReg2; 13227639Sgblack@eecs.umich.edu %sRegVect destReg; 13237639Sgblack@eecs.umich.edu ''' % (src1Prefix, src2Prefix, destPrefix) 13247639Sgblack@eecs.umich.edu for reg in range(src1Cnt): 13257639Sgblack@eecs.umich.edu eWalkCode += ''' 13268588Sgblack@eecs.umich.edu srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 13277639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 13287639Sgblack@eecs.umich.edu for reg in range(src2Cnt): 13297639Sgblack@eecs.umich.edu eWalkCode += ''' 13308588Sgblack@eecs.umich.edu srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw); 13317639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 13327639Sgblack@eecs.umich.edu if readDest: 13337639Sgblack@eecs.umich.edu for reg in range(destCnt): 13347639Sgblack@eecs.umich.edu eWalkCode += ''' 13358588Sgblack@eecs.umich.edu destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 13367639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 13377639Sgblack@eecs.umich.edu readDestCode = '' 13387639Sgblack@eecs.umich.edu if readDest: 13397639Sgblack@eecs.umich.edu readDestCode = 'destElem = gtoh(destReg.elements[i]);' 13407639Sgblack@eecs.umich.edu eWalkCode += ''' 13417639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 13427639Sgblack@eecs.umich.edu %(src1Prefix)sElement srcElem1 = gtoh(srcReg1.elements[i]); 13437639Sgblack@eecs.umich.edu %(src1Prefix)sElement srcElem2 = gtoh(srcReg2.elements[i]); 13447639Sgblack@eecs.umich.edu %(destPrefix)sElement destElem; 13457639Sgblack@eecs.umich.edu %(readDest)s 13467639Sgblack@eecs.umich.edu %(op)s 13477639Sgblack@eecs.umich.edu destReg.elements[i] = htog(destElem); 13487639Sgblack@eecs.umich.edu } 13497639Sgblack@eecs.umich.edu ''' % { "op" : op, "readDest" : readDestCode, 13507639Sgblack@eecs.umich.edu "src1Prefix" : src1Prefix, "src2Prefix" : src2Prefix, 13517639Sgblack@eecs.umich.edu "destPrefix" : destPrefix } 13527639Sgblack@eecs.umich.edu for reg in range(destCnt): 13537639Sgblack@eecs.umich.edu eWalkCode += ''' 13548588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 13557639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 13567639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 13577639Sgblack@eecs.umich.edu "RegRegRegOp", 13587639Sgblack@eecs.umich.edu { "code": eWalkCode, 13597639Sgblack@eecs.umich.edu "r_count": 2, 13607760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 13617760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 13627639Sgblack@eecs.umich.edu header_output += NeonRegRegRegOpDeclare.subst(iop) 13637639Sgblack@eecs.umich.edu exec_output += NeonUnequalRegExecute.subst(iop) 13647639Sgblack@eecs.umich.edu for type in types: 13657639Sgblack@eecs.umich.edu substDict = { "targs" : type, 13667639Sgblack@eecs.umich.edu "class_name" : Name } 13677639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 13687639Sgblack@eecs.umich.edu 13697760SGiacomo.Gabrielli@arm.com def threeRegNarrowInst(name, Name, opClass, types, op, readDest=False): 13707760SGiacomo.Gabrielli@arm.com threeUnequalRegInst(name, Name, opClass, types, op, 13717639Sgblack@eecs.umich.edu True, True, False, readDest) 13727639Sgblack@eecs.umich.edu 13737760SGiacomo.Gabrielli@arm.com def threeRegLongInst(name, Name, opClass, types, op, readDest=False): 13747760SGiacomo.Gabrielli@arm.com threeUnequalRegInst(name, Name, opClass, types, op, 13757639Sgblack@eecs.umich.edu False, False, True, readDest) 13767639Sgblack@eecs.umich.edu 13777760SGiacomo.Gabrielli@arm.com def threeRegWideInst(name, Name, opClass, types, op, readDest=False): 13787760SGiacomo.Gabrielli@arm.com threeUnequalRegInst(name, Name, opClass, types, op, 13797639Sgblack@eecs.umich.edu True, False, True, readDest) 13807639Sgblack@eecs.umich.edu 13817760SGiacomo.Gabrielli@arm.com def twoEqualRegInst(name, Name, opClass, types, rCount, op, readDest=False): 13827639Sgblack@eecs.umich.edu global header_output, exec_output 13837640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 13847639Sgblack@eecs.umich.edu RegVect srcReg1, srcReg2, destReg; 13857639Sgblack@eecs.umich.edu ''' 13867639Sgblack@eecs.umich.edu for reg in range(rCount): 13877639Sgblack@eecs.umich.edu eWalkCode += ''' 13888588Sgblack@eecs.umich.edu srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 13898588Sgblack@eecs.umich.edu srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw); 13907639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 13917639Sgblack@eecs.umich.edu if readDest: 13927639Sgblack@eecs.umich.edu eWalkCode += ''' 13938588Sgblack@eecs.umich.edu destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 13947639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 13957639Sgblack@eecs.umich.edu readDestCode = '' 13967639Sgblack@eecs.umich.edu if readDest: 13977639Sgblack@eecs.umich.edu readDestCode = 'destElem = gtoh(destReg.elements[i]);' 13987639Sgblack@eecs.umich.edu eWalkCode += ''' 13997853SMatt.Horsnell@ARM.com if (imm < 0 && imm >= eCount) { 140010474Sandreas.hansson@arm.com fault = std::make_shared<UndefinedInstruction>(machInst, false, 140110474Sandreas.hansson@arm.com mnemonic); 14027853SMatt.Horsnell@ARM.com } else { 14037853SMatt.Horsnell@ARM.com for (unsigned i = 0; i < eCount; i++) { 14047853SMatt.Horsnell@ARM.com Element srcElem1 = gtoh(srcReg1.elements[i]); 14057853SMatt.Horsnell@ARM.com Element srcElem2 = gtoh(srcReg2.elements[imm]); 14067853SMatt.Horsnell@ARM.com Element destElem; 14077853SMatt.Horsnell@ARM.com %(readDest)s 14087853SMatt.Horsnell@ARM.com %(op)s 14097853SMatt.Horsnell@ARM.com destReg.elements[i] = htog(destElem); 14107853SMatt.Horsnell@ARM.com } 14117639Sgblack@eecs.umich.edu } 14127639Sgblack@eecs.umich.edu ''' % { "op" : op, "readDest" : readDestCode } 14137639Sgblack@eecs.umich.edu for reg in range(rCount): 14147639Sgblack@eecs.umich.edu eWalkCode += ''' 14158588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 14167639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 14177639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 14187639Sgblack@eecs.umich.edu "RegRegRegImmOp", 14197639Sgblack@eecs.umich.edu { "code": eWalkCode, 14207639Sgblack@eecs.umich.edu "r_count": rCount, 14217760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14227760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 14237639Sgblack@eecs.umich.edu header_output += NeonRegRegRegImmOpDeclare.subst(iop) 14247639Sgblack@eecs.umich.edu exec_output += NeonEqualRegExecute.subst(iop) 14257639Sgblack@eecs.umich.edu for type in types: 14267639Sgblack@eecs.umich.edu substDict = { "targs" : type, 14277639Sgblack@eecs.umich.edu "class_name" : Name } 14287639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 14297639Sgblack@eecs.umich.edu 14307760SGiacomo.Gabrielli@arm.com def twoRegLongInst(name, Name, opClass, types, op, readDest=False): 14317639Sgblack@eecs.umich.edu global header_output, exec_output 14327639Sgblack@eecs.umich.edu rCount = 2 14337640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 14347639Sgblack@eecs.umich.edu RegVect srcReg1, srcReg2; 14357639Sgblack@eecs.umich.edu BigRegVect destReg; 14367639Sgblack@eecs.umich.edu ''' 14377639Sgblack@eecs.umich.edu for reg in range(rCount): 14387639Sgblack@eecs.umich.edu eWalkCode += ''' 14398588Sgblack@eecs.umich.edu srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 14408588Sgblack@eecs.umich.edu srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw);; 14417639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 14427639Sgblack@eecs.umich.edu if readDest: 14437639Sgblack@eecs.umich.edu for reg in range(2 * rCount): 14447639Sgblack@eecs.umich.edu eWalkCode += ''' 14458588Sgblack@eecs.umich.edu destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 14467639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 14477639Sgblack@eecs.umich.edu readDestCode = '' 14487639Sgblack@eecs.umich.edu if readDest: 14497639Sgblack@eecs.umich.edu readDestCode = 'destElem = gtoh(destReg.elements[i]);' 14507639Sgblack@eecs.umich.edu eWalkCode += ''' 14517853SMatt.Horsnell@ARM.com if (imm < 0 && imm >= eCount) { 145210474Sandreas.hansson@arm.com fault = std::make_shared<UndefinedInstruction>(machInst, false, 145310474Sandreas.hansson@arm.com mnemonic); 14547853SMatt.Horsnell@ARM.com } else { 14557853SMatt.Horsnell@ARM.com for (unsigned i = 0; i < eCount; i++) { 14567853SMatt.Horsnell@ARM.com Element srcElem1 = gtoh(srcReg1.elements[i]); 14577853SMatt.Horsnell@ARM.com Element srcElem2 = gtoh(srcReg2.elements[imm]); 14587853SMatt.Horsnell@ARM.com BigElement destElem; 14597853SMatt.Horsnell@ARM.com %(readDest)s 14607853SMatt.Horsnell@ARM.com %(op)s 14617853SMatt.Horsnell@ARM.com destReg.elements[i] = htog(destElem); 14627853SMatt.Horsnell@ARM.com } 14637639Sgblack@eecs.umich.edu } 14647639Sgblack@eecs.umich.edu ''' % { "op" : op, "readDest" : readDestCode } 14657639Sgblack@eecs.umich.edu for reg in range(2 * rCount): 14667639Sgblack@eecs.umich.edu eWalkCode += ''' 14678588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 14687639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 14697639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 14707639Sgblack@eecs.umich.edu "RegRegRegImmOp", 14717639Sgblack@eecs.umich.edu { "code": eWalkCode, 14727639Sgblack@eecs.umich.edu "r_count": rCount, 14737760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 14747760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 14757639Sgblack@eecs.umich.edu header_output += NeonRegRegRegImmOpDeclare.subst(iop) 14767639Sgblack@eecs.umich.edu exec_output += NeonUnequalRegExecute.subst(iop) 14777639Sgblack@eecs.umich.edu for type in types: 14787639Sgblack@eecs.umich.edu substDict = { "targs" : type, 14797639Sgblack@eecs.umich.edu "class_name" : Name } 14807639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 14817639Sgblack@eecs.umich.edu 14827760SGiacomo.Gabrielli@arm.com def twoEqualRegInstFp(name, Name, opClass, types, rCount, op, readDest=False): 14837639Sgblack@eecs.umich.edu global header_output, exec_output 14847640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 148513544Sgabeblack@google.com typedef float FloatVect[rCount]; 14867639Sgblack@eecs.umich.edu FloatVect srcRegs1, srcRegs2, destRegs; 14877639Sgblack@eecs.umich.edu ''' 14887639Sgblack@eecs.umich.edu for reg in range(rCount): 14897639Sgblack@eecs.umich.edu eWalkCode += ''' 14907639Sgblack@eecs.umich.edu srcRegs1[%(reg)d] = FpOp1P%(reg)d; 14917639Sgblack@eecs.umich.edu srcRegs2[%(reg)d] = FpOp2P%(reg)d; 14927639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 14937639Sgblack@eecs.umich.edu if readDest: 14947639Sgblack@eecs.umich.edu eWalkCode += ''' 14957639Sgblack@eecs.umich.edu destRegs[%(reg)d] = FpDestP%(reg)d; 14967639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 14977639Sgblack@eecs.umich.edu readDestCode = '' 14987639Sgblack@eecs.umich.edu if readDest: 14997639Sgblack@eecs.umich.edu readDestCode = 'destReg = destRegs[i];' 15007639Sgblack@eecs.umich.edu eWalkCode += ''' 15017853SMatt.Horsnell@ARM.com if (imm < 0 && imm >= eCount) { 150210474Sandreas.hansson@arm.com fault = std::make_shared<UndefinedInstruction>(machInst, false, 150310474Sandreas.hansson@arm.com mnemonic); 15047853SMatt.Horsnell@ARM.com } else { 15057853SMatt.Horsnell@ARM.com for (unsigned i = 0; i < rCount; i++) { 150613544Sgabeblack@google.com float srcReg1 = srcRegs1[i]; 150713544Sgabeblack@google.com float srcReg2 = srcRegs2[imm]; 150813544Sgabeblack@google.com float destReg; 15097853SMatt.Horsnell@ARM.com %(readDest)s 15107853SMatt.Horsnell@ARM.com %(op)s 15117853SMatt.Horsnell@ARM.com destRegs[i] = destReg; 15127853SMatt.Horsnell@ARM.com } 15137639Sgblack@eecs.umich.edu } 15147639Sgblack@eecs.umich.edu ''' % { "op" : op, "readDest" : readDestCode } 15157639Sgblack@eecs.umich.edu for reg in range(rCount): 15167639Sgblack@eecs.umich.edu eWalkCode += ''' 15177639Sgblack@eecs.umich.edu FpDestP%(reg)d = destRegs[%(reg)d]; 15187639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 15197639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 15207639Sgblack@eecs.umich.edu "FpRegRegRegImmOp", 15217639Sgblack@eecs.umich.edu { "code": eWalkCode, 15227639Sgblack@eecs.umich.edu "r_count": rCount, 15237760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15247760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 15257639Sgblack@eecs.umich.edu header_output += NeonRegRegRegImmOpDeclare.subst(iop) 15267639Sgblack@eecs.umich.edu exec_output += NeonEqualRegExecute.subst(iop) 15277639Sgblack@eecs.umich.edu for type in types: 15287639Sgblack@eecs.umich.edu substDict = { "targs" : type, 15297639Sgblack@eecs.umich.edu "class_name" : Name } 15307639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 15317639Sgblack@eecs.umich.edu 15327760SGiacomo.Gabrielli@arm.com def twoRegShiftInst(name, Name, opClass, types, rCount, op, 15337639Sgblack@eecs.umich.edu readDest=False, toInt=False, fromInt=False): 15347639Sgblack@eecs.umich.edu global header_output, exec_output 15357640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 15367639Sgblack@eecs.umich.edu RegVect srcRegs1, destRegs; 15377639Sgblack@eecs.umich.edu ''' 15387639Sgblack@eecs.umich.edu for reg in range(rCount): 15397639Sgblack@eecs.umich.edu eWalkCode += ''' 15408588Sgblack@eecs.umich.edu srcRegs1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 15417639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 15427639Sgblack@eecs.umich.edu if readDest: 15437639Sgblack@eecs.umich.edu eWalkCode += ''' 15448588Sgblack@eecs.umich.edu destRegs.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 15457639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 15467639Sgblack@eecs.umich.edu readDestCode = '' 15477639Sgblack@eecs.umich.edu if readDest: 15487639Sgblack@eecs.umich.edu readDestCode = 'destElem = gtoh(destRegs.elements[i]);' 15497639Sgblack@eecs.umich.edu if toInt: 15507639Sgblack@eecs.umich.edu readDestCode = 'destReg = gtoh(destRegs.regs[i]);' 15517639Sgblack@eecs.umich.edu readOpCode = 'Element srcElem1 = gtoh(srcRegs1.elements[i]);' 15527639Sgblack@eecs.umich.edu if fromInt: 155313544Sgabeblack@google.com readOpCode = 'uint32_t srcReg1 = gtoh(srcRegs1.regs[i]);' 15547639Sgblack@eecs.umich.edu declDest = 'Element destElem;' 15557639Sgblack@eecs.umich.edu writeDestCode = 'destRegs.elements[i] = htog(destElem);' 15567639Sgblack@eecs.umich.edu if toInt: 155713544Sgabeblack@google.com declDest = 'uint32_t destReg;' 15587639Sgblack@eecs.umich.edu writeDestCode = 'destRegs.regs[i] = htog(destReg);' 15597639Sgblack@eecs.umich.edu eWalkCode += ''' 15607639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 15617639Sgblack@eecs.umich.edu %(readOp)s 15627639Sgblack@eecs.umich.edu %(declDest)s 15637639Sgblack@eecs.umich.edu %(readDest)s 15647639Sgblack@eecs.umich.edu %(op)s 15657639Sgblack@eecs.umich.edu %(writeDest)s 15667639Sgblack@eecs.umich.edu } 15677639Sgblack@eecs.umich.edu ''' % { "readOp" : readOpCode, 15687639Sgblack@eecs.umich.edu "declDest" : declDest, 15697639Sgblack@eecs.umich.edu "readDest" : readDestCode, 15707639Sgblack@eecs.umich.edu "op" : op, 15717639Sgblack@eecs.umich.edu "writeDest" : writeDestCode } 15727639Sgblack@eecs.umich.edu for reg in range(rCount): 15737639Sgblack@eecs.umich.edu eWalkCode += ''' 15748588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destRegs.regs[%(reg)d]); 15757639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 15767639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 15777639Sgblack@eecs.umich.edu "RegRegImmOp", 15787639Sgblack@eecs.umich.edu { "code": eWalkCode, 15797639Sgblack@eecs.umich.edu "r_count": rCount, 15807760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 15817760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 15827639Sgblack@eecs.umich.edu header_output += NeonRegRegImmOpDeclare.subst(iop) 15837639Sgblack@eecs.umich.edu exec_output += NeonEqualRegExecute.subst(iop) 15847639Sgblack@eecs.umich.edu for type in types: 15857639Sgblack@eecs.umich.edu substDict = { "targs" : type, 15867639Sgblack@eecs.umich.edu "class_name" : Name } 15877639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 15887639Sgblack@eecs.umich.edu 15897760SGiacomo.Gabrielli@arm.com def twoRegNarrowShiftInst(name, Name, opClass, types, op, readDest=False): 15907639Sgblack@eecs.umich.edu global header_output, exec_output 15917640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 15927639Sgblack@eecs.umich.edu BigRegVect srcReg1; 15937639Sgblack@eecs.umich.edu RegVect destReg; 15947639Sgblack@eecs.umich.edu ''' 15957639Sgblack@eecs.umich.edu for reg in range(4): 15967639Sgblack@eecs.umich.edu eWalkCode += ''' 15978588Sgblack@eecs.umich.edu srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 15987639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 15997639Sgblack@eecs.umich.edu if readDest: 16007639Sgblack@eecs.umich.edu for reg in range(2): 16017639Sgblack@eecs.umich.edu eWalkCode += ''' 16028588Sgblack@eecs.umich.edu destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 16037639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 16047639Sgblack@eecs.umich.edu readDestCode = '' 16057639Sgblack@eecs.umich.edu if readDest: 16067639Sgblack@eecs.umich.edu readDestCode = 'destElem = gtoh(destReg.elements[i]);' 16077639Sgblack@eecs.umich.edu eWalkCode += ''' 16087639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 16097639Sgblack@eecs.umich.edu BigElement srcElem1 = gtoh(srcReg1.elements[i]); 16107639Sgblack@eecs.umich.edu Element destElem; 16117639Sgblack@eecs.umich.edu %(readDest)s 16127639Sgblack@eecs.umich.edu %(op)s 16137639Sgblack@eecs.umich.edu destReg.elements[i] = htog(destElem); 16147639Sgblack@eecs.umich.edu } 16157639Sgblack@eecs.umich.edu ''' % { "op" : op, "readDest" : readDestCode } 16167639Sgblack@eecs.umich.edu for reg in range(2): 16177639Sgblack@eecs.umich.edu eWalkCode += ''' 16188588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 16197639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 16207639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 16217639Sgblack@eecs.umich.edu "RegRegImmOp", 16227639Sgblack@eecs.umich.edu { "code": eWalkCode, 16237639Sgblack@eecs.umich.edu "r_count": 2, 16247760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 16257760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 16267639Sgblack@eecs.umich.edu header_output += NeonRegRegImmOpDeclare.subst(iop) 16277639Sgblack@eecs.umich.edu exec_output += NeonUnequalRegExecute.subst(iop) 16287639Sgblack@eecs.umich.edu for type in types: 16297639Sgblack@eecs.umich.edu substDict = { "targs" : type, 16307639Sgblack@eecs.umich.edu "class_name" : Name } 16317639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 16327639Sgblack@eecs.umich.edu 16337760SGiacomo.Gabrielli@arm.com def twoRegLongShiftInst(name, Name, opClass, types, op, readDest=False): 16347639Sgblack@eecs.umich.edu global header_output, exec_output 16357640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 16367639Sgblack@eecs.umich.edu RegVect srcReg1; 16377639Sgblack@eecs.umich.edu BigRegVect destReg; 16387639Sgblack@eecs.umich.edu ''' 16397639Sgblack@eecs.umich.edu for reg in range(2): 16407639Sgblack@eecs.umich.edu eWalkCode += ''' 16418588Sgblack@eecs.umich.edu srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 16427639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 16437639Sgblack@eecs.umich.edu if readDest: 16447639Sgblack@eecs.umich.edu for reg in range(4): 16457639Sgblack@eecs.umich.edu eWalkCode += ''' 16468588Sgblack@eecs.umich.edu destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 16477639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 16487639Sgblack@eecs.umich.edu readDestCode = '' 16497639Sgblack@eecs.umich.edu if readDest: 16507639Sgblack@eecs.umich.edu readDestCode = 'destReg = gtoh(destReg.elements[i]);' 16517639Sgblack@eecs.umich.edu eWalkCode += ''' 16527639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 16537639Sgblack@eecs.umich.edu Element srcElem1 = gtoh(srcReg1.elements[i]); 16547639Sgblack@eecs.umich.edu BigElement destElem; 16557639Sgblack@eecs.umich.edu %(readDest)s 16567639Sgblack@eecs.umich.edu %(op)s 16577639Sgblack@eecs.umich.edu destReg.elements[i] = htog(destElem); 16587639Sgblack@eecs.umich.edu } 16597639Sgblack@eecs.umich.edu ''' % { "op" : op, "readDest" : readDestCode } 16607639Sgblack@eecs.umich.edu for reg in range(4): 16617639Sgblack@eecs.umich.edu eWalkCode += ''' 16628588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 16637639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 16647639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 16657639Sgblack@eecs.umich.edu "RegRegImmOp", 16667639Sgblack@eecs.umich.edu { "code": eWalkCode, 16677639Sgblack@eecs.umich.edu "r_count": 2, 16687760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 16697760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 16707639Sgblack@eecs.umich.edu header_output += NeonRegRegImmOpDeclare.subst(iop) 16717639Sgblack@eecs.umich.edu exec_output += NeonUnequalRegExecute.subst(iop) 16727639Sgblack@eecs.umich.edu for type in types: 16737639Sgblack@eecs.umich.edu substDict = { "targs" : type, 16747639Sgblack@eecs.umich.edu "class_name" : Name } 16757639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 16767639Sgblack@eecs.umich.edu 16777760SGiacomo.Gabrielli@arm.com def twoRegMiscInst(name, Name, opClass, types, rCount, op, readDest=False): 16787639Sgblack@eecs.umich.edu global header_output, exec_output 16797640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 16807639Sgblack@eecs.umich.edu RegVect srcReg1, destReg; 16817639Sgblack@eecs.umich.edu ''' 16827639Sgblack@eecs.umich.edu for reg in range(rCount): 16837639Sgblack@eecs.umich.edu eWalkCode += ''' 16848588Sgblack@eecs.umich.edu srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 16857639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 16867639Sgblack@eecs.umich.edu if readDest: 16877639Sgblack@eecs.umich.edu eWalkCode += ''' 16888588Sgblack@eecs.umich.edu destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 16897639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 16907639Sgblack@eecs.umich.edu readDestCode = '' 16917639Sgblack@eecs.umich.edu if readDest: 16927639Sgblack@eecs.umich.edu readDestCode = 'destElem = gtoh(destReg.elements[i]);' 16937639Sgblack@eecs.umich.edu eWalkCode += ''' 16947639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 16957639Sgblack@eecs.umich.edu unsigned j = i; 16967639Sgblack@eecs.umich.edu Element srcElem1 = gtoh(srcReg1.elements[i]); 16977639Sgblack@eecs.umich.edu Element destElem; 16987639Sgblack@eecs.umich.edu %(readDest)s 16997639Sgblack@eecs.umich.edu %(op)s 17007639Sgblack@eecs.umich.edu destReg.elements[j] = htog(destElem); 17017639Sgblack@eecs.umich.edu } 17027639Sgblack@eecs.umich.edu ''' % { "op" : op, "readDest" : readDestCode } 17037639Sgblack@eecs.umich.edu for reg in range(rCount): 17047639Sgblack@eecs.umich.edu eWalkCode += ''' 17058588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 17067639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 17077639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 17087639Sgblack@eecs.umich.edu "RegRegOp", 17097639Sgblack@eecs.umich.edu { "code": eWalkCode, 17107639Sgblack@eecs.umich.edu "r_count": rCount, 17117760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 17127760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 17137639Sgblack@eecs.umich.edu header_output += NeonRegRegOpDeclare.subst(iop) 17147639Sgblack@eecs.umich.edu exec_output += NeonEqualRegExecute.subst(iop) 17157639Sgblack@eecs.umich.edu for type in types: 17167639Sgblack@eecs.umich.edu substDict = { "targs" : type, 17177639Sgblack@eecs.umich.edu "class_name" : Name } 17187639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 17197639Sgblack@eecs.umich.edu 17207760SGiacomo.Gabrielli@arm.com def twoRegMiscScInst(name, Name, opClass, types, rCount, op, readDest=False): 17217639Sgblack@eecs.umich.edu global header_output, exec_output 17227640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 17237639Sgblack@eecs.umich.edu RegVect srcReg1, destReg; 17247639Sgblack@eecs.umich.edu ''' 17257639Sgblack@eecs.umich.edu for reg in range(rCount): 17267639Sgblack@eecs.umich.edu eWalkCode += ''' 17278588Sgblack@eecs.umich.edu srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 17287639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 17297639Sgblack@eecs.umich.edu if readDest: 17307639Sgblack@eecs.umich.edu eWalkCode += ''' 17318588Sgblack@eecs.umich.edu destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 17327639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 17337639Sgblack@eecs.umich.edu readDestCode = '' 17347639Sgblack@eecs.umich.edu if readDest: 17357639Sgblack@eecs.umich.edu readDestCode = 'destElem = gtoh(destReg.elements[i]);' 17367639Sgblack@eecs.umich.edu eWalkCode += ''' 17377639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 17387639Sgblack@eecs.umich.edu Element srcElem1 = gtoh(srcReg1.elements[imm]); 17397639Sgblack@eecs.umich.edu Element destElem; 17407639Sgblack@eecs.umich.edu %(readDest)s 17417639Sgblack@eecs.umich.edu %(op)s 17427639Sgblack@eecs.umich.edu destReg.elements[i] = htog(destElem); 17437639Sgblack@eecs.umich.edu } 17447639Sgblack@eecs.umich.edu ''' % { "op" : op, "readDest" : readDestCode } 17457639Sgblack@eecs.umich.edu for reg in range(rCount): 17467639Sgblack@eecs.umich.edu eWalkCode += ''' 17478588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 17487639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 17497639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 17507639Sgblack@eecs.umich.edu "RegRegImmOp", 17517639Sgblack@eecs.umich.edu { "code": eWalkCode, 17527639Sgblack@eecs.umich.edu "r_count": rCount, 17537760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 17547760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 17557639Sgblack@eecs.umich.edu header_output += NeonRegRegImmOpDeclare.subst(iop) 17567639Sgblack@eecs.umich.edu exec_output += NeonEqualRegExecute.subst(iop) 17577639Sgblack@eecs.umich.edu for type in types: 17587639Sgblack@eecs.umich.edu substDict = { "targs" : type, 17597639Sgblack@eecs.umich.edu "class_name" : Name } 17607639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 17617639Sgblack@eecs.umich.edu 17627760SGiacomo.Gabrielli@arm.com def twoRegMiscScramble(name, Name, opClass, types, rCount, op, readDest=False): 17637639Sgblack@eecs.umich.edu global header_output, exec_output 17647640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 17657639Sgblack@eecs.umich.edu RegVect srcReg1, destReg; 17667639Sgblack@eecs.umich.edu ''' 17677639Sgblack@eecs.umich.edu for reg in range(rCount): 17687639Sgblack@eecs.umich.edu eWalkCode += ''' 17698588Sgblack@eecs.umich.edu srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 17708588Sgblack@eecs.umich.edu destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 17717639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 17727639Sgblack@eecs.umich.edu if readDest: 17737639Sgblack@eecs.umich.edu eWalkCode += ''' 17747639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 17757639Sgblack@eecs.umich.edu readDestCode = '' 17767639Sgblack@eecs.umich.edu if readDest: 17777639Sgblack@eecs.umich.edu readDestCode = 'destElem = gtoh(destReg.elements[i]);' 17787639Sgblack@eecs.umich.edu eWalkCode += op 17797639Sgblack@eecs.umich.edu for reg in range(rCount): 17807639Sgblack@eecs.umich.edu eWalkCode += ''' 17818588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 17828588Sgblack@eecs.umich.edu FpOp1P%(reg)d_uw = gtoh(srcReg1.regs[%(reg)d]); 17837639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 17847639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 17857639Sgblack@eecs.umich.edu "RegRegOp", 17867639Sgblack@eecs.umich.edu { "code": eWalkCode, 17877639Sgblack@eecs.umich.edu "r_count": rCount, 17887760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 17897760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 17907639Sgblack@eecs.umich.edu header_output += NeonRegRegOpDeclare.subst(iop) 17917639Sgblack@eecs.umich.edu exec_output += NeonEqualRegExecute.subst(iop) 17927639Sgblack@eecs.umich.edu for type in types: 17937639Sgblack@eecs.umich.edu substDict = { "targs" : type, 17947639Sgblack@eecs.umich.edu "class_name" : Name } 17957639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 17967639Sgblack@eecs.umich.edu 17977760SGiacomo.Gabrielli@arm.com def twoRegMiscInstFp(name, Name, opClass, types, rCount, op, 17987639Sgblack@eecs.umich.edu readDest=False, toInt=False): 17997639Sgblack@eecs.umich.edu global header_output, exec_output 18007640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 180113544Sgabeblack@google.com typedef float FloatVect[rCount]; 18027639Sgblack@eecs.umich.edu FloatVect srcRegs1; 18037639Sgblack@eecs.umich.edu ''' 18047639Sgblack@eecs.umich.edu if toInt: 18057639Sgblack@eecs.umich.edu eWalkCode += 'RegVect destRegs;\n' 18067639Sgblack@eecs.umich.edu else: 18077639Sgblack@eecs.umich.edu eWalkCode += 'FloatVect destRegs;\n' 18087639Sgblack@eecs.umich.edu for reg in range(rCount): 18097639Sgblack@eecs.umich.edu eWalkCode += ''' 18107639Sgblack@eecs.umich.edu srcRegs1[%(reg)d] = FpOp1P%(reg)d; 18117639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 18127639Sgblack@eecs.umich.edu if readDest: 18137639Sgblack@eecs.umich.edu if toInt: 18147639Sgblack@eecs.umich.edu eWalkCode += ''' 18157639Sgblack@eecs.umich.edu destRegs.regs[%(reg)d] = FpDestP%(reg)d.bits; 18167639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 18177639Sgblack@eecs.umich.edu else: 18187639Sgblack@eecs.umich.edu eWalkCode += ''' 18197639Sgblack@eecs.umich.edu destRegs[%(reg)d] = FpDestP%(reg)d; 18207639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 18217639Sgblack@eecs.umich.edu readDestCode = '' 18227639Sgblack@eecs.umich.edu if readDest: 18237639Sgblack@eecs.umich.edu readDestCode = 'destReg = destRegs[i];' 182413544Sgabeblack@google.com destType = 'float' 18257639Sgblack@eecs.umich.edu writeDest = 'destRegs[r] = destReg;' 18267639Sgblack@eecs.umich.edu if toInt: 182713544Sgabeblack@google.com destType = 'uint32_t' 18287639Sgblack@eecs.umich.edu writeDest = 'destRegs.regs[r] = destReg;' 18297639Sgblack@eecs.umich.edu eWalkCode += ''' 18307639Sgblack@eecs.umich.edu for (unsigned r = 0; r < rCount; r++) { 183113544Sgabeblack@google.com float srcReg1 = srcRegs1[r]; 18327639Sgblack@eecs.umich.edu %(destType)s destReg; 18337639Sgblack@eecs.umich.edu %(readDest)s 18347639Sgblack@eecs.umich.edu %(op)s 18357639Sgblack@eecs.umich.edu %(writeDest)s 18367639Sgblack@eecs.umich.edu } 18377639Sgblack@eecs.umich.edu ''' % { "op" : op, 18387639Sgblack@eecs.umich.edu "readDest" : readDestCode, 18397639Sgblack@eecs.umich.edu "destType" : destType, 18407639Sgblack@eecs.umich.edu "writeDest" : writeDest } 18417639Sgblack@eecs.umich.edu for reg in range(rCount): 18427639Sgblack@eecs.umich.edu if toInt: 18437639Sgblack@eecs.umich.edu eWalkCode += ''' 18448588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = destRegs.regs[%(reg)d]; 18457639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 18467639Sgblack@eecs.umich.edu else: 18477639Sgblack@eecs.umich.edu eWalkCode += ''' 18487639Sgblack@eecs.umich.edu FpDestP%(reg)d = destRegs[%(reg)d]; 18497639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 18507639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 18517639Sgblack@eecs.umich.edu "FpRegRegOp", 18527639Sgblack@eecs.umich.edu { "code": eWalkCode, 18537639Sgblack@eecs.umich.edu "r_count": rCount, 18547760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 18557760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 18567639Sgblack@eecs.umich.edu header_output += NeonRegRegOpDeclare.subst(iop) 18577639Sgblack@eecs.umich.edu exec_output += NeonEqualRegExecute.subst(iop) 18587639Sgblack@eecs.umich.edu for type in types: 18597639Sgblack@eecs.umich.edu substDict = { "targs" : type, 18607639Sgblack@eecs.umich.edu "class_name" : Name } 18617639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 18627639Sgblack@eecs.umich.edu 18637760SGiacomo.Gabrielli@arm.com def twoRegCondenseInst(name, Name, opClass, types, rCount, op, readDest=False): 18647639Sgblack@eecs.umich.edu global header_output, exec_output 18657640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 18667639Sgblack@eecs.umich.edu RegVect srcRegs; 18677639Sgblack@eecs.umich.edu BigRegVect destReg; 18687639Sgblack@eecs.umich.edu ''' 18697639Sgblack@eecs.umich.edu for reg in range(rCount): 18707639Sgblack@eecs.umich.edu eWalkCode += ''' 18718588Sgblack@eecs.umich.edu srcRegs.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 18727639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 18737639Sgblack@eecs.umich.edu if readDest: 18747639Sgblack@eecs.umich.edu eWalkCode += ''' 18758588Sgblack@eecs.umich.edu destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 18767639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 18777639Sgblack@eecs.umich.edu readDestCode = '' 18787639Sgblack@eecs.umich.edu if readDest: 18797639Sgblack@eecs.umich.edu readDestCode = 'destElem = gtoh(destReg.elements[i]);' 18807639Sgblack@eecs.umich.edu eWalkCode += ''' 18817639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount / 2; i++) { 18827639Sgblack@eecs.umich.edu Element srcElem1 = gtoh(srcRegs.elements[2 * i]); 18837639Sgblack@eecs.umich.edu Element srcElem2 = gtoh(srcRegs.elements[2 * i + 1]); 18847639Sgblack@eecs.umich.edu BigElement destElem; 18857639Sgblack@eecs.umich.edu %(readDest)s 18867639Sgblack@eecs.umich.edu %(op)s 18877639Sgblack@eecs.umich.edu destReg.elements[i] = htog(destElem); 18887639Sgblack@eecs.umich.edu } 18897639Sgblack@eecs.umich.edu ''' % { "op" : op, "readDest" : readDestCode } 18907639Sgblack@eecs.umich.edu for reg in range(rCount): 18917639Sgblack@eecs.umich.edu eWalkCode += ''' 18928588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 18937639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 18947639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 18957639Sgblack@eecs.umich.edu "RegRegOp", 18967639Sgblack@eecs.umich.edu { "code": eWalkCode, 18977639Sgblack@eecs.umich.edu "r_count": rCount, 18987760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 18997760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 19007639Sgblack@eecs.umich.edu header_output += NeonRegRegOpDeclare.subst(iop) 19017639Sgblack@eecs.umich.edu exec_output += NeonUnequalRegExecute.subst(iop) 19027639Sgblack@eecs.umich.edu for type in types: 19037639Sgblack@eecs.umich.edu substDict = { "targs" : type, 19047639Sgblack@eecs.umich.edu "class_name" : Name } 19057639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 19067639Sgblack@eecs.umich.edu 19077760SGiacomo.Gabrielli@arm.com def twoRegNarrowMiscInst(name, Name, opClass, types, op, readDest=False): 19087639Sgblack@eecs.umich.edu global header_output, exec_output 19097640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 19107639Sgblack@eecs.umich.edu BigRegVect srcReg1; 19117639Sgblack@eecs.umich.edu RegVect destReg; 19127639Sgblack@eecs.umich.edu ''' 19137639Sgblack@eecs.umich.edu for reg in range(4): 19147639Sgblack@eecs.umich.edu eWalkCode += ''' 19158588Sgblack@eecs.umich.edu srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 19167639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 19177639Sgblack@eecs.umich.edu if readDest: 19187639Sgblack@eecs.umich.edu for reg in range(2): 19197639Sgblack@eecs.umich.edu eWalkCode += ''' 19208588Sgblack@eecs.umich.edu destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 19217639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 19227639Sgblack@eecs.umich.edu readDestCode = '' 19237639Sgblack@eecs.umich.edu if readDest: 19247639Sgblack@eecs.umich.edu readDestCode = 'destElem = gtoh(destReg.elements[i]);' 19257639Sgblack@eecs.umich.edu eWalkCode += ''' 19267639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 19277639Sgblack@eecs.umich.edu BigElement srcElem1 = gtoh(srcReg1.elements[i]); 19287639Sgblack@eecs.umich.edu Element destElem; 19297639Sgblack@eecs.umich.edu %(readDest)s 19307639Sgblack@eecs.umich.edu %(op)s 19317639Sgblack@eecs.umich.edu destReg.elements[i] = htog(destElem); 19327639Sgblack@eecs.umich.edu } 19337639Sgblack@eecs.umich.edu ''' % { "op" : op, "readDest" : readDestCode } 19347639Sgblack@eecs.umich.edu for reg in range(2): 19357639Sgblack@eecs.umich.edu eWalkCode += ''' 19368588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 19377639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 19387639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 19397639Sgblack@eecs.umich.edu "RegRegOp", 19407639Sgblack@eecs.umich.edu { "code": eWalkCode, 19417639Sgblack@eecs.umich.edu "r_count": 2, 19427760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 19437760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 19447639Sgblack@eecs.umich.edu header_output += NeonRegRegOpDeclare.subst(iop) 19457639Sgblack@eecs.umich.edu exec_output += NeonUnequalRegExecute.subst(iop) 19467639Sgblack@eecs.umich.edu for type in types: 19477639Sgblack@eecs.umich.edu substDict = { "targs" : type, 19487639Sgblack@eecs.umich.edu "class_name" : Name } 19497639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 19507639Sgblack@eecs.umich.edu 19517760SGiacomo.Gabrielli@arm.com def oneRegImmInst(name, Name, opClass, types, rCount, op, readDest=False): 19527639Sgblack@eecs.umich.edu global header_output, exec_output 19537640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 19547639Sgblack@eecs.umich.edu RegVect destReg; 19557639Sgblack@eecs.umich.edu ''' 19567639Sgblack@eecs.umich.edu if readDest: 19577639Sgblack@eecs.umich.edu for reg in range(rCount): 19587639Sgblack@eecs.umich.edu eWalkCode += ''' 19598588Sgblack@eecs.umich.edu destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 19607639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 19617639Sgblack@eecs.umich.edu readDestCode = '' 19627639Sgblack@eecs.umich.edu if readDest: 19637639Sgblack@eecs.umich.edu readDestCode = 'destElem = gtoh(destReg.elements[i]);' 19647639Sgblack@eecs.umich.edu eWalkCode += ''' 19657639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 19667639Sgblack@eecs.umich.edu Element destElem; 19677639Sgblack@eecs.umich.edu %(readDest)s 19687639Sgblack@eecs.umich.edu %(op)s 19697639Sgblack@eecs.umich.edu destReg.elements[i] = htog(destElem); 19707639Sgblack@eecs.umich.edu } 19717639Sgblack@eecs.umich.edu ''' % { "op" : op, "readDest" : readDestCode } 19727639Sgblack@eecs.umich.edu for reg in range(rCount): 19737639Sgblack@eecs.umich.edu eWalkCode += ''' 19748588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 19757639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 19767639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 19777639Sgblack@eecs.umich.edu "RegImmOp", 19787639Sgblack@eecs.umich.edu { "code": eWalkCode, 19797639Sgblack@eecs.umich.edu "r_count": rCount, 19807760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 19817760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 19827639Sgblack@eecs.umich.edu header_output += NeonRegImmOpDeclare.subst(iop) 19837639Sgblack@eecs.umich.edu exec_output += NeonEqualRegExecute.subst(iop) 19847639Sgblack@eecs.umich.edu for type in types: 19857639Sgblack@eecs.umich.edu substDict = { "targs" : type, 19867639Sgblack@eecs.umich.edu "class_name" : Name } 19877639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 19887639Sgblack@eecs.umich.edu 19897760SGiacomo.Gabrielli@arm.com def twoRegLongMiscInst(name, Name, opClass, types, op, readDest=False): 19907639Sgblack@eecs.umich.edu global header_output, exec_output 19917640Sgblack@eecs.umich.edu eWalkCode = simdEnabledCheckCode + ''' 19927639Sgblack@eecs.umich.edu RegVect srcReg1; 19937639Sgblack@eecs.umich.edu BigRegVect destReg; 19947639Sgblack@eecs.umich.edu ''' 19957639Sgblack@eecs.umich.edu for reg in range(2): 19967639Sgblack@eecs.umich.edu eWalkCode += ''' 19978588Sgblack@eecs.umich.edu srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 19987639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 19997639Sgblack@eecs.umich.edu if readDest: 20007639Sgblack@eecs.umich.edu for reg in range(4): 20017639Sgblack@eecs.umich.edu eWalkCode += ''' 20028588Sgblack@eecs.umich.edu destReg.regs[%(reg)d] = htog(FpDestP%(reg)d_uw); 20037639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 20047639Sgblack@eecs.umich.edu readDestCode = '' 20057639Sgblack@eecs.umich.edu if readDest: 20067639Sgblack@eecs.umich.edu readDestCode = 'destReg = gtoh(destReg.elements[i]);' 20077639Sgblack@eecs.umich.edu eWalkCode += ''' 20087639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 20097639Sgblack@eecs.umich.edu Element srcElem1 = gtoh(srcReg1.elements[i]); 20107639Sgblack@eecs.umich.edu BigElement destElem; 20117639Sgblack@eecs.umich.edu %(readDest)s 20127639Sgblack@eecs.umich.edu %(op)s 20137639Sgblack@eecs.umich.edu destReg.elements[i] = htog(destElem); 20147639Sgblack@eecs.umich.edu } 20157639Sgblack@eecs.umich.edu ''' % { "op" : op, "readDest" : readDestCode } 20167639Sgblack@eecs.umich.edu for reg in range(4): 20177639Sgblack@eecs.umich.edu eWalkCode += ''' 20188588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 20197639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 20207639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 20217639Sgblack@eecs.umich.edu "RegRegOp", 20227639Sgblack@eecs.umich.edu { "code": eWalkCode, 20237639Sgblack@eecs.umich.edu "r_count": 2, 20247760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 20257760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 20267639Sgblack@eecs.umich.edu header_output += NeonRegRegOpDeclare.subst(iop) 20277639Sgblack@eecs.umich.edu exec_output += NeonUnequalRegExecute.subst(iop) 20287639Sgblack@eecs.umich.edu for type in types: 20297639Sgblack@eecs.umich.edu substDict = { "targs" : type, 20307639Sgblack@eecs.umich.edu "class_name" : Name } 20317639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 20327639Sgblack@eecs.umich.edu 20337639Sgblack@eecs.umich.edu vhaddCode = ''' 20347639Sgblack@eecs.umich.edu Element carryBit = 20357639Sgblack@eecs.umich.edu (((unsigned)srcElem1 & 0x1) + 20367639Sgblack@eecs.umich.edu ((unsigned)srcElem2 & 0x1)) >> 1; 20377639Sgblack@eecs.umich.edu // Use division instead of a shift to ensure the sign extension works 20387639Sgblack@eecs.umich.edu // right. The compiler will figure out if it can be a shift. Mask the 20397639Sgblack@eecs.umich.edu // inputs so they get truncated correctly. 20407639Sgblack@eecs.umich.edu destElem = (((srcElem1 & ~(Element)1) / 2) + 20417639Sgblack@eecs.umich.edu ((srcElem2 & ~(Element)1) / 2)) + carryBit; 20427639Sgblack@eecs.umich.edu ''' 20437760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vhadd", "VhaddD", "SimdAddOp", allTypes, 2, vhaddCode) 20447760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vhadd", "VhaddQ", "SimdAddOp", allTypes, 4, vhaddCode) 20457639Sgblack@eecs.umich.edu 20467639Sgblack@eecs.umich.edu vrhaddCode = ''' 20477639Sgblack@eecs.umich.edu Element carryBit = 20487639Sgblack@eecs.umich.edu (((unsigned)srcElem1 & 0x1) + 20497639Sgblack@eecs.umich.edu ((unsigned)srcElem2 & 0x1) + 1) >> 1; 20507639Sgblack@eecs.umich.edu // Use division instead of a shift to ensure the sign extension works 20517639Sgblack@eecs.umich.edu // right. The compiler will figure out if it can be a shift. Mask the 20527639Sgblack@eecs.umich.edu // inputs so they get truncated correctly. 20537639Sgblack@eecs.umich.edu destElem = (((srcElem1 & ~(Element)1) / 2) + 20547639Sgblack@eecs.umich.edu ((srcElem2 & ~(Element)1) / 2)) + carryBit; 20557639Sgblack@eecs.umich.edu ''' 20567760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vrhadd", "VrhaddD", "SimdAddOp", allTypes, 2, vrhaddCode) 20577760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vrhadd", "VrhaddQ", "SimdAddOp", allTypes, 4, vrhaddCode) 20587639Sgblack@eecs.umich.edu 20597639Sgblack@eecs.umich.edu vhsubCode = ''' 20607639Sgblack@eecs.umich.edu Element barrowBit = 20617639Sgblack@eecs.umich.edu (((srcElem1 & 0x1) - (srcElem2 & 0x1)) >> 1) & 0x1; 20627639Sgblack@eecs.umich.edu // Use division instead of a shift to ensure the sign extension works 20637639Sgblack@eecs.umich.edu // right. The compiler will figure out if it can be a shift. Mask the 20647639Sgblack@eecs.umich.edu // inputs so they get truncated correctly. 20657639Sgblack@eecs.umich.edu destElem = (((srcElem1 & ~(Element)1) / 2) - 20667639Sgblack@eecs.umich.edu ((srcElem2 & ~(Element)1) / 2)) - barrowBit; 20677639Sgblack@eecs.umich.edu ''' 20687760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vhsub", "VhsubD", "SimdAddOp", allTypes, 2, vhsubCode) 20697760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vhsub", "VhsubQ", "SimdAddOp", allTypes, 4, vhsubCode) 20707639Sgblack@eecs.umich.edu 20717639Sgblack@eecs.umich.edu vandCode = ''' 20727639Sgblack@eecs.umich.edu destElem = srcElem1 & srcElem2; 20737639Sgblack@eecs.umich.edu ''' 20747760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vand", "VandD", "SimdAluOp", unsignedTypes, 2, vandCode) 20757760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vand", "VandQ", "SimdAluOp", unsignedTypes, 4, vandCode) 20767639Sgblack@eecs.umich.edu 20777639Sgblack@eecs.umich.edu vbicCode = ''' 20787639Sgblack@eecs.umich.edu destElem = srcElem1 & ~srcElem2; 20797639Sgblack@eecs.umich.edu ''' 20807760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vbic", "VbicD", "SimdAluOp", unsignedTypes, 2, vbicCode) 20817760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vbic", "VbicQ", "SimdAluOp", unsignedTypes, 4, vbicCode) 20827639Sgblack@eecs.umich.edu 20837639Sgblack@eecs.umich.edu vorrCode = ''' 20847639Sgblack@eecs.umich.edu destElem = srcElem1 | srcElem2; 20857639Sgblack@eecs.umich.edu ''' 20867760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vorr", "VorrD", "SimdAluOp", unsignedTypes, 2, vorrCode) 20877760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vorr", "VorrQ", "SimdAluOp", unsignedTypes, 4, vorrCode) 20887639Sgblack@eecs.umich.edu 20897760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vmov", "VmovD", "SimdMiscOp", unsignedTypes, 2, vorrCode) 20907760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vmov", "VmovQ", "SimdMiscOp", unsignedTypes, 4, vorrCode) 20917639Sgblack@eecs.umich.edu 20927639Sgblack@eecs.umich.edu vornCode = ''' 20937639Sgblack@eecs.umich.edu destElem = srcElem1 | ~srcElem2; 20947639Sgblack@eecs.umich.edu ''' 20957760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vorn", "VornD", "SimdAluOp", unsignedTypes, 2, vornCode) 20967760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vorn", "VornQ", "SimdAluOp", unsignedTypes, 4, vornCode) 20977639Sgblack@eecs.umich.edu 20987639Sgblack@eecs.umich.edu veorCode = ''' 20997639Sgblack@eecs.umich.edu destElem = srcElem1 ^ srcElem2; 21007639Sgblack@eecs.umich.edu ''' 21017760SGiacomo.Gabrielli@arm.com threeEqualRegInst("veor", "VeorD", "SimdAluOp", unsignedTypes, 2, veorCode) 21027760SGiacomo.Gabrielli@arm.com threeEqualRegInst("veor", "VeorQ", "SimdAluOp", unsignedTypes, 4, veorCode) 21037639Sgblack@eecs.umich.edu 21047639Sgblack@eecs.umich.edu vbifCode = ''' 21057639Sgblack@eecs.umich.edu destElem = (destElem & srcElem2) | (srcElem1 & ~srcElem2); 21067639Sgblack@eecs.umich.edu ''' 21077760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vbif", "VbifD", "SimdAluOp", unsignedTypes, 2, vbifCode, True) 21087760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vbif", "VbifQ", "SimdAluOp", unsignedTypes, 4, vbifCode, True) 21097639Sgblack@eecs.umich.edu vbitCode = ''' 21107639Sgblack@eecs.umich.edu destElem = (srcElem1 & srcElem2) | (destElem & ~srcElem2); 21117639Sgblack@eecs.umich.edu ''' 21127760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vbit", "VbitD", "SimdAluOp", unsignedTypes, 2, vbitCode, True) 21137760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vbit", "VbitQ", "SimdAluOp", unsignedTypes, 4, vbitCode, True) 21147639Sgblack@eecs.umich.edu vbslCode = ''' 21157639Sgblack@eecs.umich.edu destElem = (srcElem1 & destElem) | (srcElem2 & ~destElem); 21167639Sgblack@eecs.umich.edu ''' 21177760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vbsl", "VbslD", "SimdAluOp", unsignedTypes, 2, vbslCode, True) 21187760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vbsl", "VbslQ", "SimdAluOp", unsignedTypes, 4, vbslCode, True) 21197639Sgblack@eecs.umich.edu 21207639Sgblack@eecs.umich.edu vmaxCode = ''' 21217639Sgblack@eecs.umich.edu destElem = (srcElem1 > srcElem2) ? srcElem1 : srcElem2; 21227639Sgblack@eecs.umich.edu ''' 21237760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vmax", "VmaxD", "SimdCmpOp", allTypes, 2, vmaxCode) 21247760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vmax", "VmaxQ", "SimdCmpOp", allTypes, 4, vmaxCode) 21257639Sgblack@eecs.umich.edu 21267639Sgblack@eecs.umich.edu vminCode = ''' 21277639Sgblack@eecs.umich.edu destElem = (srcElem1 < srcElem2) ? srcElem1 : srcElem2; 21287639Sgblack@eecs.umich.edu ''' 21297760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vmin", "VminD", "SimdCmpOp", allTypes, 2, vminCode) 21307760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vmin", "VminQ", "SimdCmpOp", allTypes, 4, vminCode) 21317639Sgblack@eecs.umich.edu 21327639Sgblack@eecs.umich.edu vaddCode = ''' 21337639Sgblack@eecs.umich.edu destElem = srcElem1 + srcElem2; 21347639Sgblack@eecs.umich.edu ''' 21357760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vadd", "NVaddD", "SimdAddOp", unsignedTypes, 2, vaddCode) 21367760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vadd", "NVaddQ", "SimdAddOp", unsignedTypes, 4, vaddCode) 21377639Sgblack@eecs.umich.edu 21388607Sgblack@eecs.umich.edu threeEqualRegInst("vpadd", "NVpaddD", "SimdAddOp", smallUnsignedTypes, 21397639Sgblack@eecs.umich.edu 2, vaddCode, pairwise=True) 21407639Sgblack@eecs.umich.edu vaddlwCode = ''' 21417639Sgblack@eecs.umich.edu destElem = (BigElement)srcElem1 + (BigElement)srcElem2; 21427639Sgblack@eecs.umich.edu ''' 21437760SGiacomo.Gabrielli@arm.com threeRegLongInst("vaddl", "Vaddl", "SimdAddOp", smallTypes, vaddlwCode) 21447760SGiacomo.Gabrielli@arm.com threeRegWideInst("vaddw", "Vaddw", "SimdAddOp", smallTypes, vaddlwCode) 21457639Sgblack@eecs.umich.edu vaddhnCode = ''' 21467639Sgblack@eecs.umich.edu destElem = ((BigElement)srcElem1 + (BigElement)srcElem2) >> 21477639Sgblack@eecs.umich.edu (sizeof(Element) * 8); 21487639Sgblack@eecs.umich.edu ''' 21497760SGiacomo.Gabrielli@arm.com threeRegNarrowInst("vaddhn", "Vaddhn", "SimdAddOp", smallTypes, vaddhnCode) 21507639Sgblack@eecs.umich.edu vraddhnCode = ''' 21517639Sgblack@eecs.umich.edu destElem = ((BigElement)srcElem1 + (BigElement)srcElem2 + 21527639Sgblack@eecs.umich.edu ((BigElement)1 << (sizeof(Element) * 8 - 1))) >> 21537639Sgblack@eecs.umich.edu (sizeof(Element) * 8); 21547639Sgblack@eecs.umich.edu ''' 21557760SGiacomo.Gabrielli@arm.com threeRegNarrowInst("vraddhn", "Vraddhn", "SimdAddOp", smallTypes, vraddhnCode) 21567639Sgblack@eecs.umich.edu 21577639Sgblack@eecs.umich.edu vsubCode = ''' 21587639Sgblack@eecs.umich.edu destElem = srcElem1 - srcElem2; 21597639Sgblack@eecs.umich.edu ''' 21607760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vsub", "NVsubD", "SimdAddOp", unsignedTypes, 2, vsubCode) 21617760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vsub", "NVsubQ", "SimdAddOp", unsignedTypes, 4, vsubCode) 21627639Sgblack@eecs.umich.edu vsublwCode = ''' 21637639Sgblack@eecs.umich.edu destElem = (BigElement)srcElem1 - (BigElement)srcElem2; 21647639Sgblack@eecs.umich.edu ''' 21657760SGiacomo.Gabrielli@arm.com threeRegLongInst("vsubl", "Vsubl", "SimdAddOp", smallTypes, vsublwCode) 21667760SGiacomo.Gabrielli@arm.com threeRegWideInst("vsubw", "Vsubw", "SimdAddOp", smallTypes, vsublwCode) 21677639Sgblack@eecs.umich.edu 21687639Sgblack@eecs.umich.edu vqaddUCode = ''' 21697639Sgblack@eecs.umich.edu destElem = srcElem1 + srcElem2; 21707783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 21717639Sgblack@eecs.umich.edu if (destElem < srcElem1 || destElem < srcElem2) { 21727639Sgblack@eecs.umich.edu destElem = (Element)(-1); 21737639Sgblack@eecs.umich.edu fpscr.qc = 1; 21747639Sgblack@eecs.umich.edu } 21757783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 21767639Sgblack@eecs.umich.edu ''' 21777760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqadd", "VqaddUD", "SimdAddOp", unsignedTypes, 2, vqaddUCode) 21787760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqadd", "VqaddUQ", "SimdAddOp", unsignedTypes, 4, vqaddUCode) 21797639Sgblack@eecs.umich.edu vsubhnCode = ''' 21807639Sgblack@eecs.umich.edu destElem = ((BigElement)srcElem1 - (BigElement)srcElem2) >> 21817639Sgblack@eecs.umich.edu (sizeof(Element) * 8); 21827639Sgblack@eecs.umich.edu ''' 21837760SGiacomo.Gabrielli@arm.com threeRegNarrowInst("vsubhn", "Vsubhn", "SimdAddOp", smallTypes, vsubhnCode) 21847639Sgblack@eecs.umich.edu vrsubhnCode = ''' 21857639Sgblack@eecs.umich.edu destElem = ((BigElement)srcElem1 - (BigElement)srcElem2 + 21867639Sgblack@eecs.umich.edu ((BigElement)1 << (sizeof(Element) * 8 - 1))) >> 21877639Sgblack@eecs.umich.edu (sizeof(Element) * 8); 21887639Sgblack@eecs.umich.edu ''' 21897760SGiacomo.Gabrielli@arm.com threeRegNarrowInst("vrsubhn", "Vrsubhn", "SimdAddOp", smallTypes, vrsubhnCode) 21907639Sgblack@eecs.umich.edu 21917639Sgblack@eecs.umich.edu vqaddSCode = ''' 21927639Sgblack@eecs.umich.edu destElem = srcElem1 + srcElem2; 21937783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 21947639Sgblack@eecs.umich.edu bool negDest = (destElem < 0); 21957639Sgblack@eecs.umich.edu bool negSrc1 = (srcElem1 < 0); 21967639Sgblack@eecs.umich.edu bool negSrc2 = (srcElem2 < 0); 21977639Sgblack@eecs.umich.edu if ((negDest != negSrc1) && (negSrc1 == negSrc2)) { 21987639Sgblack@eecs.umich.edu if (negDest) 219912038Srekai.gonzalezalberquilla@arm.com /* If (>=0) plus (>=0) yields (<0), saturate to +. */ 220012038Srekai.gonzalezalberquilla@arm.com destElem = std::numeric_limits<Element>::max(); 220112038Srekai.gonzalezalberquilla@arm.com else 220212038Srekai.gonzalezalberquilla@arm.com /* If (<0) plus (<0) yields (>=0), saturate to -. */ 220312038Srekai.gonzalezalberquilla@arm.com destElem = std::numeric_limits<Element>::min(); 22047639Sgblack@eecs.umich.edu fpscr.qc = 1; 22057639Sgblack@eecs.umich.edu } 22067783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 22077639Sgblack@eecs.umich.edu ''' 22087760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqadd", "VqaddSD", "SimdAddOp", signedTypes, 2, vqaddSCode) 22097760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqadd", "VqaddSQ", "SimdAddOp", signedTypes, 4, vqaddSCode) 22107639Sgblack@eecs.umich.edu 22117639Sgblack@eecs.umich.edu vqsubUCode = ''' 22127639Sgblack@eecs.umich.edu destElem = srcElem1 - srcElem2; 22137783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 22147639Sgblack@eecs.umich.edu if (destElem > srcElem1) { 22157639Sgblack@eecs.umich.edu destElem = 0; 22167639Sgblack@eecs.umich.edu fpscr.qc = 1; 22177639Sgblack@eecs.umich.edu } 22187783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 22197639Sgblack@eecs.umich.edu ''' 22207760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqsub", "VqsubUD", "SimdAddOp", unsignedTypes, 2, vqsubUCode) 22217760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqsub", "VqsubUQ", "SimdAddOp", unsignedTypes, 4, vqsubUCode) 22227639Sgblack@eecs.umich.edu 22237639Sgblack@eecs.umich.edu vqsubSCode = ''' 22247639Sgblack@eecs.umich.edu destElem = srcElem1 - srcElem2; 22257783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 22267639Sgblack@eecs.umich.edu bool negDest = (destElem < 0); 22277639Sgblack@eecs.umich.edu bool negSrc1 = (srcElem1 < 0); 22287639Sgblack@eecs.umich.edu bool posSrc2 = (srcElem2 >= 0); 22297639Sgblack@eecs.umich.edu if ((negDest != negSrc1) && (negSrc1 == posSrc2)) { 22307639Sgblack@eecs.umich.edu if (negDest) 223112038Srekai.gonzalezalberquilla@arm.com /* If (>=0) minus (<0) yields (<0), saturate to +. */ 223212038Srekai.gonzalezalberquilla@arm.com destElem = std::numeric_limits<Element>::max(); 223312038Srekai.gonzalezalberquilla@arm.com else 223412038Srekai.gonzalezalberquilla@arm.com /* If (<0) minus (>=0) yields (>=0), saturate to -. */ 223512038Srekai.gonzalezalberquilla@arm.com destElem = std::numeric_limits<Element>::min(); 22367639Sgblack@eecs.umich.edu fpscr.qc = 1; 22377639Sgblack@eecs.umich.edu } 22387783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 22397639Sgblack@eecs.umich.edu ''' 22407760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqsub", "VqsubSD", "SimdAddOp", signedTypes, 2, vqsubSCode) 22417760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqsub", "VqsubSQ", "SimdAddOp", signedTypes, 4, vqsubSCode) 22427639Sgblack@eecs.umich.edu 22437639Sgblack@eecs.umich.edu vcgtCode = ''' 22447639Sgblack@eecs.umich.edu destElem = (srcElem1 > srcElem2) ? (Element)(-1) : 0; 22457639Sgblack@eecs.umich.edu ''' 22467760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vcgt", "VcgtD", "SimdCmpOp", allTypes, 2, vcgtCode) 22477760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vcgt", "VcgtQ", "SimdCmpOp", allTypes, 4, vcgtCode) 22487639Sgblack@eecs.umich.edu 22497639Sgblack@eecs.umich.edu vcgeCode = ''' 22507639Sgblack@eecs.umich.edu destElem = (srcElem1 >= srcElem2) ? (Element)(-1) : 0; 22517639Sgblack@eecs.umich.edu ''' 22527760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vcge", "VcgeD", "SimdCmpOp", allTypes, 2, vcgeCode) 22537760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vcge", "VcgeQ", "SimdCmpOp", allTypes, 4, vcgeCode) 22547639Sgblack@eecs.umich.edu 22557639Sgblack@eecs.umich.edu vceqCode = ''' 22567639Sgblack@eecs.umich.edu destElem = (srcElem1 == srcElem2) ? (Element)(-1) : 0; 22577639Sgblack@eecs.umich.edu ''' 22587760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vceq", "VceqD", "SimdCmpOp", unsignedTypes, 2, vceqCode) 22597760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vceq", "VceqQ", "SimdCmpOp", unsignedTypes, 4, vceqCode) 22607639Sgblack@eecs.umich.edu 22617639Sgblack@eecs.umich.edu vshlCode = ''' 22627639Sgblack@eecs.umich.edu int16_t shiftAmt = (int8_t)srcElem2; 22637639Sgblack@eecs.umich.edu if (shiftAmt < 0) { 22647639Sgblack@eecs.umich.edu shiftAmt = -shiftAmt; 22657639Sgblack@eecs.umich.edu if (shiftAmt >= sizeof(Element) * 8) { 22667639Sgblack@eecs.umich.edu shiftAmt = sizeof(Element) * 8 - 1; 22677639Sgblack@eecs.umich.edu destElem = 0; 22687639Sgblack@eecs.umich.edu } else { 22697639Sgblack@eecs.umich.edu destElem = (srcElem1 >> shiftAmt); 22707639Sgblack@eecs.umich.edu } 22717639Sgblack@eecs.umich.edu // Make sure the right shift sign extended when it should. 22727641Sgblack@eecs.umich.edu if (ltz(srcElem1) && !ltz(destElem)) { 22737639Sgblack@eecs.umich.edu destElem |= -((Element)1 << (sizeof(Element) * 8 - 22747639Sgblack@eecs.umich.edu 1 - shiftAmt)); 22757639Sgblack@eecs.umich.edu } 22767639Sgblack@eecs.umich.edu } else { 22777639Sgblack@eecs.umich.edu if (shiftAmt >= sizeof(Element) * 8) { 22787639Sgblack@eecs.umich.edu destElem = 0; 22797639Sgblack@eecs.umich.edu } else { 22807639Sgblack@eecs.umich.edu destElem = srcElem1 << shiftAmt; 22817639Sgblack@eecs.umich.edu } 22827639Sgblack@eecs.umich.edu } 22837639Sgblack@eecs.umich.edu ''' 22848206SWilliam.Wang@arm.com threeEqualRegInst("vshl", "VshlD", "SimdShiftOp", allTypes, 2, vshlCode) 22858206SWilliam.Wang@arm.com threeEqualRegInst("vshl", "VshlQ", "SimdShiftOp", allTypes, 4, vshlCode) 22867639Sgblack@eecs.umich.edu 22877639Sgblack@eecs.umich.edu vrshlCode = ''' 22887639Sgblack@eecs.umich.edu int16_t shiftAmt = (int8_t)srcElem2; 22897639Sgblack@eecs.umich.edu if (shiftAmt < 0) { 22907639Sgblack@eecs.umich.edu shiftAmt = -shiftAmt; 22917639Sgblack@eecs.umich.edu Element rBit = 0; 22927639Sgblack@eecs.umich.edu if (shiftAmt <= sizeof(Element) * 8) 22937639Sgblack@eecs.umich.edu rBit = bits(srcElem1, shiftAmt - 1); 22947641Sgblack@eecs.umich.edu if (shiftAmt > sizeof(Element) * 8 && ltz(srcElem1)) 22957639Sgblack@eecs.umich.edu rBit = 1; 22967639Sgblack@eecs.umich.edu if (shiftAmt >= sizeof(Element) * 8) { 22977639Sgblack@eecs.umich.edu shiftAmt = sizeof(Element) * 8 - 1; 22987639Sgblack@eecs.umich.edu destElem = 0; 22997639Sgblack@eecs.umich.edu } else { 23007639Sgblack@eecs.umich.edu destElem = (srcElem1 >> shiftAmt); 23017639Sgblack@eecs.umich.edu } 23027639Sgblack@eecs.umich.edu // Make sure the right shift sign extended when it should. 23037641Sgblack@eecs.umich.edu if (ltz(srcElem1) && !ltz(destElem)) { 23047639Sgblack@eecs.umich.edu destElem |= -((Element)1 << (sizeof(Element) * 8 - 23057639Sgblack@eecs.umich.edu 1 - shiftAmt)); 23067639Sgblack@eecs.umich.edu } 23077639Sgblack@eecs.umich.edu destElem += rBit; 23087639Sgblack@eecs.umich.edu } else if (shiftAmt > 0) { 23097639Sgblack@eecs.umich.edu if (shiftAmt >= sizeof(Element) * 8) { 23107639Sgblack@eecs.umich.edu destElem = 0; 23117639Sgblack@eecs.umich.edu } else { 23127639Sgblack@eecs.umich.edu destElem = srcElem1 << shiftAmt; 23137639Sgblack@eecs.umich.edu } 23147639Sgblack@eecs.umich.edu } else { 23157639Sgblack@eecs.umich.edu destElem = srcElem1; 23167639Sgblack@eecs.umich.edu } 23177639Sgblack@eecs.umich.edu ''' 23187760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vrshl", "VrshlD", "SimdAluOp", allTypes, 2, vrshlCode) 23197760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vrshl", "VrshlQ", "SimdAluOp", allTypes, 4, vrshlCode) 23207639Sgblack@eecs.umich.edu 23217639Sgblack@eecs.umich.edu vqshlUCode = ''' 23227639Sgblack@eecs.umich.edu int16_t shiftAmt = (int8_t)srcElem2; 23237783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 23247639Sgblack@eecs.umich.edu if (shiftAmt < 0) { 23257639Sgblack@eecs.umich.edu shiftAmt = -shiftAmt; 23267639Sgblack@eecs.umich.edu if (shiftAmt >= sizeof(Element) * 8) { 23277639Sgblack@eecs.umich.edu shiftAmt = sizeof(Element) * 8 - 1; 23287639Sgblack@eecs.umich.edu destElem = 0; 23297639Sgblack@eecs.umich.edu } else { 23307639Sgblack@eecs.umich.edu destElem = (srcElem1 >> shiftAmt); 23317639Sgblack@eecs.umich.edu } 23327639Sgblack@eecs.umich.edu } else if (shiftAmt > 0) { 23337639Sgblack@eecs.umich.edu if (shiftAmt >= sizeof(Element) * 8) { 23347639Sgblack@eecs.umich.edu if (srcElem1 != 0) { 23357639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8); 23367639Sgblack@eecs.umich.edu fpscr.qc = 1; 23377639Sgblack@eecs.umich.edu } else { 23387639Sgblack@eecs.umich.edu destElem = 0; 23397639Sgblack@eecs.umich.edu } 23407639Sgblack@eecs.umich.edu } else { 23417639Sgblack@eecs.umich.edu if (bits(srcElem1, sizeof(Element) * 8 - 1, 23427639Sgblack@eecs.umich.edu sizeof(Element) * 8 - shiftAmt)) { 23437639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8); 23447639Sgblack@eecs.umich.edu fpscr.qc = 1; 23457639Sgblack@eecs.umich.edu } else { 23467639Sgblack@eecs.umich.edu destElem = srcElem1 << shiftAmt; 23477639Sgblack@eecs.umich.edu } 23487639Sgblack@eecs.umich.edu } 23497639Sgblack@eecs.umich.edu } else { 23507639Sgblack@eecs.umich.edu destElem = srcElem1; 23517639Sgblack@eecs.umich.edu } 23527783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 23537639Sgblack@eecs.umich.edu ''' 23547760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqshl", "VqshlUD", "SimdAluOp", unsignedTypes, 2, vqshlUCode) 23557760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqshl", "VqshlUQ", "SimdAluOp", unsignedTypes, 4, vqshlUCode) 23567639Sgblack@eecs.umich.edu 23577639Sgblack@eecs.umich.edu vqshlSCode = ''' 23587639Sgblack@eecs.umich.edu int16_t shiftAmt = (int8_t)srcElem2; 23597783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 23607639Sgblack@eecs.umich.edu if (shiftAmt < 0) { 23617639Sgblack@eecs.umich.edu shiftAmt = -shiftAmt; 23627639Sgblack@eecs.umich.edu if (shiftAmt >= sizeof(Element) * 8) { 23637639Sgblack@eecs.umich.edu shiftAmt = sizeof(Element) * 8 - 1; 23647639Sgblack@eecs.umich.edu destElem = 0; 23657639Sgblack@eecs.umich.edu } else { 23667639Sgblack@eecs.umich.edu destElem = (srcElem1 >> shiftAmt); 23677639Sgblack@eecs.umich.edu } 23687639Sgblack@eecs.umich.edu // Make sure the right shift sign extended when it should. 23697639Sgblack@eecs.umich.edu if (srcElem1 < 0 && destElem >= 0) { 23707639Sgblack@eecs.umich.edu destElem |= -((Element)1 << (sizeof(Element) * 8 - 23717639Sgblack@eecs.umich.edu 1 - shiftAmt)); 23727639Sgblack@eecs.umich.edu } 23737639Sgblack@eecs.umich.edu } else if (shiftAmt > 0) { 23747639Sgblack@eecs.umich.edu bool sat = false; 23757639Sgblack@eecs.umich.edu if (shiftAmt >= sizeof(Element) * 8) { 23767639Sgblack@eecs.umich.edu if (srcElem1 != 0) 23777639Sgblack@eecs.umich.edu sat = true; 23787639Sgblack@eecs.umich.edu else 23797639Sgblack@eecs.umich.edu destElem = 0; 23807639Sgblack@eecs.umich.edu } else { 23817639Sgblack@eecs.umich.edu if (bits(srcElem1, sizeof(Element) * 8 - 1, 23827639Sgblack@eecs.umich.edu sizeof(Element) * 8 - 1 - shiftAmt) != 23837639Sgblack@eecs.umich.edu ((srcElem1 < 0) ? mask(shiftAmt + 1) : 0)) { 23847639Sgblack@eecs.umich.edu sat = true; 23857639Sgblack@eecs.umich.edu } else { 23867639Sgblack@eecs.umich.edu destElem = srcElem1 << shiftAmt; 23877639Sgblack@eecs.umich.edu } 23887639Sgblack@eecs.umich.edu } 23897639Sgblack@eecs.umich.edu if (sat) { 23907639Sgblack@eecs.umich.edu fpscr.qc = 1; 23917639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8 - 1); 23927639Sgblack@eecs.umich.edu if (srcElem1 < 0) 23937639Sgblack@eecs.umich.edu destElem = ~destElem; 23947639Sgblack@eecs.umich.edu } 23957639Sgblack@eecs.umich.edu } else { 23967639Sgblack@eecs.umich.edu destElem = srcElem1; 23977639Sgblack@eecs.umich.edu } 23987783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 23997639Sgblack@eecs.umich.edu ''' 24007760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqshl", "VqshlSD", "SimdCmpOp", signedTypes, 2, vqshlSCode) 24017760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqshl", "VqshlSQ", "SimdCmpOp", signedTypes, 4, vqshlSCode) 24027639Sgblack@eecs.umich.edu 24037639Sgblack@eecs.umich.edu vqrshlUCode = ''' 24047639Sgblack@eecs.umich.edu int16_t shiftAmt = (int8_t)srcElem2; 24057783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 24067639Sgblack@eecs.umich.edu if (shiftAmt < 0) { 24077639Sgblack@eecs.umich.edu shiftAmt = -shiftAmt; 24087639Sgblack@eecs.umich.edu Element rBit = 0; 24097639Sgblack@eecs.umich.edu if (shiftAmt <= sizeof(Element) * 8) 24107639Sgblack@eecs.umich.edu rBit = bits(srcElem1, shiftAmt - 1); 24117639Sgblack@eecs.umich.edu if (shiftAmt >= sizeof(Element) * 8) { 24127639Sgblack@eecs.umich.edu shiftAmt = sizeof(Element) * 8 - 1; 24137639Sgblack@eecs.umich.edu destElem = 0; 24147639Sgblack@eecs.umich.edu } else { 24157639Sgblack@eecs.umich.edu destElem = (srcElem1 >> shiftAmt); 24167639Sgblack@eecs.umich.edu } 24177639Sgblack@eecs.umich.edu destElem += rBit; 24187639Sgblack@eecs.umich.edu } else { 24197639Sgblack@eecs.umich.edu if (shiftAmt >= sizeof(Element) * 8) { 24207639Sgblack@eecs.umich.edu if (srcElem1 != 0) { 24217639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8); 24227639Sgblack@eecs.umich.edu fpscr.qc = 1; 24237639Sgblack@eecs.umich.edu } else { 24247639Sgblack@eecs.umich.edu destElem = 0; 24257639Sgblack@eecs.umich.edu } 24267639Sgblack@eecs.umich.edu } else { 24277639Sgblack@eecs.umich.edu if (bits(srcElem1, sizeof(Element) * 8 - 1, 24287639Sgblack@eecs.umich.edu sizeof(Element) * 8 - shiftAmt)) { 24297639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8); 24307639Sgblack@eecs.umich.edu fpscr.qc = 1; 24317639Sgblack@eecs.umich.edu } else { 24327639Sgblack@eecs.umich.edu destElem = srcElem1 << shiftAmt; 24337639Sgblack@eecs.umich.edu } 24347639Sgblack@eecs.umich.edu } 24357639Sgblack@eecs.umich.edu } 24367783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 24377639Sgblack@eecs.umich.edu ''' 24387760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqrshl", "VqrshlUD", "SimdCmpOp", unsignedTypes, 2, vqrshlUCode) 24397760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqrshl", "VqrshlUQ", "SimdCmpOp", unsignedTypes, 4, vqrshlUCode) 24407639Sgblack@eecs.umich.edu 24417639Sgblack@eecs.umich.edu vqrshlSCode = ''' 24427639Sgblack@eecs.umich.edu int16_t shiftAmt = (int8_t)srcElem2; 24437783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 24447639Sgblack@eecs.umich.edu if (shiftAmt < 0) { 24457639Sgblack@eecs.umich.edu shiftAmt = -shiftAmt; 24467639Sgblack@eecs.umich.edu Element rBit = 0; 24477639Sgblack@eecs.umich.edu if (shiftAmt <= sizeof(Element) * 8) 24487639Sgblack@eecs.umich.edu rBit = bits(srcElem1, shiftAmt - 1); 24497639Sgblack@eecs.umich.edu if (shiftAmt > sizeof(Element) * 8 && srcElem1 < 0) 24507639Sgblack@eecs.umich.edu rBit = 1; 24517639Sgblack@eecs.umich.edu if (shiftAmt >= sizeof(Element) * 8) { 24527639Sgblack@eecs.umich.edu shiftAmt = sizeof(Element) * 8 - 1; 24537639Sgblack@eecs.umich.edu destElem = 0; 24547639Sgblack@eecs.umich.edu } else { 24557639Sgblack@eecs.umich.edu destElem = (srcElem1 >> shiftAmt); 24567639Sgblack@eecs.umich.edu } 24577639Sgblack@eecs.umich.edu // Make sure the right shift sign extended when it should. 24587639Sgblack@eecs.umich.edu if (srcElem1 < 0 && destElem >= 0) { 24597639Sgblack@eecs.umich.edu destElem |= -((Element)1 << (sizeof(Element) * 8 - 24607639Sgblack@eecs.umich.edu 1 - shiftAmt)); 24617639Sgblack@eecs.umich.edu } 24627639Sgblack@eecs.umich.edu destElem += rBit; 24637639Sgblack@eecs.umich.edu } else if (shiftAmt > 0) { 24647639Sgblack@eecs.umich.edu bool sat = false; 24657639Sgblack@eecs.umich.edu if (shiftAmt >= sizeof(Element) * 8) { 24667639Sgblack@eecs.umich.edu if (srcElem1 != 0) 24677639Sgblack@eecs.umich.edu sat = true; 24687639Sgblack@eecs.umich.edu else 24697639Sgblack@eecs.umich.edu destElem = 0; 24707639Sgblack@eecs.umich.edu } else { 24717639Sgblack@eecs.umich.edu if (bits(srcElem1, sizeof(Element) * 8 - 1, 24727639Sgblack@eecs.umich.edu sizeof(Element) * 8 - 1 - shiftAmt) != 24737639Sgblack@eecs.umich.edu ((srcElem1 < 0) ? mask(shiftAmt + 1) : 0)) { 24747639Sgblack@eecs.umich.edu sat = true; 24757639Sgblack@eecs.umich.edu } else { 24767639Sgblack@eecs.umich.edu destElem = srcElem1 << shiftAmt; 24777639Sgblack@eecs.umich.edu } 24787639Sgblack@eecs.umich.edu } 24797639Sgblack@eecs.umich.edu if (sat) { 24807639Sgblack@eecs.umich.edu fpscr.qc = 1; 24817639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8 - 1); 24827639Sgblack@eecs.umich.edu if (srcElem1 < 0) 24837639Sgblack@eecs.umich.edu destElem = ~destElem; 24847639Sgblack@eecs.umich.edu } 24857639Sgblack@eecs.umich.edu } else { 24867639Sgblack@eecs.umich.edu destElem = srcElem1; 24877639Sgblack@eecs.umich.edu } 24887783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 24897639Sgblack@eecs.umich.edu ''' 24907760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqrshl", "VqrshlSD", "SimdCmpOp", signedTypes, 2, vqrshlSCode) 24917760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqrshl", "VqrshlSQ", "SimdCmpOp", signedTypes, 4, vqrshlSCode) 24927639Sgblack@eecs.umich.edu 24937639Sgblack@eecs.umich.edu vabaCode = ''' 24947639Sgblack@eecs.umich.edu destElem += (srcElem1 > srcElem2) ? (srcElem1 - srcElem2) : 24957639Sgblack@eecs.umich.edu (srcElem2 - srcElem1); 24967639Sgblack@eecs.umich.edu ''' 24977760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vaba", "VabaD", "SimdAddAccOp", allTypes, 2, vabaCode, True) 24987760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vaba", "VabaQ", "SimdAddAccOp", allTypes, 4, vabaCode, True) 24997639Sgblack@eecs.umich.edu vabalCode = ''' 25007639Sgblack@eecs.umich.edu destElem += (srcElem1 > srcElem2) ? 25017639Sgblack@eecs.umich.edu ((BigElement)srcElem1 - (BigElement)srcElem2) : 25027639Sgblack@eecs.umich.edu ((BigElement)srcElem2 - (BigElement)srcElem1); 25037639Sgblack@eecs.umich.edu ''' 25047760SGiacomo.Gabrielli@arm.com threeRegLongInst("vabal", "Vabal", "SimdAddAccOp", smallTypes, vabalCode, True) 25057639Sgblack@eecs.umich.edu 25067639Sgblack@eecs.umich.edu vabdCode = ''' 25077639Sgblack@eecs.umich.edu destElem = (srcElem1 > srcElem2) ? (srcElem1 - srcElem2) : 25087639Sgblack@eecs.umich.edu (srcElem2 - srcElem1); 25097639Sgblack@eecs.umich.edu ''' 25107760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vabd", "VabdD", "SimdAddOp", allTypes, 2, vabdCode) 25117760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vabd", "VabdQ", "SimdAddOp", allTypes, 4, vabdCode) 25127639Sgblack@eecs.umich.edu vabdlCode = ''' 25137639Sgblack@eecs.umich.edu destElem = (srcElem1 > srcElem2) ? 25147639Sgblack@eecs.umich.edu ((BigElement)srcElem1 - (BigElement)srcElem2) : 25157639Sgblack@eecs.umich.edu ((BigElement)srcElem2 - (BigElement)srcElem1); 25167639Sgblack@eecs.umich.edu ''' 25177760SGiacomo.Gabrielli@arm.com threeRegLongInst("vabdl", "Vabdl", "SimdAddOp", smallTypes, vabdlCode) 25187639Sgblack@eecs.umich.edu 25197639Sgblack@eecs.umich.edu vtstCode = ''' 25207639Sgblack@eecs.umich.edu destElem = (srcElem1 & srcElem2) ? (Element)(-1) : 0; 25217639Sgblack@eecs.umich.edu ''' 25227760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vtst", "VtstD", "SimdAluOp", unsignedTypes, 2, vtstCode) 25237760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vtst", "VtstQ", "SimdAluOp", unsignedTypes, 4, vtstCode) 25247639Sgblack@eecs.umich.edu 25257639Sgblack@eecs.umich.edu vmulCode = ''' 25267639Sgblack@eecs.umich.edu destElem = srcElem1 * srcElem2; 25277639Sgblack@eecs.umich.edu ''' 25287760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vmul", "NVmulD", "SimdMultOp", allTypes, 2, vmulCode) 25297760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vmul", "NVmulQ", "SimdMultOp", allTypes, 4, vmulCode) 25307639Sgblack@eecs.umich.edu vmullCode = ''' 25317639Sgblack@eecs.umich.edu destElem = (BigElement)srcElem1 * (BigElement)srcElem2; 25327639Sgblack@eecs.umich.edu ''' 25337760SGiacomo.Gabrielli@arm.com threeRegLongInst("vmull", "Vmull", "SimdMultOp", smallTypes, vmullCode) 25347639Sgblack@eecs.umich.edu 25357639Sgblack@eecs.umich.edu vmlaCode = ''' 25367639Sgblack@eecs.umich.edu destElem = destElem + srcElem1 * srcElem2; 25377639Sgblack@eecs.umich.edu ''' 25387760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vmla", "NVmlaD", "SimdMultAccOp", allTypes, 2, vmlaCode, True) 25397760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vmla", "NVmlaQ", "SimdMultAccOp", allTypes, 4, vmlaCode, True) 25407639Sgblack@eecs.umich.edu vmlalCode = ''' 25417639Sgblack@eecs.umich.edu destElem = destElem + (BigElement)srcElem1 * (BigElement)srcElem2; 25427639Sgblack@eecs.umich.edu ''' 25437760SGiacomo.Gabrielli@arm.com threeRegLongInst("vmlal", "Vmlal", "SimdMultAccOp", smallTypes, vmlalCode, True) 25447639Sgblack@eecs.umich.edu 25457639Sgblack@eecs.umich.edu vqdmlalCode = ''' 25467783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 25477639Sgblack@eecs.umich.edu BigElement midElem = (2 * (int64_t)srcElem1 * (int64_t)srcElem2); 254812038Srekai.gonzalezalberquilla@arm.com Element maxNeg = std::numeric_limits<Element>::min(); 25497639Sgblack@eecs.umich.edu Element halfNeg = maxNeg / 2; 25507639Sgblack@eecs.umich.edu if ((srcElem1 == maxNeg && srcElem2 == maxNeg) || 25517639Sgblack@eecs.umich.edu (srcElem1 == halfNeg && srcElem2 == maxNeg) || 25527639Sgblack@eecs.umich.edu (srcElem1 == maxNeg && srcElem2 == halfNeg)) { 25537639Sgblack@eecs.umich.edu midElem = ~((BigElement)maxNeg << (sizeof(Element) * 8)); 25547639Sgblack@eecs.umich.edu fpscr.qc = 1; 25557639Sgblack@eecs.umich.edu } 25567641Sgblack@eecs.umich.edu bool negPreDest = ltz(destElem); 25577639Sgblack@eecs.umich.edu destElem += midElem; 25587641Sgblack@eecs.umich.edu bool negDest = ltz(destElem); 25597641Sgblack@eecs.umich.edu bool negMid = ltz(midElem); 25607639Sgblack@eecs.umich.edu if (negPreDest == negMid && negMid != negDest) { 25617639Sgblack@eecs.umich.edu destElem = mask(sizeof(BigElement) * 8 - 1); 25627639Sgblack@eecs.umich.edu if (negPreDest) 25637639Sgblack@eecs.umich.edu destElem = ~destElem; 25647639Sgblack@eecs.umich.edu fpscr.qc = 1; 25657639Sgblack@eecs.umich.edu } 25667783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 25677639Sgblack@eecs.umich.edu ''' 25687760SGiacomo.Gabrielli@arm.com threeRegLongInst("vqdmlal", "Vqdmlal", "SimdMultAccOp", smallTypes, vqdmlalCode, True) 25697639Sgblack@eecs.umich.edu 25707639Sgblack@eecs.umich.edu vqdmlslCode = ''' 25717783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 25727639Sgblack@eecs.umich.edu BigElement midElem = (2 * (int64_t)srcElem1 * (int64_t)srcElem2); 257312038Srekai.gonzalezalberquilla@arm.com Element maxNeg = std::numeric_limits<Element>::min(); 25747639Sgblack@eecs.umich.edu Element halfNeg = maxNeg / 2; 25757639Sgblack@eecs.umich.edu if ((srcElem1 == maxNeg && srcElem2 == maxNeg) || 25767639Sgblack@eecs.umich.edu (srcElem1 == halfNeg && srcElem2 == maxNeg) || 25777639Sgblack@eecs.umich.edu (srcElem1 == maxNeg && srcElem2 == halfNeg)) { 25787639Sgblack@eecs.umich.edu midElem = ~((BigElement)maxNeg << (sizeof(Element) * 8)); 25797639Sgblack@eecs.umich.edu fpscr.qc = 1; 25807639Sgblack@eecs.umich.edu } 25817641Sgblack@eecs.umich.edu bool negPreDest = ltz(destElem); 25827639Sgblack@eecs.umich.edu destElem -= midElem; 25837641Sgblack@eecs.umich.edu bool negDest = ltz(destElem); 25847641Sgblack@eecs.umich.edu bool posMid = ltz((BigElement)-midElem); 25857639Sgblack@eecs.umich.edu if (negPreDest == posMid && posMid != negDest) { 25867639Sgblack@eecs.umich.edu destElem = mask(sizeof(BigElement) * 8 - 1); 25877639Sgblack@eecs.umich.edu if (negPreDest) 25887639Sgblack@eecs.umich.edu destElem = ~destElem; 25897639Sgblack@eecs.umich.edu fpscr.qc = 1; 25907639Sgblack@eecs.umich.edu } 25917783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 25927639Sgblack@eecs.umich.edu ''' 25937760SGiacomo.Gabrielli@arm.com threeRegLongInst("vqdmlsl", "Vqdmlsl", "SimdMultAccOp", smallTypes, vqdmlslCode, True) 25947639Sgblack@eecs.umich.edu 25957639Sgblack@eecs.umich.edu vqdmullCode = ''' 25967783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 25977639Sgblack@eecs.umich.edu destElem = (2 * (int64_t)srcElem1 * (int64_t)srcElem2); 25987639Sgblack@eecs.umich.edu if (srcElem1 == srcElem2 && 259912038Srekai.gonzalezalberquilla@arm.com srcElem1 == (Element)(std::numeric_limits<Element>::min())) { 26007639Sgblack@eecs.umich.edu destElem = ~((BigElement)srcElem1 << (sizeof(Element) * 8)); 26017639Sgblack@eecs.umich.edu fpscr.qc = 1; 26027639Sgblack@eecs.umich.edu } 26037783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 26047639Sgblack@eecs.umich.edu ''' 26057760SGiacomo.Gabrielli@arm.com threeRegLongInst("vqdmull", "Vqdmull", "SimdMultAccOp", smallTypes, vqdmullCode) 26067639Sgblack@eecs.umich.edu 26077639Sgblack@eecs.umich.edu vmlsCode = ''' 26087639Sgblack@eecs.umich.edu destElem = destElem - srcElem1 * srcElem2; 26097639Sgblack@eecs.umich.edu ''' 26107760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vmls", "NVmlsD", "SimdMultAccOp", allTypes, 2, vmlsCode, True) 26117760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vmls", "NVmlsQ", "SimdMultAccOp", allTypes, 4, vmlsCode, True) 26127639Sgblack@eecs.umich.edu vmlslCode = ''' 26137639Sgblack@eecs.umich.edu destElem = destElem - (BigElement)srcElem1 * (BigElement)srcElem2; 26147639Sgblack@eecs.umich.edu ''' 26157760SGiacomo.Gabrielli@arm.com threeRegLongInst("vmlsl", "Vmlsl", "SimdMultAccOp", smallTypes, vmlslCode, True) 26167639Sgblack@eecs.umich.edu 26177639Sgblack@eecs.umich.edu vmulpCode = ''' 26187639Sgblack@eecs.umich.edu destElem = 0; 26197639Sgblack@eecs.umich.edu for (unsigned j = 0; j < sizeof(Element) * 8; j++) { 26207639Sgblack@eecs.umich.edu if (bits(srcElem2, j)) 26217639Sgblack@eecs.umich.edu destElem ^= srcElem1 << j; 26227639Sgblack@eecs.umich.edu } 26237639Sgblack@eecs.umich.edu ''' 26247760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vmul", "NVmulpD", "SimdMultOp", unsignedTypes, 2, vmulpCode) 26257760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vmul", "NVmulpQ", "SimdMultOp", unsignedTypes, 4, vmulpCode) 26267639Sgblack@eecs.umich.edu vmullpCode = ''' 26277639Sgblack@eecs.umich.edu destElem = 0; 26287639Sgblack@eecs.umich.edu for (unsigned j = 0; j < sizeof(Element) * 8; j++) { 26297639Sgblack@eecs.umich.edu if (bits(srcElem2, j)) 26307639Sgblack@eecs.umich.edu destElem ^= (BigElement)srcElem1 << j; 26317639Sgblack@eecs.umich.edu } 26327639Sgblack@eecs.umich.edu ''' 26337760SGiacomo.Gabrielli@arm.com threeRegLongInst("vmull", "Vmullp", "SimdMultOp", smallUnsignedTypes, vmullpCode) 26347639Sgblack@eecs.umich.edu 26358607Sgblack@eecs.umich.edu threeEqualRegInst("vpmax", "VpmaxD", "SimdCmpOp", smallTypes, 2, vmaxCode, pairwise=True) 26367639Sgblack@eecs.umich.edu 26378607Sgblack@eecs.umich.edu threeEqualRegInst("vpmin", "VpminD", "SimdCmpOp", smallTypes, 2, vminCode, pairwise=True) 26387639Sgblack@eecs.umich.edu 26397639Sgblack@eecs.umich.edu vqdmulhCode = ''' 26407783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 26417639Sgblack@eecs.umich.edu destElem = (2 * (int64_t)srcElem1 * (int64_t)srcElem2) >> 26427639Sgblack@eecs.umich.edu (sizeof(Element) * 8); 26437639Sgblack@eecs.umich.edu if (srcElem1 == srcElem2 && 264412038Srekai.gonzalezalberquilla@arm.com srcElem1 == (Element)(std::numeric_limits<Element>::min())) { 26457639Sgblack@eecs.umich.edu destElem = ~srcElem1; 26467639Sgblack@eecs.umich.edu fpscr.qc = 1; 26477639Sgblack@eecs.umich.edu } 26487783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 26497639Sgblack@eecs.umich.edu ''' 26507760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqdmulh", "VqdmulhD", "SimdMultOp", smallSignedTypes, 2, vqdmulhCode) 26517760SGiacomo.Gabrielli@arm.com threeEqualRegInst("vqdmulh", "VqdmulhQ", "SimdMultOp", smallSignedTypes, 4, vqdmulhCode) 26527639Sgblack@eecs.umich.edu 26537639Sgblack@eecs.umich.edu vqrdmulhCode = ''' 26547783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 26557639Sgblack@eecs.umich.edu destElem = (2 * (int64_t)srcElem1 * (int64_t)srcElem2 + 26567639Sgblack@eecs.umich.edu ((int64_t)1 << (sizeof(Element) * 8 - 1))) >> 26577639Sgblack@eecs.umich.edu (sizeof(Element) * 8); 265812038Srekai.gonzalezalberquilla@arm.com Element maxNeg = std::numeric_limits<Element>::min(); 26597639Sgblack@eecs.umich.edu Element halfNeg = maxNeg / 2; 26607639Sgblack@eecs.umich.edu if ((srcElem1 == maxNeg && srcElem2 == maxNeg) || 26617639Sgblack@eecs.umich.edu (srcElem1 == halfNeg && srcElem2 == maxNeg) || 26627639Sgblack@eecs.umich.edu (srcElem1 == maxNeg && srcElem2 == halfNeg)) { 26637639Sgblack@eecs.umich.edu if (destElem < 0) { 26647639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8 - 1); 26657639Sgblack@eecs.umich.edu } else { 266612038Srekai.gonzalezalberquilla@arm.com destElem = std::numeric_limits<Element>::min(); 26677639Sgblack@eecs.umich.edu } 26687639Sgblack@eecs.umich.edu fpscr.qc = 1; 26697639Sgblack@eecs.umich.edu } 26707783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 26717639Sgblack@eecs.umich.edu ''' 26727639Sgblack@eecs.umich.edu threeEqualRegInst("vqrdmulh", "VqrdmulhD", 26737760SGiacomo.Gabrielli@arm.com "SimdMultOp", smallSignedTypes, 2, vqrdmulhCode) 26747639Sgblack@eecs.umich.edu threeEqualRegInst("vqrdmulh", "VqrdmulhQ", 26757760SGiacomo.Gabrielli@arm.com "SimdMultOp", smallSignedTypes, 4, vqrdmulhCode) 26767639Sgblack@eecs.umich.edu 267713978Sciro.santilli@arm.com vMinMaxFpCode = ''' 267813978Sciro.santilli@arm.com destElem = fplib%s<Element>(srcElem1, srcElem2, fpscr); 26797639Sgblack@eecs.umich.edu ''' 268013978Sciro.santilli@arm.com vMinMaxInsts = [ 268113978Sciro.santilli@arm.com ("vmax", "VmaxDFp", 2, "Max", False, ), 268213978Sciro.santilli@arm.com ("vmax", "VmaxQFp", 4, "Max", False, ), 268313978Sciro.santilli@arm.com ("vmaxnm", "VmaxnmDFp", 2, "MaxNum", False, ), 268413978Sciro.santilli@arm.com ("vmaxnm", "VmaxnmQFp", 4, "MaxNum", False, ), 268513978Sciro.santilli@arm.com ("vpmax", "VpmaxDFp", 2, "Max", True, ), 268613978Sciro.santilli@arm.com ("vpmax", "VpmaxQFp", 4, "Max", True, ), 268713978Sciro.santilli@arm.com ("vmin", "VminDFp", 2, "Min", False, ), 268813978Sciro.santilli@arm.com ("vmin", "VminQFp", 4, "Min", False, ), 268913978Sciro.santilli@arm.com ("vminnm", "VminnmDFp", 2, "MinNum", False, ), 269013978Sciro.santilli@arm.com ("vminnm", "VminnmQFp", 4, "MinNum", False, ), 269113978Sciro.santilli@arm.com ("vpmin", "VpminDFp", 2, "Min", True, ), 269213978Sciro.santilli@arm.com ("vpmin", "VpminQFp", 4, "Min", True, ), 269313978Sciro.santilli@arm.com ] 269413978Sciro.santilli@arm.com for name, Name, rCount, op, pairwise in vMinMaxInsts: 269513978Sciro.santilli@arm.com threeEqualRegInst( 269613978Sciro.santilli@arm.com name, 269713978Sciro.santilli@arm.com Name, 269813978Sciro.santilli@arm.com "SimdFloatCmpOp", 269913978Sciro.santilli@arm.com ("uint32_t",), 270013978Sciro.santilli@arm.com rCount, 270113978Sciro.santilli@arm.com vMinMaxFpCode % op, 270213978Sciro.santilli@arm.com pairwise=pairwise, 270313978Sciro.santilli@arm.com standardFpcsr=True, 270413978Sciro.santilli@arm.com ) 27057639Sgblack@eecs.umich.edu 27067639Sgblack@eecs.umich.edu vaddfpCode = ''' 27077783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 27087639Sgblack@eecs.umich.edu destReg = binaryOp(fpscr, srcReg1, srcReg2, fpAddS, 27097639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 27107783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 27117639Sgblack@eecs.umich.edu ''' 27127760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vadd", "VaddDFp", "SimdFloatAddOp", ("float",), 2, vaddfpCode) 27137760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vadd", "VaddQFp", "SimdFloatAddOp", ("float",), 4, vaddfpCode) 27147639Sgblack@eecs.umich.edu 27157760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vpadd", "VpaddDFp", "SimdFloatAddOp", ("float",), 27167639Sgblack@eecs.umich.edu 2, vaddfpCode, pairwise=True) 27177760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vpadd", "VpaddQFp", "SimdFloatAddOp", ("float",), 27187639Sgblack@eecs.umich.edu 4, vaddfpCode, pairwise=True) 27197639Sgblack@eecs.umich.edu 27207639Sgblack@eecs.umich.edu vsubfpCode = ''' 27217783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 27227639Sgblack@eecs.umich.edu destReg = binaryOp(fpscr, srcReg1, srcReg2, fpSubS, 27237639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 27247783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 27257639Sgblack@eecs.umich.edu ''' 27267760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vsub", "VsubDFp", "SimdFloatAddOp", ("float",), 2, vsubfpCode) 27277760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vsub", "VsubQFp", "SimdFloatAddOp", ("float",), 4, vsubfpCode) 27287639Sgblack@eecs.umich.edu 27297639Sgblack@eecs.umich.edu vmulfpCode = ''' 27307783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 27317639Sgblack@eecs.umich.edu destReg = binaryOp(fpscr, srcReg1, srcReg2, fpMulS, 27327639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 27337783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 27347639Sgblack@eecs.umich.edu ''' 27357760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vmul", "NVmulDFp", "SimdFloatMultOp", ("float",), 2, vmulfpCode) 27367760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vmul", "NVmulQFp", "SimdFloatMultOp", ("float",), 4, vmulfpCode) 27377639Sgblack@eecs.umich.edu 27387639Sgblack@eecs.umich.edu vmlafpCode = ''' 27397783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 27407639Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, srcReg1, srcReg2, fpMulS, 27417639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 27427639Sgblack@eecs.umich.edu destReg = binaryOp(fpscr, mid, destReg, fpAddS, 27437639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 27447783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 27457639Sgblack@eecs.umich.edu ''' 27467760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vmla", "NVmlaDFp", "SimdFloatMultAccOp", ("float",), 2, vmlafpCode, True) 27477760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vmla", "NVmlaQFp", "SimdFloatMultAccOp", ("float",), 4, vmlafpCode, True) 27487639Sgblack@eecs.umich.edu 274910037SARM gem5 Developers vfmafpCode = ''' 275010037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrExc; 275110037SARM gem5 Developers destReg = ternaryOp(fpscr, srcReg1, srcReg2, destReg, fpMulAdd<float>, 275210037SARM gem5 Developers true, true, VfpRoundNearest); 275310037SARM gem5 Developers FpscrExc = fpscr; 275410037SARM gem5 Developers ''' 275510037SARM gem5 Developers threeEqualRegInstFp("vfma", "NVfmaDFp", "SimdFloatMultAccOp", ("float",), 2, vfmafpCode, True) 275610037SARM gem5 Developers threeEqualRegInstFp("vfma", "NVfmaQFp", "SimdFloatMultAccOp", ("float",), 4, vfmafpCode, True) 275710037SARM gem5 Developers 275810037SARM gem5 Developers vfmsfpCode = ''' 275910037SARM gem5 Developers FPSCR fpscr = (FPSCR) FpscrExc; 276010037SARM gem5 Developers destReg = ternaryOp(fpscr, -srcReg1, srcReg2, destReg, fpMulAdd<float>, 276110037SARM gem5 Developers true, true, VfpRoundNearest); 276210037SARM gem5 Developers FpscrExc = fpscr; 276310037SARM gem5 Developers ''' 276410037SARM gem5 Developers threeEqualRegInstFp("vfms", "NVfmsDFp", "SimdFloatMultAccOp", ("float",), 2, vfmsfpCode, True) 276510037SARM gem5 Developers threeEqualRegInstFp("vfms", "NVfmsQFp", "SimdFloatMultAccOp", ("float",), 4, vfmsfpCode, True) 276610037SARM gem5 Developers 27677639Sgblack@eecs.umich.edu vmlsfpCode = ''' 27687783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 27697639Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, srcReg1, srcReg2, fpMulS, 27707639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 27717639Sgblack@eecs.umich.edu destReg = binaryOp(fpscr, destReg, mid, fpSubS, 27727639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 27737783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 27747639Sgblack@eecs.umich.edu ''' 27757760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vmls", "NVmlsDFp", "SimdFloatMultAccOp", ("float",), 2, vmlsfpCode, True) 27767760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vmls", "NVmlsQFp", "SimdFloatMultAccOp", ("float",), 4, vmlsfpCode, True) 27777639Sgblack@eecs.umich.edu 27787639Sgblack@eecs.umich.edu vcgtfpCode = ''' 27797783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 27807639Sgblack@eecs.umich.edu float res = binaryOp(fpscr, srcReg1, srcReg2, vcgtFunc, 27817639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 27827639Sgblack@eecs.umich.edu destReg = (res == 0) ? -1 : 0; 27837639Sgblack@eecs.umich.edu if (res == 2.0) 27847639Sgblack@eecs.umich.edu fpscr.ioc = 1; 27857783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 27867639Sgblack@eecs.umich.edu ''' 27877760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vcgt", "VcgtDFp", "SimdFloatCmpOp", ("float",), 27887639Sgblack@eecs.umich.edu 2, vcgtfpCode, toInt = True) 27897760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vcgt", "VcgtQFp", "SimdFloatCmpOp", ("float",), 27907639Sgblack@eecs.umich.edu 4, vcgtfpCode, toInt = True) 27917639Sgblack@eecs.umich.edu 27927639Sgblack@eecs.umich.edu vcgefpCode = ''' 27937783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 27947639Sgblack@eecs.umich.edu float res = binaryOp(fpscr, srcReg1, srcReg2, vcgeFunc, 27957639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 27967639Sgblack@eecs.umich.edu destReg = (res == 0) ? -1 : 0; 27977639Sgblack@eecs.umich.edu if (res == 2.0) 27987639Sgblack@eecs.umich.edu fpscr.ioc = 1; 27997783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 28007639Sgblack@eecs.umich.edu ''' 28017760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vcge", "VcgeDFp", "SimdFloatCmpOp", ("float",), 28027639Sgblack@eecs.umich.edu 2, vcgefpCode, toInt = True) 28037760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vcge", "VcgeQFp", "SimdFloatCmpOp", ("float",), 28047639Sgblack@eecs.umich.edu 4, vcgefpCode, toInt = True) 28057639Sgblack@eecs.umich.edu 28067639Sgblack@eecs.umich.edu vacgtfpCode = ''' 28077783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 28087639Sgblack@eecs.umich.edu float res = binaryOp(fpscr, srcReg1, srcReg2, vacgtFunc, 28097639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 28107639Sgblack@eecs.umich.edu destReg = (res == 0) ? -1 : 0; 28117639Sgblack@eecs.umich.edu if (res == 2.0) 28127639Sgblack@eecs.umich.edu fpscr.ioc = 1; 28137783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 28147639Sgblack@eecs.umich.edu ''' 28157760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vacgt", "VacgtDFp", "SimdFloatCmpOp", ("float",), 28167639Sgblack@eecs.umich.edu 2, vacgtfpCode, toInt = True) 28177760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vacgt", "VacgtQFp", "SimdFloatCmpOp", ("float",), 28187639Sgblack@eecs.umich.edu 4, vacgtfpCode, toInt = True) 28197639Sgblack@eecs.umich.edu 28207639Sgblack@eecs.umich.edu vacgefpCode = ''' 28217783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 28227639Sgblack@eecs.umich.edu float res = binaryOp(fpscr, srcReg1, srcReg2, vacgeFunc, 28237639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 28247639Sgblack@eecs.umich.edu destReg = (res == 0) ? -1 : 0; 28257639Sgblack@eecs.umich.edu if (res == 2.0) 28267639Sgblack@eecs.umich.edu fpscr.ioc = 1; 28277783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 28287639Sgblack@eecs.umich.edu ''' 28297760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vacge", "VacgeDFp", "SimdFloatCmpOp", ("float",), 28307639Sgblack@eecs.umich.edu 2, vacgefpCode, toInt = True) 28317760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vacge", "VacgeQFp", "SimdFloatCmpOp", ("float",), 28327639Sgblack@eecs.umich.edu 4, vacgefpCode, toInt = True) 28337639Sgblack@eecs.umich.edu 28347639Sgblack@eecs.umich.edu vceqfpCode = ''' 28357783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 28367639Sgblack@eecs.umich.edu float res = binaryOp(fpscr, srcReg1, srcReg2, vceqFunc, 28377639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 28387639Sgblack@eecs.umich.edu destReg = (res == 0) ? -1 : 0; 28397639Sgblack@eecs.umich.edu if (res == 2.0) 28407639Sgblack@eecs.umich.edu fpscr.ioc = 1; 28417783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 28427639Sgblack@eecs.umich.edu ''' 28437760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vceq", "VceqDFp", "SimdFloatCmpOp", ("float",), 28447639Sgblack@eecs.umich.edu 2, vceqfpCode, toInt = True) 28457760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vceq", "VceqQFp", "SimdFloatCmpOp", ("float",), 28467639Sgblack@eecs.umich.edu 4, vceqfpCode, toInt = True) 28477639Sgblack@eecs.umich.edu 28487639Sgblack@eecs.umich.edu vrecpsCode = ''' 28497783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 28507639Sgblack@eecs.umich.edu destReg = binaryOp(fpscr, srcReg1, srcReg2, fpRecpsS, 28517639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 28527783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 28537639Sgblack@eecs.umich.edu ''' 28547760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vrecps", "VrecpsDFp", "SimdFloatMultAccOp", ("float",), 2, vrecpsCode) 28557760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vrecps", "VrecpsQFp", "SimdFloatMultAccOp", ("float",), 4, vrecpsCode) 28567639Sgblack@eecs.umich.edu 28577639Sgblack@eecs.umich.edu vrsqrtsCode = ''' 28587783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 28597639Sgblack@eecs.umich.edu destReg = binaryOp(fpscr, srcReg1, srcReg2, fpRSqrtsS, 28607639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 28617783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 28627639Sgblack@eecs.umich.edu ''' 28637760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vrsqrts", "VrsqrtsDFp", "SimdFloatMiscOp", ("float",), 2, vrsqrtsCode) 28647760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vrsqrts", "VrsqrtsQFp", "SimdFloatMiscOp", ("float",), 4, vrsqrtsCode) 28657639Sgblack@eecs.umich.edu 28667639Sgblack@eecs.umich.edu vabdfpCode = ''' 28677783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 28687639Sgblack@eecs.umich.edu float mid = binaryOp(fpscr, srcReg1, srcReg2, fpSubS, 28697639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 28707639Sgblack@eecs.umich.edu destReg = fabs(mid); 28717783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 28727639Sgblack@eecs.umich.edu ''' 28737760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vabd", "VabdDFp", "SimdFloatAddOp", ("float",), 2, vabdfpCode) 28747760SGiacomo.Gabrielli@arm.com threeEqualRegInstFp("vabd", "VabdQFp", "SimdFloatAddOp", ("float",), 4, vabdfpCode) 28757639Sgblack@eecs.umich.edu 28767760SGiacomo.Gabrielli@arm.com twoEqualRegInst("vmla", "VmlasD", "SimdMultAccOp", unsignedTypes, 2, vmlaCode, True) 28777760SGiacomo.Gabrielli@arm.com twoEqualRegInst("vmla", "VmlasQ", "SimdMultAccOp", unsignedTypes, 4, vmlaCode, True) 28787760SGiacomo.Gabrielli@arm.com twoEqualRegInstFp("vmla", "VmlasDFp", "SimdFloatMultAccOp", ("float",), 2, vmlafpCode, True) 28797760SGiacomo.Gabrielli@arm.com twoEqualRegInstFp("vmla", "VmlasQFp", "SimdFloatMultAccOp", ("float",), 4, vmlafpCode, True) 28807760SGiacomo.Gabrielli@arm.com twoRegLongInst("vmlal", "Vmlals", "SimdMultAccOp", smallTypes, vmlalCode, True) 28817639Sgblack@eecs.umich.edu 28827760SGiacomo.Gabrielli@arm.com twoEqualRegInst("vmls", "VmlssD", "SimdMultAccOp", allTypes, 2, vmlsCode, True) 28837760SGiacomo.Gabrielli@arm.com twoEqualRegInst("vmls", "VmlssQ", "SimdMultAccOp", allTypes, 4, vmlsCode, True) 28847760SGiacomo.Gabrielli@arm.com twoEqualRegInstFp("vmls", "VmlssDFp", "SimdFloatMultAccOp", ("float",), 2, vmlsfpCode, True) 28857760SGiacomo.Gabrielli@arm.com twoEqualRegInstFp("vmls", "VmlssQFp", "SimdFloatMultAccOp", ("float",), 4, vmlsfpCode, True) 28867760SGiacomo.Gabrielli@arm.com twoRegLongInst("vmlsl", "Vmlsls", "SimdMultAccOp", smallTypes, vmlslCode, True) 28877639Sgblack@eecs.umich.edu 28887760SGiacomo.Gabrielli@arm.com twoEqualRegInst("vmul", "VmulsD", "SimdMultOp", allTypes, 2, vmulCode) 28897760SGiacomo.Gabrielli@arm.com twoEqualRegInst("vmul", "VmulsQ", "SimdMultOp", allTypes, 4, vmulCode) 28907760SGiacomo.Gabrielli@arm.com twoEqualRegInstFp("vmul", "VmulsDFp", "SimdFloatMultOp", ("float",), 2, vmulfpCode) 28917760SGiacomo.Gabrielli@arm.com twoEqualRegInstFp("vmul", "VmulsQFp", "SimdFloatMultOp", ("float",), 4, vmulfpCode) 28927760SGiacomo.Gabrielli@arm.com twoRegLongInst("vmull", "Vmulls", "SimdMultOp", smallTypes, vmullCode) 28937639Sgblack@eecs.umich.edu 28947760SGiacomo.Gabrielli@arm.com twoRegLongInst("vqdmull", "Vqdmulls", "SimdMultOp", smallTypes, vqdmullCode) 28957760SGiacomo.Gabrielli@arm.com twoRegLongInst("vqdmlal", "Vqdmlals", "SimdMultAccOp", smallTypes, vqdmlalCode, True) 28967760SGiacomo.Gabrielli@arm.com twoRegLongInst("vqdmlsl", "Vqdmlsls", "SimdMultAccOp", smallTypes, vqdmlslCode, True) 28977760SGiacomo.Gabrielli@arm.com twoEqualRegInst("vqdmulh", "VqdmulhsD", "SimdMultOp", smallSignedTypes, 2, vqdmulhCode) 28987760SGiacomo.Gabrielli@arm.com twoEqualRegInst("vqdmulh", "VqdmulhsQ", "SimdMultOp", smallSignedTypes, 4, vqdmulhCode) 28997639Sgblack@eecs.umich.edu twoEqualRegInst("vqrdmulh", "VqrdmulhsD", 29007760SGiacomo.Gabrielli@arm.com "SimdMultOp", smallSignedTypes, 2, vqrdmulhCode) 29017639Sgblack@eecs.umich.edu twoEqualRegInst("vqrdmulh", "VqrdmulhsQ", 29027760SGiacomo.Gabrielli@arm.com "SimdMultOp", smallSignedTypes, 4, vqrdmulhCode) 29037639Sgblack@eecs.umich.edu 29047639Sgblack@eecs.umich.edu vshrCode = ''' 29057639Sgblack@eecs.umich.edu if (imm >= sizeof(srcElem1) * 8) { 29067641Sgblack@eecs.umich.edu if (ltz(srcElem1)) 29077639Sgblack@eecs.umich.edu destElem = -1; 29087639Sgblack@eecs.umich.edu else 29097639Sgblack@eecs.umich.edu destElem = 0; 29107639Sgblack@eecs.umich.edu } else { 29117639Sgblack@eecs.umich.edu destElem = srcElem1 >> imm; 29127639Sgblack@eecs.umich.edu } 29137639Sgblack@eecs.umich.edu ''' 29147760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vshr", "NVshrD", "SimdShiftOp", allTypes, 2, vshrCode) 29157760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vshr", "NVshrQ", "SimdShiftOp", allTypes, 4, vshrCode) 29167639Sgblack@eecs.umich.edu 29177639Sgblack@eecs.umich.edu vsraCode = ''' 29187639Sgblack@eecs.umich.edu Element mid;; 29197639Sgblack@eecs.umich.edu if (imm >= sizeof(srcElem1) * 8) { 29207641Sgblack@eecs.umich.edu mid = ltz(srcElem1) ? -1 : 0; 29217639Sgblack@eecs.umich.edu } else { 29227639Sgblack@eecs.umich.edu mid = srcElem1 >> imm; 29237641Sgblack@eecs.umich.edu if (ltz(srcElem1) && !ltz(mid)) { 29247639Sgblack@eecs.umich.edu mid |= -(mid & ((Element)1 << 29257639Sgblack@eecs.umich.edu (sizeof(Element) * 8 - 1 - imm))); 29267639Sgblack@eecs.umich.edu } 29277639Sgblack@eecs.umich.edu } 29287639Sgblack@eecs.umich.edu destElem += mid; 29297639Sgblack@eecs.umich.edu ''' 29307760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vsra", "NVsraD", "SimdShiftAccOp", allTypes, 2, vsraCode, True) 29317760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vsra", "NVsraQ", "SimdShiftAccOp", allTypes, 4, vsraCode, True) 29327639Sgblack@eecs.umich.edu 29337639Sgblack@eecs.umich.edu vrshrCode = ''' 29347639Sgblack@eecs.umich.edu if (imm > sizeof(srcElem1) * 8) { 29357639Sgblack@eecs.umich.edu destElem = 0; 29367639Sgblack@eecs.umich.edu } else if (imm) { 29377639Sgblack@eecs.umich.edu Element rBit = bits(srcElem1, imm - 1); 29387639Sgblack@eecs.umich.edu destElem = ((srcElem1 >> (imm - 1)) >> 1) + rBit; 29397639Sgblack@eecs.umich.edu } else { 29407639Sgblack@eecs.umich.edu destElem = srcElem1; 29417639Sgblack@eecs.umich.edu } 29427639Sgblack@eecs.umich.edu ''' 29437760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vrshr", "NVrshrD", "SimdShiftOp", allTypes, 2, vrshrCode) 29447760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vrshr", "NVrshrQ", "SimdShiftOp", allTypes, 4, vrshrCode) 29457639Sgblack@eecs.umich.edu 29467639Sgblack@eecs.umich.edu vrsraCode = ''' 29477639Sgblack@eecs.umich.edu if (imm > sizeof(srcElem1) * 8) { 29487639Sgblack@eecs.umich.edu destElem += 0; 29497639Sgblack@eecs.umich.edu } else if (imm) { 29507639Sgblack@eecs.umich.edu Element rBit = bits(srcElem1, imm - 1); 29517639Sgblack@eecs.umich.edu destElem += ((srcElem1 >> (imm - 1)) >> 1) + rBit; 29527639Sgblack@eecs.umich.edu } else { 29537639Sgblack@eecs.umich.edu destElem += srcElem1; 29547639Sgblack@eecs.umich.edu } 29557639Sgblack@eecs.umich.edu ''' 29567760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vrsra", "NVrsraD", "SimdShiftAccOp", allTypes, 2, vrsraCode, True) 29577760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vrsra", "NVrsraQ", "SimdShiftAccOp", allTypes, 4, vrsraCode, True) 29587639Sgblack@eecs.umich.edu 29597639Sgblack@eecs.umich.edu vsriCode = ''' 296011443Sandreas.hansson@arm.com if (imm >= sizeof(Element) * 8) { 29617639Sgblack@eecs.umich.edu destElem = destElem; 296211443Sandreas.hansson@arm.com } else { 29637639Sgblack@eecs.umich.edu destElem = (srcElem1 >> imm) | 29647639Sgblack@eecs.umich.edu (destElem & ~mask(sizeof(Element) * 8 - imm)); 296511443Sandreas.hansson@arm.com } 29667639Sgblack@eecs.umich.edu ''' 29677760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vsri", "NVsriD", "SimdShiftOp", unsignedTypes, 2, vsriCode, True) 29687760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vsri", "NVsriQ", "SimdShiftOp", unsignedTypes, 4, vsriCode, True) 29697639Sgblack@eecs.umich.edu 29707639Sgblack@eecs.umich.edu vshlCode = ''' 297111443Sandreas.hansson@arm.com if (imm >= sizeof(Element) * 8) { 29727639Sgblack@eecs.umich.edu destElem = (srcElem1 << (sizeof(Element) * 8 - 1)) << 1; 297311443Sandreas.hansson@arm.com } else { 29747639Sgblack@eecs.umich.edu destElem = srcElem1 << imm; 297511443Sandreas.hansson@arm.com } 29767639Sgblack@eecs.umich.edu ''' 29777760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vshl", "NVshlD", "SimdShiftOp", unsignedTypes, 2, vshlCode) 29787760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vshl", "NVshlQ", "SimdShiftOp", unsignedTypes, 4, vshlCode) 29797639Sgblack@eecs.umich.edu 29807639Sgblack@eecs.umich.edu vsliCode = ''' 298111443Sandreas.hansson@arm.com if (imm >= sizeof(Element) * 8) { 29827639Sgblack@eecs.umich.edu destElem = destElem; 298311443Sandreas.hansson@arm.com } else { 29847639Sgblack@eecs.umich.edu destElem = (srcElem1 << imm) | (destElem & mask(imm)); 298511443Sandreas.hansson@arm.com } 29867639Sgblack@eecs.umich.edu ''' 29877760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vsli", "NVsliD", "SimdShiftOp", unsignedTypes, 2, vsliCode, True) 29887760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vsli", "NVsliQ", "SimdShiftOp", unsignedTypes, 4, vsliCode, True) 29897639Sgblack@eecs.umich.edu 29907639Sgblack@eecs.umich.edu vqshlCode = ''' 29917783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 29927639Sgblack@eecs.umich.edu if (imm >= sizeof(Element) * 8) { 29937639Sgblack@eecs.umich.edu if (srcElem1 != 0) { 299412038Srekai.gonzalezalberquilla@arm.com destElem = std::numeric_limits<Element>::min(); 29957639Sgblack@eecs.umich.edu if (srcElem1 > 0) 29967639Sgblack@eecs.umich.edu destElem = ~destElem; 29977639Sgblack@eecs.umich.edu fpscr.qc = 1; 29987639Sgblack@eecs.umich.edu } else { 29997639Sgblack@eecs.umich.edu destElem = 0; 30007639Sgblack@eecs.umich.edu } 30017639Sgblack@eecs.umich.edu } else if (imm) { 30027639Sgblack@eecs.umich.edu destElem = (srcElem1 << imm); 30037639Sgblack@eecs.umich.edu uint64_t topBits = bits((uint64_t)srcElem1, 30047639Sgblack@eecs.umich.edu sizeof(Element) * 8 - 1, 30057639Sgblack@eecs.umich.edu sizeof(Element) * 8 - 1 - imm); 30067639Sgblack@eecs.umich.edu if (topBits != 0 && topBits != mask(imm + 1)) { 300712038Srekai.gonzalezalberquilla@arm.com destElem = std::numeric_limits<Element>::min(); 30087639Sgblack@eecs.umich.edu if (srcElem1 > 0) 30097639Sgblack@eecs.umich.edu destElem = ~destElem; 30107639Sgblack@eecs.umich.edu fpscr.qc = 1; 30117639Sgblack@eecs.umich.edu } 30127639Sgblack@eecs.umich.edu } else { 30137639Sgblack@eecs.umich.edu destElem = srcElem1; 30147639Sgblack@eecs.umich.edu } 30157783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 30167639Sgblack@eecs.umich.edu ''' 30177760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vqshl", "NVqshlD", "SimdShiftOp", signedTypes, 2, vqshlCode) 30187760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vqshl", "NVqshlQ", "SimdShiftOp", signedTypes, 4, vqshlCode) 30197639Sgblack@eecs.umich.edu 30207639Sgblack@eecs.umich.edu vqshluCode = ''' 30217783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 30227639Sgblack@eecs.umich.edu if (imm >= sizeof(Element) * 8) { 30237639Sgblack@eecs.umich.edu if (srcElem1 != 0) { 30247639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8); 30257639Sgblack@eecs.umich.edu fpscr.qc = 1; 30267639Sgblack@eecs.umich.edu } else { 30277639Sgblack@eecs.umich.edu destElem = 0; 30287639Sgblack@eecs.umich.edu } 30297639Sgblack@eecs.umich.edu } else if (imm) { 30307639Sgblack@eecs.umich.edu destElem = (srcElem1 << imm); 30317639Sgblack@eecs.umich.edu uint64_t topBits = bits((uint64_t)srcElem1, 30327639Sgblack@eecs.umich.edu sizeof(Element) * 8 - 1, 30337639Sgblack@eecs.umich.edu sizeof(Element) * 8 - imm); 30347639Sgblack@eecs.umich.edu if (topBits != 0) { 30357639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8); 30367639Sgblack@eecs.umich.edu fpscr.qc = 1; 30377639Sgblack@eecs.umich.edu } 30387639Sgblack@eecs.umich.edu } else { 30397639Sgblack@eecs.umich.edu destElem = srcElem1; 30407639Sgblack@eecs.umich.edu } 30417783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 30427639Sgblack@eecs.umich.edu ''' 30437760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vqshlu", "NVqshluD", "SimdShiftOp", unsignedTypes, 2, vqshluCode) 30447760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vqshlu", "NVqshluQ", "SimdShiftOp", unsignedTypes, 4, vqshluCode) 30457639Sgblack@eecs.umich.edu 30467639Sgblack@eecs.umich.edu vqshlusCode = ''' 30477783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 30487639Sgblack@eecs.umich.edu if (imm >= sizeof(Element) * 8) { 30497639Sgblack@eecs.umich.edu if (srcElem1 < 0) { 30507639Sgblack@eecs.umich.edu destElem = 0; 30517639Sgblack@eecs.umich.edu fpscr.qc = 1; 30527639Sgblack@eecs.umich.edu } else if (srcElem1 > 0) { 30537639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8); 30547639Sgblack@eecs.umich.edu fpscr.qc = 1; 30557639Sgblack@eecs.umich.edu } else { 30567639Sgblack@eecs.umich.edu destElem = 0; 30577639Sgblack@eecs.umich.edu } 30587639Sgblack@eecs.umich.edu } else if (imm) { 30597639Sgblack@eecs.umich.edu destElem = (srcElem1 << imm); 30607639Sgblack@eecs.umich.edu uint64_t topBits = bits((uint64_t)srcElem1, 30617639Sgblack@eecs.umich.edu sizeof(Element) * 8 - 1, 30627639Sgblack@eecs.umich.edu sizeof(Element) * 8 - imm); 30637639Sgblack@eecs.umich.edu if (srcElem1 < 0) { 30647639Sgblack@eecs.umich.edu destElem = 0; 30657639Sgblack@eecs.umich.edu fpscr.qc = 1; 30667639Sgblack@eecs.umich.edu } else if (topBits != 0) { 30677639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8); 30687639Sgblack@eecs.umich.edu fpscr.qc = 1; 30697639Sgblack@eecs.umich.edu } 30707639Sgblack@eecs.umich.edu } else { 30717639Sgblack@eecs.umich.edu if (srcElem1 < 0) { 30727639Sgblack@eecs.umich.edu fpscr.qc = 1; 30737639Sgblack@eecs.umich.edu destElem = 0; 30747639Sgblack@eecs.umich.edu } else { 30757639Sgblack@eecs.umich.edu destElem = srcElem1; 30767639Sgblack@eecs.umich.edu } 30777639Sgblack@eecs.umich.edu } 30787783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 30797639Sgblack@eecs.umich.edu ''' 30807760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vqshlus", "NVqshlusD", "SimdShiftOp", signedTypes, 2, vqshlusCode) 30817760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vqshlus", "NVqshlusQ", "SimdShiftOp", signedTypes, 4, vqshlusCode) 30827639Sgblack@eecs.umich.edu 30837639Sgblack@eecs.umich.edu vshrnCode = ''' 30847639Sgblack@eecs.umich.edu if (imm >= sizeof(srcElem1) * 8) { 30857639Sgblack@eecs.umich.edu destElem = 0; 30867639Sgblack@eecs.umich.edu } else { 30877639Sgblack@eecs.umich.edu destElem = srcElem1 >> imm; 30887639Sgblack@eecs.umich.edu } 30897639Sgblack@eecs.umich.edu ''' 30907760SGiacomo.Gabrielli@arm.com twoRegNarrowShiftInst("vshrn", "NVshrn", "SimdShiftOp", smallUnsignedTypes, vshrnCode) 30917639Sgblack@eecs.umich.edu 30927639Sgblack@eecs.umich.edu vrshrnCode = ''' 30937639Sgblack@eecs.umich.edu if (imm > sizeof(srcElem1) * 8) { 30947639Sgblack@eecs.umich.edu destElem = 0; 30957639Sgblack@eecs.umich.edu } else if (imm) { 30967639Sgblack@eecs.umich.edu Element rBit = bits(srcElem1, imm - 1); 30977639Sgblack@eecs.umich.edu destElem = ((srcElem1 >> (imm - 1)) >> 1) + rBit; 30987639Sgblack@eecs.umich.edu } else { 30997639Sgblack@eecs.umich.edu destElem = srcElem1; 31007639Sgblack@eecs.umich.edu } 31017639Sgblack@eecs.umich.edu ''' 31027760SGiacomo.Gabrielli@arm.com twoRegNarrowShiftInst("vrshrn", "NVrshrn", "SimdShiftOp", smallUnsignedTypes, vrshrnCode) 31037639Sgblack@eecs.umich.edu 31047639Sgblack@eecs.umich.edu vqshrnCode = ''' 31057783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 31067639Sgblack@eecs.umich.edu if (imm > sizeof(srcElem1) * 8) { 31077639Sgblack@eecs.umich.edu if (srcElem1 != 0 && srcElem1 != -1) 31087639Sgblack@eecs.umich.edu fpscr.qc = 1; 31097639Sgblack@eecs.umich.edu destElem = 0; 31107639Sgblack@eecs.umich.edu } else if (imm) { 31117639Sgblack@eecs.umich.edu BigElement mid = ((srcElem1 >> (imm - 1)) >> 1); 31127639Sgblack@eecs.umich.edu mid |= -(mid & ((BigElement)1 << 31137639Sgblack@eecs.umich.edu (sizeof(BigElement) * 8 - 1 - imm))); 31147639Sgblack@eecs.umich.edu if (mid != (Element)mid) { 31157639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8 - 1); 31167639Sgblack@eecs.umich.edu if (srcElem1 < 0) 31177639Sgblack@eecs.umich.edu destElem = ~destElem; 31187639Sgblack@eecs.umich.edu fpscr.qc = 1; 31197639Sgblack@eecs.umich.edu } else { 31207639Sgblack@eecs.umich.edu destElem = mid; 31217639Sgblack@eecs.umich.edu } 31227639Sgblack@eecs.umich.edu } else { 31237639Sgblack@eecs.umich.edu destElem = srcElem1; 31247639Sgblack@eecs.umich.edu } 31257783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 31267639Sgblack@eecs.umich.edu ''' 31277760SGiacomo.Gabrielli@arm.com twoRegNarrowShiftInst("vqshrn", "NVqshrn", "SimdShiftOp", smallSignedTypes, vqshrnCode) 31287639Sgblack@eecs.umich.edu 31297639Sgblack@eecs.umich.edu vqshrunCode = ''' 31307783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 31317639Sgblack@eecs.umich.edu if (imm > sizeof(srcElem1) * 8) { 31327639Sgblack@eecs.umich.edu if (srcElem1 != 0) 31337639Sgblack@eecs.umich.edu fpscr.qc = 1; 31347639Sgblack@eecs.umich.edu destElem = 0; 31357639Sgblack@eecs.umich.edu } else if (imm) { 31367639Sgblack@eecs.umich.edu BigElement mid = ((srcElem1 >> (imm - 1)) >> 1); 31377639Sgblack@eecs.umich.edu if (mid != (Element)mid) { 31387639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8); 31397639Sgblack@eecs.umich.edu fpscr.qc = 1; 31407639Sgblack@eecs.umich.edu } else { 31417639Sgblack@eecs.umich.edu destElem = mid; 31427639Sgblack@eecs.umich.edu } 31437639Sgblack@eecs.umich.edu } else { 31447639Sgblack@eecs.umich.edu destElem = srcElem1; 31457639Sgblack@eecs.umich.edu } 31467783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 31477639Sgblack@eecs.umich.edu ''' 31487639Sgblack@eecs.umich.edu twoRegNarrowShiftInst("vqshrun", "NVqshrun", 31497760SGiacomo.Gabrielli@arm.com "SimdShiftOp", smallUnsignedTypes, vqshrunCode) 31507639Sgblack@eecs.umich.edu 31517639Sgblack@eecs.umich.edu vqshrunsCode = ''' 31527783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 31537639Sgblack@eecs.umich.edu if (imm > sizeof(srcElem1) * 8) { 31547639Sgblack@eecs.umich.edu if (srcElem1 != 0) 31557639Sgblack@eecs.umich.edu fpscr.qc = 1; 31567639Sgblack@eecs.umich.edu destElem = 0; 31577639Sgblack@eecs.umich.edu } else if (imm) { 31587639Sgblack@eecs.umich.edu BigElement mid = ((srcElem1 >> (imm - 1)) >> 1); 31597639Sgblack@eecs.umich.edu if (bits(mid, sizeof(BigElement) * 8 - 1, 31607639Sgblack@eecs.umich.edu sizeof(Element) * 8) != 0) { 31617639Sgblack@eecs.umich.edu if (srcElem1 < 0) { 31627639Sgblack@eecs.umich.edu destElem = 0; 31637639Sgblack@eecs.umich.edu } else { 31647639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8); 31657639Sgblack@eecs.umich.edu } 31667639Sgblack@eecs.umich.edu fpscr.qc = 1; 31677639Sgblack@eecs.umich.edu } else { 31687639Sgblack@eecs.umich.edu destElem = mid; 31697639Sgblack@eecs.umich.edu } 31707639Sgblack@eecs.umich.edu } else { 31717639Sgblack@eecs.umich.edu destElem = srcElem1; 31727639Sgblack@eecs.umich.edu } 31737783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 31747639Sgblack@eecs.umich.edu ''' 31757639Sgblack@eecs.umich.edu twoRegNarrowShiftInst("vqshrun", "NVqshruns", 31767760SGiacomo.Gabrielli@arm.com "SimdShiftOp", smallSignedTypes, vqshrunsCode) 31777639Sgblack@eecs.umich.edu 31787639Sgblack@eecs.umich.edu vqrshrnCode = ''' 31797783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 31807639Sgblack@eecs.umich.edu if (imm > sizeof(srcElem1) * 8) { 31817639Sgblack@eecs.umich.edu if (srcElem1 != 0 && srcElem1 != -1) 31827639Sgblack@eecs.umich.edu fpscr.qc = 1; 31837639Sgblack@eecs.umich.edu destElem = 0; 31847639Sgblack@eecs.umich.edu } else if (imm) { 31857639Sgblack@eecs.umich.edu BigElement mid = (srcElem1 >> (imm - 1)); 31867639Sgblack@eecs.umich.edu uint64_t rBit = mid & 0x1; 31877639Sgblack@eecs.umich.edu mid >>= 1; 31887639Sgblack@eecs.umich.edu mid |= -(mid & ((BigElement)1 << 31897639Sgblack@eecs.umich.edu (sizeof(BigElement) * 8 - 1 - imm))); 31907639Sgblack@eecs.umich.edu mid += rBit; 31917639Sgblack@eecs.umich.edu if (mid != (Element)mid) { 31927639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8 - 1); 31937639Sgblack@eecs.umich.edu if (srcElem1 < 0) 31947639Sgblack@eecs.umich.edu destElem = ~destElem; 31957639Sgblack@eecs.umich.edu fpscr.qc = 1; 31967639Sgblack@eecs.umich.edu } else { 31977639Sgblack@eecs.umich.edu destElem = mid; 31987639Sgblack@eecs.umich.edu } 31997639Sgblack@eecs.umich.edu } else { 32007639Sgblack@eecs.umich.edu if (srcElem1 != (Element)srcElem1) { 32017639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8 - 1); 32027639Sgblack@eecs.umich.edu if (srcElem1 < 0) 32037639Sgblack@eecs.umich.edu destElem = ~destElem; 32047639Sgblack@eecs.umich.edu fpscr.qc = 1; 32057639Sgblack@eecs.umich.edu } else { 32067639Sgblack@eecs.umich.edu destElem = srcElem1; 32077639Sgblack@eecs.umich.edu } 32087639Sgblack@eecs.umich.edu } 32097783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 32107639Sgblack@eecs.umich.edu ''' 32117639Sgblack@eecs.umich.edu twoRegNarrowShiftInst("vqrshrn", "NVqrshrn", 32127760SGiacomo.Gabrielli@arm.com "SimdShiftOp", smallSignedTypes, vqrshrnCode) 32137639Sgblack@eecs.umich.edu 32147639Sgblack@eecs.umich.edu vqrshrunCode = ''' 32157783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 32167639Sgblack@eecs.umich.edu if (imm > sizeof(srcElem1) * 8) { 32177639Sgblack@eecs.umich.edu if (srcElem1 != 0) 32187639Sgblack@eecs.umich.edu fpscr.qc = 1; 32197639Sgblack@eecs.umich.edu destElem = 0; 32207639Sgblack@eecs.umich.edu } else if (imm) { 32217639Sgblack@eecs.umich.edu BigElement mid = (srcElem1 >> (imm - 1)); 32227639Sgblack@eecs.umich.edu uint64_t rBit = mid & 0x1; 32237639Sgblack@eecs.umich.edu mid >>= 1; 32247639Sgblack@eecs.umich.edu mid += rBit; 32257639Sgblack@eecs.umich.edu if (mid != (Element)mid) { 32267639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8); 32277639Sgblack@eecs.umich.edu fpscr.qc = 1; 32287639Sgblack@eecs.umich.edu } else { 32297639Sgblack@eecs.umich.edu destElem = mid; 32307639Sgblack@eecs.umich.edu } 32317639Sgblack@eecs.umich.edu } else { 32327639Sgblack@eecs.umich.edu if (srcElem1 != (Element)srcElem1) { 32337639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8 - 1); 32347639Sgblack@eecs.umich.edu fpscr.qc = 1; 32357639Sgblack@eecs.umich.edu } else { 32367639Sgblack@eecs.umich.edu destElem = srcElem1; 32377639Sgblack@eecs.umich.edu } 32387639Sgblack@eecs.umich.edu } 32397783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 32407639Sgblack@eecs.umich.edu ''' 32417639Sgblack@eecs.umich.edu twoRegNarrowShiftInst("vqrshrun", "NVqrshrun", 32427760SGiacomo.Gabrielli@arm.com "SimdShiftOp", smallUnsignedTypes, vqrshrunCode) 32437639Sgblack@eecs.umich.edu 32447639Sgblack@eecs.umich.edu vqrshrunsCode = ''' 32457783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 32467639Sgblack@eecs.umich.edu if (imm > sizeof(srcElem1) * 8) { 32477639Sgblack@eecs.umich.edu if (srcElem1 != 0) 32487639Sgblack@eecs.umich.edu fpscr.qc = 1; 32497639Sgblack@eecs.umich.edu destElem = 0; 32507639Sgblack@eecs.umich.edu } else if (imm) { 32517639Sgblack@eecs.umich.edu BigElement mid = (srcElem1 >> (imm - 1)); 32527639Sgblack@eecs.umich.edu uint64_t rBit = mid & 0x1; 32537639Sgblack@eecs.umich.edu mid >>= 1; 32547639Sgblack@eecs.umich.edu mid |= -(mid & ((BigElement)1 << 32557639Sgblack@eecs.umich.edu (sizeof(BigElement) * 8 - 1 - imm))); 32567639Sgblack@eecs.umich.edu mid += rBit; 32577639Sgblack@eecs.umich.edu if (bits(mid, sizeof(BigElement) * 8 - 1, 32587639Sgblack@eecs.umich.edu sizeof(Element) * 8) != 0) { 32597639Sgblack@eecs.umich.edu if (srcElem1 < 0) { 32607639Sgblack@eecs.umich.edu destElem = 0; 32617639Sgblack@eecs.umich.edu } else { 32627639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8); 32637639Sgblack@eecs.umich.edu } 32647639Sgblack@eecs.umich.edu fpscr.qc = 1; 32657639Sgblack@eecs.umich.edu } else { 32667639Sgblack@eecs.umich.edu destElem = mid; 32677639Sgblack@eecs.umich.edu } 32687639Sgblack@eecs.umich.edu } else { 32697639Sgblack@eecs.umich.edu if (srcElem1 < 0) { 32707639Sgblack@eecs.umich.edu fpscr.qc = 1; 32717639Sgblack@eecs.umich.edu destElem = 0; 32727639Sgblack@eecs.umich.edu } else { 32737639Sgblack@eecs.umich.edu destElem = srcElem1; 32747639Sgblack@eecs.umich.edu } 32757639Sgblack@eecs.umich.edu } 32767783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 32777639Sgblack@eecs.umich.edu ''' 32787639Sgblack@eecs.umich.edu twoRegNarrowShiftInst("vqrshrun", "NVqrshruns", 32797760SGiacomo.Gabrielli@arm.com "SimdShiftOp", smallSignedTypes, vqrshrunsCode) 32807639Sgblack@eecs.umich.edu 32817639Sgblack@eecs.umich.edu vshllCode = ''' 32827639Sgblack@eecs.umich.edu if (imm >= sizeof(destElem) * 8) { 32837639Sgblack@eecs.umich.edu destElem = 0; 32847639Sgblack@eecs.umich.edu } else { 32857639Sgblack@eecs.umich.edu destElem = (BigElement)srcElem1 << imm; 32867639Sgblack@eecs.umich.edu } 32877639Sgblack@eecs.umich.edu ''' 32887760SGiacomo.Gabrielli@arm.com twoRegLongShiftInst("vshll", "NVshll", "SimdShiftOp", smallTypes, vshllCode) 32897639Sgblack@eecs.umich.edu 32907639Sgblack@eecs.umich.edu vmovlCode = ''' 32917639Sgblack@eecs.umich.edu destElem = srcElem1; 32927639Sgblack@eecs.umich.edu ''' 32937760SGiacomo.Gabrielli@arm.com twoRegLongShiftInst("vmovl", "NVmovl", "SimdMiscOp", smallTypes, vmovlCode) 32947639Sgblack@eecs.umich.edu 32957639Sgblack@eecs.umich.edu vcvt2ufxCode = ''' 32967783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 32977639Sgblack@eecs.umich.edu if (flushToZero(srcElem1)) 32987639Sgblack@eecs.umich.edu fpscr.idc = 1; 32997639Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(VfpRoundNearest); 33007639Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (srcElem1) : "m" (srcElem1)); 330110037SARM gem5 Developers destReg = vfpFpToFixed<float>(srcElem1, false, 32, imm); 33027639Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (destReg)); 33037639Sgblack@eecs.umich.edu finishVfp(fpscr, state, true); 33047783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 33057639Sgblack@eecs.umich.edu ''' 33067760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vcvt", "NVcvt2ufxD", "SimdCvtOp", ("float",), 33077639Sgblack@eecs.umich.edu 2, vcvt2ufxCode, toInt = True) 33087760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vcvt", "NVcvt2ufxQ", "SimdCvtOp", ("float",), 33097639Sgblack@eecs.umich.edu 4, vcvt2ufxCode, toInt = True) 33107639Sgblack@eecs.umich.edu 33117639Sgblack@eecs.umich.edu vcvt2sfxCode = ''' 33127783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 33137639Sgblack@eecs.umich.edu if (flushToZero(srcElem1)) 33147639Sgblack@eecs.umich.edu fpscr.idc = 1; 33157639Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(VfpRoundNearest); 33167639Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (srcElem1) : "m" (srcElem1)); 331710037SARM gem5 Developers destReg = vfpFpToFixed<float>(srcElem1, true, 32, imm); 33187639Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (destReg)); 33197639Sgblack@eecs.umich.edu finishVfp(fpscr, state, true); 33207783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 33217639Sgblack@eecs.umich.edu ''' 33227760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vcvt", "NVcvt2sfxD", "SimdCvtOp", ("float",), 33237639Sgblack@eecs.umich.edu 2, vcvt2sfxCode, toInt = True) 33247760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vcvt", "NVcvt2sfxQ", "SimdCvtOp", ("float",), 33257639Sgblack@eecs.umich.edu 4, vcvt2sfxCode, toInt = True) 33267639Sgblack@eecs.umich.edu 33277639Sgblack@eecs.umich.edu vcvtu2fpCode = ''' 33287783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 33297639Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(VfpRoundNearest); 33307639Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (srcReg1) : "m" (srcReg1)); 333110037SARM gem5 Developers destElem = vfpUFixedToFpS(true, true, srcReg1, 32, imm); 33327639Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (destElem)); 33337639Sgblack@eecs.umich.edu finishVfp(fpscr, state, true); 33347783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 33357639Sgblack@eecs.umich.edu ''' 33367760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vcvt", "NVcvtu2fpD", "SimdCvtOp", ("float",), 33377639Sgblack@eecs.umich.edu 2, vcvtu2fpCode, fromInt = True) 33387760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vcvt", "NVcvtu2fpQ", "SimdCvtOp", ("float",), 33397639Sgblack@eecs.umich.edu 4, vcvtu2fpCode, fromInt = True) 33407639Sgblack@eecs.umich.edu 33417639Sgblack@eecs.umich.edu vcvts2fpCode = ''' 33427783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 33437639Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(VfpRoundNearest); 33447639Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (srcReg1) : "m" (srcReg1)); 334510037SARM gem5 Developers destElem = vfpSFixedToFpS(true, true, srcReg1, 32, imm); 33467639Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (destElem)); 33477639Sgblack@eecs.umich.edu finishVfp(fpscr, state, true); 33487783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 33497639Sgblack@eecs.umich.edu ''' 33507760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vcvt", "NVcvts2fpD", "SimdCvtOp", ("float",), 33517639Sgblack@eecs.umich.edu 2, vcvts2fpCode, fromInt = True) 33527760SGiacomo.Gabrielli@arm.com twoRegShiftInst("vcvt", "NVcvts2fpQ", "SimdCvtOp", ("float",), 33537639Sgblack@eecs.umich.edu 4, vcvts2fpCode, fromInt = True) 33547639Sgblack@eecs.umich.edu 33557639Sgblack@eecs.umich.edu vcvts2hCode = ''' 33569557Sandreas.hansson@arm.com destElem = 0; 33577783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 33587639Sgblack@eecs.umich.edu float srcFp1 = bitsToFp(srcElem1, (float)0.0); 33597639Sgblack@eecs.umich.edu if (flushToZero(srcFp1)) 33607639Sgblack@eecs.umich.edu fpscr.idc = 1; 33617639Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(VfpRoundNearest); 33627639Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (srcFp1), "=m" (destElem) 33637639Sgblack@eecs.umich.edu : "m" (srcFp1), "m" (destElem)); 33647639Sgblack@eecs.umich.edu destElem = vcvtFpSFpH(fpscr, true, true, VfpRoundNearest, 33657639Sgblack@eecs.umich.edu fpscr.ahp, srcFp1); 33667639Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (destElem)); 33677639Sgblack@eecs.umich.edu finishVfp(fpscr, state, true); 33687783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 33697639Sgblack@eecs.umich.edu ''' 33707760SGiacomo.Gabrielli@arm.com twoRegNarrowMiscInst("vcvt", "NVcvts2h", "SimdCvtOp", ("uint16_t",), vcvts2hCode) 33717639Sgblack@eecs.umich.edu 33727639Sgblack@eecs.umich.edu vcvth2sCode = ''' 33739557Sandreas.hansson@arm.com destElem = 0; 33747783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 33757639Sgblack@eecs.umich.edu VfpSavedState state = prepFpState(VfpRoundNearest); 33767639Sgblack@eecs.umich.edu __asm__ __volatile__("" : "=m" (srcElem1), "=m" (destElem) 33777639Sgblack@eecs.umich.edu : "m" (srcElem1), "m" (destElem)); 33787639Sgblack@eecs.umich.edu destElem = fpToBits(vcvtFpHFpS(fpscr, true, fpscr.ahp, srcElem1)); 33797639Sgblack@eecs.umich.edu __asm__ __volatile__("" :: "m" (destElem)); 33807639Sgblack@eecs.umich.edu finishVfp(fpscr, state, true); 33817783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 33827639Sgblack@eecs.umich.edu ''' 33837760SGiacomo.Gabrielli@arm.com twoRegLongMiscInst("vcvt", "NVcvth2s", "SimdCvtOp", ("uint16_t",), vcvth2sCode) 33847639Sgblack@eecs.umich.edu 33857639Sgblack@eecs.umich.edu vrsqrteCode = ''' 33867639Sgblack@eecs.umich.edu destElem = unsignedRSqrtEstimate(srcElem1); 33877639Sgblack@eecs.umich.edu ''' 33887760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vrsqrte", "NVrsqrteD", "SimdSqrtOp", ("uint32_t",), 2, vrsqrteCode) 33897760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vrsqrte", "NVrsqrteQ", "SimdSqrtOp", ("uint32_t",), 4, vrsqrteCode) 33907639Sgblack@eecs.umich.edu 33917639Sgblack@eecs.umich.edu vrsqrtefpCode = ''' 33927783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 33937639Sgblack@eecs.umich.edu if (flushToZero(srcReg1)) 33947639Sgblack@eecs.umich.edu fpscr.idc = 1; 33957639Sgblack@eecs.umich.edu destReg = fprSqrtEstimate(fpscr, srcReg1); 33967783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 33977639Sgblack@eecs.umich.edu ''' 33987760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vrsqrte", "NVrsqrteDFp", "SimdFloatSqrtOp", ("float",), 2, vrsqrtefpCode) 33997760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vrsqrte", "NVrsqrteQFp", "SimdFloatSqrtOp", ("float",), 4, vrsqrtefpCode) 34007639Sgblack@eecs.umich.edu 34017639Sgblack@eecs.umich.edu vrecpeCode = ''' 34027639Sgblack@eecs.umich.edu destElem = unsignedRecipEstimate(srcElem1); 34037639Sgblack@eecs.umich.edu ''' 34047760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vrecpe", "NVrecpeD", "SimdMultAccOp", ("uint32_t",), 2, vrecpeCode) 34057760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vrecpe", "NVrecpeQ", "SimdMultAccOp", ("uint32_t",), 4, vrecpeCode) 34067639Sgblack@eecs.umich.edu 34077639Sgblack@eecs.umich.edu vrecpefpCode = ''' 34087783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 34097639Sgblack@eecs.umich.edu if (flushToZero(srcReg1)) 34107639Sgblack@eecs.umich.edu fpscr.idc = 1; 34117639Sgblack@eecs.umich.edu destReg = fpRecipEstimate(fpscr, srcReg1); 34127783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 34137639Sgblack@eecs.umich.edu ''' 34147760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vrecpe", "NVrecpeDFp", "SimdFloatMultAccOp", ("float",), 2, vrecpefpCode) 34157760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vrecpe", "NVrecpeQFp", "SimdFloatMultAccOp", ("float",), 4, vrecpefpCode) 34167639Sgblack@eecs.umich.edu 34177639Sgblack@eecs.umich.edu vrev16Code = ''' 34187639Sgblack@eecs.umich.edu destElem = srcElem1; 34197639Sgblack@eecs.umich.edu unsigned groupSize = ((1 << 1) / sizeof(Element)); 34207639Sgblack@eecs.umich.edu unsigned reverseMask = (groupSize - 1); 34217639Sgblack@eecs.umich.edu j = i ^ reverseMask; 34227639Sgblack@eecs.umich.edu ''' 34237760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vrev16", "NVrev16D", "SimdAluOp", ("uint8_t",), 2, vrev16Code) 34247760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vrev16", "NVrev16Q", "SimdAluOp", ("uint8_t",), 4, vrev16Code) 34257639Sgblack@eecs.umich.edu vrev32Code = ''' 34267639Sgblack@eecs.umich.edu destElem = srcElem1; 34277639Sgblack@eecs.umich.edu unsigned groupSize = ((1 << 2) / sizeof(Element)); 34287639Sgblack@eecs.umich.edu unsigned reverseMask = (groupSize - 1); 34297639Sgblack@eecs.umich.edu j = i ^ reverseMask; 34307639Sgblack@eecs.umich.edu ''' 34317639Sgblack@eecs.umich.edu twoRegMiscInst("vrev32", "NVrev32D", 34327760SGiacomo.Gabrielli@arm.com "SimdAluOp", ("uint8_t", "uint16_t"), 2, vrev32Code) 34337639Sgblack@eecs.umich.edu twoRegMiscInst("vrev32", "NVrev32Q", 34347760SGiacomo.Gabrielli@arm.com "SimdAluOp", ("uint8_t", "uint16_t"), 4, vrev32Code) 34357639Sgblack@eecs.umich.edu vrev64Code = ''' 34367639Sgblack@eecs.umich.edu destElem = srcElem1; 34377639Sgblack@eecs.umich.edu unsigned groupSize = ((1 << 3) / sizeof(Element)); 34387639Sgblack@eecs.umich.edu unsigned reverseMask = (groupSize - 1); 34397639Sgblack@eecs.umich.edu j = i ^ reverseMask; 34407639Sgblack@eecs.umich.edu ''' 34417760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vrev64", "NVrev64D", "SimdAluOp", smallUnsignedTypes, 2, vrev64Code) 34427760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vrev64", "NVrev64Q", "SimdAluOp", smallUnsignedTypes, 4, vrev64Code) 34437639Sgblack@eecs.umich.edu 344410197SCurtis.Dunham@arm.com split('exec') 344510197SCurtis.Dunham@arm.com exec_output += vcompares + vcomparesL 344610197SCurtis.Dunham@arm.com 34477639Sgblack@eecs.umich.edu vpaddlCode = ''' 34487639Sgblack@eecs.umich.edu destElem = (BigElement)srcElem1 + (BigElement)srcElem2; 34497639Sgblack@eecs.umich.edu ''' 34507760SGiacomo.Gabrielli@arm.com twoRegCondenseInst("vpaddl", "NVpaddlD", "SimdAddOp", smallTypes, 2, vpaddlCode) 34517760SGiacomo.Gabrielli@arm.com twoRegCondenseInst("vpaddl", "NVpaddlQ", "SimdAddOp", smallTypes, 4, vpaddlCode) 34527639Sgblack@eecs.umich.edu 34537639Sgblack@eecs.umich.edu vpadalCode = ''' 34547639Sgblack@eecs.umich.edu destElem += (BigElement)srcElem1 + (BigElement)srcElem2; 34557639Sgblack@eecs.umich.edu ''' 34567760SGiacomo.Gabrielli@arm.com twoRegCondenseInst("vpadal", "NVpadalD", "SimdAddAccOp", smallTypes, 2, vpadalCode, True) 34577760SGiacomo.Gabrielli@arm.com twoRegCondenseInst("vpadal", "NVpadalQ", "SimdAddAccOp", smallTypes, 4, vpadalCode, True) 34587639Sgblack@eecs.umich.edu 34597639Sgblack@eecs.umich.edu vclsCode = ''' 34607639Sgblack@eecs.umich.edu unsigned count = 0; 34617639Sgblack@eecs.umich.edu if (srcElem1 < 0) { 34627639Sgblack@eecs.umich.edu srcElem1 <<= 1; 34637639Sgblack@eecs.umich.edu while (srcElem1 < 0 && count < sizeof(Element) * 8 - 1) { 34647639Sgblack@eecs.umich.edu count++; 34657639Sgblack@eecs.umich.edu srcElem1 <<= 1; 34667639Sgblack@eecs.umich.edu } 34677639Sgblack@eecs.umich.edu } else { 34687639Sgblack@eecs.umich.edu srcElem1 <<= 1; 34697639Sgblack@eecs.umich.edu while (srcElem1 >= 0 && count < sizeof(Element) * 8 - 1) { 34707639Sgblack@eecs.umich.edu count++; 34717639Sgblack@eecs.umich.edu srcElem1 <<= 1; 34727639Sgblack@eecs.umich.edu } 34737639Sgblack@eecs.umich.edu } 34747639Sgblack@eecs.umich.edu destElem = count; 34757639Sgblack@eecs.umich.edu ''' 34767760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vcls", "NVclsD", "SimdAluOp", signedTypes, 2, vclsCode) 34777760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vcls", "NVclsQ", "SimdAluOp", signedTypes, 4, vclsCode) 34787639Sgblack@eecs.umich.edu 34797639Sgblack@eecs.umich.edu vclzCode = ''' 34807639Sgblack@eecs.umich.edu unsigned count = 0; 34817639Sgblack@eecs.umich.edu while (srcElem1 >= 0 && count < sizeof(Element) * 8) { 34827639Sgblack@eecs.umich.edu count++; 34837639Sgblack@eecs.umich.edu srcElem1 <<= 1; 34847639Sgblack@eecs.umich.edu } 34857639Sgblack@eecs.umich.edu destElem = count; 34867639Sgblack@eecs.umich.edu ''' 34877760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vclz", "NVclzD", "SimdAluOp", signedTypes, 2, vclzCode) 34887760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vclz", "NVclzQ", "SimdAluOp", signedTypes, 4, vclzCode) 34897639Sgblack@eecs.umich.edu 34907639Sgblack@eecs.umich.edu vcntCode = ''' 34917639Sgblack@eecs.umich.edu unsigned count = 0; 34927639Sgblack@eecs.umich.edu while (srcElem1 && count < sizeof(Element) * 8) { 34937639Sgblack@eecs.umich.edu count += srcElem1 & 0x1; 34947639Sgblack@eecs.umich.edu srcElem1 >>= 1; 34957639Sgblack@eecs.umich.edu } 34967639Sgblack@eecs.umich.edu destElem = count; 34977639Sgblack@eecs.umich.edu ''' 34987760SGiacomo.Gabrielli@arm.com 34997760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vcnt", "NVcntD", "SimdAluOp", unsignedTypes, 2, vcntCode) 35007760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vcnt", "NVcntQ", "SimdAluOp", unsignedTypes, 4, vcntCode) 35017639Sgblack@eecs.umich.edu 35027639Sgblack@eecs.umich.edu vmvnCode = ''' 35037639Sgblack@eecs.umich.edu destElem = ~srcElem1; 35047639Sgblack@eecs.umich.edu ''' 35057760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vmvn", "NVmvnD", "SimdAluOp", ("uint64_t",), 2, vmvnCode) 35067760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vmvn", "NVmvnQ", "SimdAluOp", ("uint64_t",), 4, vmvnCode) 35077639Sgblack@eecs.umich.edu 35087639Sgblack@eecs.umich.edu vqabsCode = ''' 35097783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 351012038Srekai.gonzalezalberquilla@arm.com if (srcElem1 == (Element)(std::numeric_limits<Element>::min())) { 35117639Sgblack@eecs.umich.edu fpscr.qc = 1; 35127639Sgblack@eecs.umich.edu destElem = ~srcElem1; 35137639Sgblack@eecs.umich.edu } else if (srcElem1 < 0) { 35147639Sgblack@eecs.umich.edu destElem = -srcElem1; 35157639Sgblack@eecs.umich.edu } else { 35167639Sgblack@eecs.umich.edu destElem = srcElem1; 35177639Sgblack@eecs.umich.edu } 35187783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 35197639Sgblack@eecs.umich.edu ''' 35207760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vqabs", "NVqabsD", "SimdAluOp", signedTypes, 2, vqabsCode) 35217760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vqabs", "NVqabsQ", "SimdAluOp", signedTypes, 4, vqabsCode) 35227639Sgblack@eecs.umich.edu 35237639Sgblack@eecs.umich.edu vqnegCode = ''' 35247783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 352512038Srekai.gonzalezalberquilla@arm.com if (srcElem1 == (Element)(std::numeric_limits<Element>::min())) { 35267639Sgblack@eecs.umich.edu fpscr.qc = 1; 35277639Sgblack@eecs.umich.edu destElem = ~srcElem1; 35287639Sgblack@eecs.umich.edu } else { 35297639Sgblack@eecs.umich.edu destElem = -srcElem1; 35307639Sgblack@eecs.umich.edu } 35317783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 35327639Sgblack@eecs.umich.edu ''' 35337760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vqneg", "NVqnegD", "SimdAluOp", signedTypes, 2, vqnegCode) 35347760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vqneg", "NVqnegQ", "SimdAluOp", signedTypes, 4, vqnegCode) 35357639Sgblack@eecs.umich.edu 35367639Sgblack@eecs.umich.edu vabsCode = ''' 35377639Sgblack@eecs.umich.edu if (srcElem1 < 0) { 35387639Sgblack@eecs.umich.edu destElem = -srcElem1; 35397639Sgblack@eecs.umich.edu } else { 35407639Sgblack@eecs.umich.edu destElem = srcElem1; 35417639Sgblack@eecs.umich.edu } 35427639Sgblack@eecs.umich.edu ''' 35437760SGiacomo.Gabrielli@arm.com 35447760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vabs", "NVabsD", "SimdAluOp", signedTypes, 2, vabsCode) 35457760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vabs", "NVabsQ", "SimdAluOp", signedTypes, 4, vabsCode) 35467639Sgblack@eecs.umich.edu vabsfpCode = ''' 35477639Sgblack@eecs.umich.edu union 35487639Sgblack@eecs.umich.edu { 35497639Sgblack@eecs.umich.edu uint32_t i; 35507639Sgblack@eecs.umich.edu float f; 35517639Sgblack@eecs.umich.edu } cStruct; 35527639Sgblack@eecs.umich.edu cStruct.f = srcReg1; 35537639Sgblack@eecs.umich.edu cStruct.i &= mask(sizeof(Element) * 8 - 1); 35547639Sgblack@eecs.umich.edu destReg = cStruct.f; 35557639Sgblack@eecs.umich.edu ''' 35567760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vabs", "NVabsDFp", "SimdFloatAluOp", ("float",), 2, vabsfpCode) 35577760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vabs", "NVabsQFp", "SimdFloatAluOp", ("float",), 4, vabsfpCode) 35587639Sgblack@eecs.umich.edu 35597639Sgblack@eecs.umich.edu vnegCode = ''' 35607639Sgblack@eecs.umich.edu destElem = -srcElem1; 35617639Sgblack@eecs.umich.edu ''' 35627760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vneg", "NVnegD", "SimdAluOp", signedTypes, 2, vnegCode) 35637760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vneg", "NVnegQ", "SimdAluOp", signedTypes, 4, vnegCode) 35647639Sgblack@eecs.umich.edu vnegfpCode = ''' 35657639Sgblack@eecs.umich.edu destReg = -srcReg1; 35667639Sgblack@eecs.umich.edu ''' 35677760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vneg", "NVnegDFp", "SimdFloatAluOp", ("float",), 2, vnegfpCode) 35687760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vneg", "NVnegQFp", "SimdFloatAluOp", ("float",), 4, vnegfpCode) 35697639Sgblack@eecs.umich.edu 35707639Sgblack@eecs.umich.edu vcgtCode = 'destElem = (srcElem1 > 0) ? mask(sizeof(Element) * 8) : 0;' 35717760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vcgt", "NVcgtD", "SimdCmpOp", signedTypes, 2, vcgtCode) 35727760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vcgt", "NVcgtQ", "SimdCmpOp", signedTypes, 4, vcgtCode) 35737639Sgblack@eecs.umich.edu vcgtfpCode = ''' 35747783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 357513544Sgabeblack@google.com float res = binaryOp(fpscr, srcReg1, (float)0.0, vcgtFunc, 35767639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 35777639Sgblack@eecs.umich.edu destReg = (res == 0) ? -1 : 0; 35787639Sgblack@eecs.umich.edu if (res == 2.0) 35797639Sgblack@eecs.umich.edu fpscr.ioc = 1; 35807783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 35817639Sgblack@eecs.umich.edu ''' 35827760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vcgt", "NVcgtDFp", "SimdFloatCmpOp", ("float",), 35837639Sgblack@eecs.umich.edu 2, vcgtfpCode, toInt = True) 35847760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vcgt", "NVcgtQFp", "SimdFloatCmpOp", ("float",), 35857639Sgblack@eecs.umich.edu 4, vcgtfpCode, toInt = True) 35867639Sgblack@eecs.umich.edu 35877639Sgblack@eecs.umich.edu vcgeCode = 'destElem = (srcElem1 >= 0) ? mask(sizeof(Element) * 8) : 0;' 35887760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vcge", "NVcgeD", "SimdCmpOp", signedTypes, 2, vcgeCode) 35897760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vcge", "NVcgeQ", "SimdCmpOp", signedTypes, 4, vcgeCode) 35907639Sgblack@eecs.umich.edu vcgefpCode = ''' 35917783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 359213544Sgabeblack@google.com float res = binaryOp(fpscr, srcReg1, (float)0.0, vcgeFunc, 35937639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 35947639Sgblack@eecs.umich.edu destReg = (res == 0) ? -1 : 0; 35957639Sgblack@eecs.umich.edu if (res == 2.0) 35967639Sgblack@eecs.umich.edu fpscr.ioc = 1; 35977783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 35987639Sgblack@eecs.umich.edu ''' 35997760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vcge", "NVcgeDFp", "SimdFloatCmpOp", ("float",), 36007639Sgblack@eecs.umich.edu 2, vcgefpCode, toInt = True) 36017760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vcge", "NVcgeQFp", "SimdFloatCmpOp", ("float",), 36027639Sgblack@eecs.umich.edu 4, vcgefpCode, toInt = True) 36037639Sgblack@eecs.umich.edu 36047639Sgblack@eecs.umich.edu vceqCode = 'destElem = (srcElem1 == 0) ? mask(sizeof(Element) * 8) : 0;' 36057760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vceq", "NVceqD", "SimdCmpOp", signedTypes, 2, vceqCode) 36067760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vceq", "NVceqQ", "SimdCmpOp", signedTypes, 4, vceqCode) 36077639Sgblack@eecs.umich.edu vceqfpCode = ''' 36087783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 360913544Sgabeblack@google.com float res = binaryOp(fpscr, srcReg1, (float)0.0, vceqFunc, 36107639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 36117639Sgblack@eecs.umich.edu destReg = (res == 0) ? -1 : 0; 36127639Sgblack@eecs.umich.edu if (res == 2.0) 36137639Sgblack@eecs.umich.edu fpscr.ioc = 1; 36147783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 36157639Sgblack@eecs.umich.edu ''' 36167760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vceq", "NVceqDFp", "SimdFloatCmpOp", ("float",), 36177639Sgblack@eecs.umich.edu 2, vceqfpCode, toInt = True) 36187760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vceq", "NVceqQFp", "SimdFloatCmpOp", ("float",), 36197639Sgblack@eecs.umich.edu 4, vceqfpCode, toInt = True) 36207639Sgblack@eecs.umich.edu 36217639Sgblack@eecs.umich.edu vcleCode = 'destElem = (srcElem1 <= 0) ? mask(sizeof(Element) * 8) : 0;' 36227760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vcle", "NVcleD", "SimdCmpOp", signedTypes, 2, vcleCode) 36237760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vcle", "NVcleQ", "SimdCmpOp", signedTypes, 4, vcleCode) 36247639Sgblack@eecs.umich.edu vclefpCode = ''' 36257783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 362613544Sgabeblack@google.com float res = binaryOp(fpscr, srcReg1, (float)0.0, vcleFunc, 36277639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 36287639Sgblack@eecs.umich.edu destReg = (res == 0) ? -1 : 0; 36297639Sgblack@eecs.umich.edu if (res == 2.0) 36307639Sgblack@eecs.umich.edu fpscr.ioc = 1; 36317783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 36327639Sgblack@eecs.umich.edu ''' 36337760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vcle", "NVcleDFp", "SimdFloatCmpOp", ("float",), 36347639Sgblack@eecs.umich.edu 2, vclefpCode, toInt = True) 36357760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vcle", "NVcleQFp", "SimdFloatCmpOp", ("float",), 36367639Sgblack@eecs.umich.edu 4, vclefpCode, toInt = True) 36377639Sgblack@eecs.umich.edu 36387639Sgblack@eecs.umich.edu vcltCode = 'destElem = (srcElem1 < 0) ? mask(sizeof(Element) * 8) : 0;' 36397760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vclt", "NVcltD", "SimdCmpOp", signedTypes, 2, vcltCode) 36407760SGiacomo.Gabrielli@arm.com twoRegMiscInst("vclt", "NVcltQ", "SimdCmpOp", signedTypes, 4, vcltCode) 36417639Sgblack@eecs.umich.edu vcltfpCode = ''' 36427783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrExc; 364313544Sgabeblack@google.com float res = binaryOp(fpscr, srcReg1, (float)0.0, vcltFunc, 36447639Sgblack@eecs.umich.edu true, true, VfpRoundNearest); 36457639Sgblack@eecs.umich.edu destReg = (res == 0) ? -1 : 0; 36467639Sgblack@eecs.umich.edu if (res == 2.0) 36477639Sgblack@eecs.umich.edu fpscr.ioc = 1; 36487783SGiacomo.Gabrielli@arm.com FpscrExc = fpscr; 36497639Sgblack@eecs.umich.edu ''' 36507760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vclt", "NVcltDFp", "SimdFloatCmpOp", ("float",), 36517639Sgblack@eecs.umich.edu 2, vcltfpCode, toInt = True) 36527760SGiacomo.Gabrielli@arm.com twoRegMiscInstFp("vclt", "NVcltQFp", "SimdFloatCmpOp", ("float",), 36537639Sgblack@eecs.umich.edu 4, vcltfpCode, toInt = True) 36547639Sgblack@eecs.umich.edu 36557639Sgblack@eecs.umich.edu vswpCode = ''' 365613544Sgabeblack@google.com uint32_t mid; 36577639Sgblack@eecs.umich.edu for (unsigned r = 0; r < rCount; r++) { 36587639Sgblack@eecs.umich.edu mid = srcReg1.regs[r]; 36597639Sgblack@eecs.umich.edu srcReg1.regs[r] = destReg.regs[r]; 36607639Sgblack@eecs.umich.edu destReg.regs[r] = mid; 36617639Sgblack@eecs.umich.edu } 36627639Sgblack@eecs.umich.edu ''' 36637760SGiacomo.Gabrielli@arm.com twoRegMiscScramble("vswp", "NVswpD", "SimdAluOp", ("uint64_t",), 2, vswpCode) 36647760SGiacomo.Gabrielli@arm.com twoRegMiscScramble("vswp", "NVswpQ", "SimdAluOp", ("uint64_t",), 4, vswpCode) 36657639Sgblack@eecs.umich.edu 36667639Sgblack@eecs.umich.edu vtrnCode = ''' 36677639Sgblack@eecs.umich.edu Element mid; 36687639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i += 2) { 36697639Sgblack@eecs.umich.edu mid = srcReg1.elements[i]; 36707639Sgblack@eecs.umich.edu srcReg1.elements[i] = destReg.elements[i + 1]; 36717639Sgblack@eecs.umich.edu destReg.elements[i + 1] = mid; 36727639Sgblack@eecs.umich.edu } 36737639Sgblack@eecs.umich.edu ''' 36748607Sgblack@eecs.umich.edu twoRegMiscScramble("vtrn", "NVtrnD", "SimdAluOp", 36758607Sgblack@eecs.umich.edu smallUnsignedTypes, 2, vtrnCode) 36768607Sgblack@eecs.umich.edu twoRegMiscScramble("vtrn", "NVtrnQ", "SimdAluOp", 36778607Sgblack@eecs.umich.edu smallUnsignedTypes, 4, vtrnCode) 36787639Sgblack@eecs.umich.edu 36797639Sgblack@eecs.umich.edu vuzpCode = ''' 36807639Sgblack@eecs.umich.edu Element mid[eCount]; 36817639Sgblack@eecs.umich.edu memcpy(&mid, &srcReg1, sizeof(srcReg1)); 36827639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount / 2; i++) { 36837639Sgblack@eecs.umich.edu srcReg1.elements[i] = destReg.elements[2 * i + 1]; 36847639Sgblack@eecs.umich.edu srcReg1.elements[eCount / 2 + i] = mid[2 * i + 1]; 36857639Sgblack@eecs.umich.edu destReg.elements[i] = destReg.elements[2 * i]; 36867639Sgblack@eecs.umich.edu } 36877639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount / 2; i++) { 36887639Sgblack@eecs.umich.edu destReg.elements[eCount / 2 + i] = mid[2 * i]; 36897639Sgblack@eecs.umich.edu } 36907639Sgblack@eecs.umich.edu ''' 36917760SGiacomo.Gabrielli@arm.com twoRegMiscScramble("vuzp", "NVuzpD", "SimdAluOp", unsignedTypes, 2, vuzpCode) 36927760SGiacomo.Gabrielli@arm.com twoRegMiscScramble("vuzp", "NVuzpQ", "SimdAluOp", unsignedTypes, 4, vuzpCode) 36937639Sgblack@eecs.umich.edu 36947639Sgblack@eecs.umich.edu vzipCode = ''' 36957639Sgblack@eecs.umich.edu Element mid[eCount]; 36967639Sgblack@eecs.umich.edu memcpy(&mid, &destReg, sizeof(destReg)); 36977639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount / 2; i++) { 36987639Sgblack@eecs.umich.edu destReg.elements[2 * i] = mid[i]; 36997639Sgblack@eecs.umich.edu destReg.elements[2 * i + 1] = srcReg1.elements[i]; 37007639Sgblack@eecs.umich.edu } 37017639Sgblack@eecs.umich.edu for (int i = 0; i < eCount / 2; i++) { 37027639Sgblack@eecs.umich.edu srcReg1.elements[2 * i] = mid[eCount / 2 + i]; 37037639Sgblack@eecs.umich.edu srcReg1.elements[2 * i + 1] = srcReg1.elements[eCount / 2 + i]; 37047639Sgblack@eecs.umich.edu } 37057639Sgblack@eecs.umich.edu ''' 37067760SGiacomo.Gabrielli@arm.com twoRegMiscScramble("vzip", "NVzipD", "SimdAluOp", unsignedTypes, 2, vzipCode) 37077760SGiacomo.Gabrielli@arm.com twoRegMiscScramble("vzip", "NVzipQ", "SimdAluOp", unsignedTypes, 4, vzipCode) 37087639Sgblack@eecs.umich.edu 37097639Sgblack@eecs.umich.edu vmovnCode = 'destElem = srcElem1;' 37107760SGiacomo.Gabrielli@arm.com twoRegNarrowMiscInst("vmovn", "NVmovn", "SimdMiscOp", smallUnsignedTypes, vmovnCode) 37117639Sgblack@eecs.umich.edu 37127639Sgblack@eecs.umich.edu vdupCode = 'destElem = srcElem1;' 37137760SGiacomo.Gabrielli@arm.com twoRegMiscScInst("vdup", "NVdupD", "SimdAluOp", smallUnsignedTypes, 2, vdupCode) 37147760SGiacomo.Gabrielli@arm.com twoRegMiscScInst("vdup", "NVdupQ", "SimdAluOp", smallUnsignedTypes, 4, vdupCode) 37157639Sgblack@eecs.umich.edu 37167760SGiacomo.Gabrielli@arm.com def vdupGprInst(name, Name, opClass, types, rCount): 37177639Sgblack@eecs.umich.edu global header_output, exec_output 371810829Sandreas.hansson@arm.com eWalkCode = simdEnabledCheckCode + ''' 37197639Sgblack@eecs.umich.edu RegVect destReg; 37207639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 37217639Sgblack@eecs.umich.edu destReg.elements[i] = htog((Element)Op1); 37227639Sgblack@eecs.umich.edu } 37237639Sgblack@eecs.umich.edu ''' 37247639Sgblack@eecs.umich.edu for reg in range(rCount): 37257639Sgblack@eecs.umich.edu eWalkCode += ''' 37268588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 37277639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 37287639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 37297639Sgblack@eecs.umich.edu "RegRegOp", 37307639Sgblack@eecs.umich.edu { "code": eWalkCode, 37317639Sgblack@eecs.umich.edu "r_count": rCount, 37327760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 37337760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 37347639Sgblack@eecs.umich.edu header_output += NeonRegRegOpDeclare.subst(iop) 37357639Sgblack@eecs.umich.edu exec_output += NeonEqualRegExecute.subst(iop) 37367639Sgblack@eecs.umich.edu for type in types: 37377639Sgblack@eecs.umich.edu substDict = { "targs" : type, 37387639Sgblack@eecs.umich.edu "class_name" : Name } 37397639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 37408206SWilliam.Wang@arm.com vdupGprInst("vdup", "NVdupDGpr", "SimdMiscOp", smallUnsignedTypes, 2) 37418206SWilliam.Wang@arm.com vdupGprInst("vdup", "NVdupQGpr", "SimdMiscOp", smallUnsignedTypes, 4) 37427639Sgblack@eecs.umich.edu 37437639Sgblack@eecs.umich.edu vmovCode = 'destElem = imm;' 37447760SGiacomo.Gabrielli@arm.com oneRegImmInst("vmov", "NVmoviD", "SimdMiscOp", ("uint64_t",), 2, vmovCode) 37457760SGiacomo.Gabrielli@arm.com oneRegImmInst("vmov", "NVmoviQ", "SimdMiscOp", ("uint64_t",), 4, vmovCode) 37467639Sgblack@eecs.umich.edu 37477639Sgblack@eecs.umich.edu vorrCode = 'destElem |= imm;' 37487760SGiacomo.Gabrielli@arm.com oneRegImmInst("vorr", "NVorriD", "SimdAluOp", ("uint64_t",), 2, vorrCode, True) 37497760SGiacomo.Gabrielli@arm.com oneRegImmInst("vorr", "NVorriQ", "SimdAluOp", ("uint64_t",), 4, vorrCode, True) 37507639Sgblack@eecs.umich.edu 37517639Sgblack@eecs.umich.edu vmvnCode = 'destElem = ~imm;' 37527760SGiacomo.Gabrielli@arm.com oneRegImmInst("vmvn", "NVmvniD", "SimdAluOp", ("uint64_t",), 2, vmvnCode) 37537760SGiacomo.Gabrielli@arm.com oneRegImmInst("vmvn", "NVmvniQ", "SimdAluOp", ("uint64_t",), 4, vmvnCode) 37547639Sgblack@eecs.umich.edu 37557639Sgblack@eecs.umich.edu vbicCode = 'destElem &= ~imm;' 37567760SGiacomo.Gabrielli@arm.com oneRegImmInst("vbic", "NVbiciD", "SimdAluOp", ("uint64_t",), 2, vbicCode, True) 37577760SGiacomo.Gabrielli@arm.com oneRegImmInst("vbic", "NVbiciQ", "SimdAluOp", ("uint64_t",), 4, vbicCode, True) 37587639Sgblack@eecs.umich.edu 37597639Sgblack@eecs.umich.edu vqmovnCode = ''' 37607783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 37617639Sgblack@eecs.umich.edu destElem = srcElem1; 37627639Sgblack@eecs.umich.edu if ((BigElement)destElem != srcElem1) { 37637639Sgblack@eecs.umich.edu fpscr.qc = 1; 37647639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8 - 1); 37657639Sgblack@eecs.umich.edu if (srcElem1 < 0) 37667639Sgblack@eecs.umich.edu destElem = ~destElem; 37677639Sgblack@eecs.umich.edu } 37687783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 37697639Sgblack@eecs.umich.edu ''' 37707760SGiacomo.Gabrielli@arm.com twoRegNarrowMiscInst("vqmovn", "NVqmovn", "SimdMiscOp", smallSignedTypes, vqmovnCode) 37717639Sgblack@eecs.umich.edu 37727639Sgblack@eecs.umich.edu vqmovunCode = ''' 37737783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 37747639Sgblack@eecs.umich.edu destElem = srcElem1; 37757639Sgblack@eecs.umich.edu if ((BigElement)destElem != srcElem1) { 37767639Sgblack@eecs.umich.edu fpscr.qc = 1; 37777639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8); 37787639Sgblack@eecs.umich.edu } 37797783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 37807639Sgblack@eecs.umich.edu ''' 37817639Sgblack@eecs.umich.edu twoRegNarrowMiscInst("vqmovun", "NVqmovun", 37827760SGiacomo.Gabrielli@arm.com "SimdMiscOp", smallUnsignedTypes, vqmovunCode) 37837639Sgblack@eecs.umich.edu 37847639Sgblack@eecs.umich.edu vqmovunsCode = ''' 37857783SGiacomo.Gabrielli@arm.com FPSCR fpscr = (FPSCR) FpscrQc; 37867639Sgblack@eecs.umich.edu destElem = srcElem1; 37877639Sgblack@eecs.umich.edu if (srcElem1 < 0 || 37887639Sgblack@eecs.umich.edu ((BigElement)destElem & mask(sizeof(Element) * 8)) != srcElem1) { 37897639Sgblack@eecs.umich.edu fpscr.qc = 1; 37907639Sgblack@eecs.umich.edu destElem = mask(sizeof(Element) * 8); 37917639Sgblack@eecs.umich.edu if (srcElem1 < 0) 37927639Sgblack@eecs.umich.edu destElem = ~destElem; 37937639Sgblack@eecs.umich.edu } 37947783SGiacomo.Gabrielli@arm.com FpscrQc = fpscr; 37957639Sgblack@eecs.umich.edu ''' 37967639Sgblack@eecs.umich.edu twoRegNarrowMiscInst("vqmovun", "NVqmovuns", 37977760SGiacomo.Gabrielli@arm.com "SimdMiscOp", smallSignedTypes, vqmovunsCode) 37987639Sgblack@eecs.umich.edu 37997760SGiacomo.Gabrielli@arm.com def buildVext(name, Name, opClass, types, rCount, op): 38007639Sgblack@eecs.umich.edu global header_output, exec_output 380110829Sandreas.hansson@arm.com eWalkCode = simdEnabledCheckCode + ''' 38027639Sgblack@eecs.umich.edu RegVect srcReg1, srcReg2, destReg; 38037639Sgblack@eecs.umich.edu ''' 38047639Sgblack@eecs.umich.edu for reg in range(rCount): 380510829Sandreas.hansson@arm.com eWalkCode += ''' 38068588Sgblack@eecs.umich.edu srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw); 38078588Sgblack@eecs.umich.edu srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d_uw); 38087639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 38097639Sgblack@eecs.umich.edu eWalkCode += op 38107639Sgblack@eecs.umich.edu for reg in range(rCount): 38117639Sgblack@eecs.umich.edu eWalkCode += ''' 38128588Sgblack@eecs.umich.edu FpDestP%(reg)d_uw = gtoh(destReg.regs[%(reg)d]); 38137639Sgblack@eecs.umich.edu ''' % { "reg" : reg } 38147639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 38157639Sgblack@eecs.umich.edu "RegRegRegImmOp", 38167639Sgblack@eecs.umich.edu { "code": eWalkCode, 38177639Sgblack@eecs.umich.edu "r_count": rCount, 38187760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 38197760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 38207639Sgblack@eecs.umich.edu header_output += NeonRegRegRegImmOpDeclare.subst(iop) 38217639Sgblack@eecs.umich.edu exec_output += NeonEqualRegExecute.subst(iop) 38227639Sgblack@eecs.umich.edu for type in types: 38237639Sgblack@eecs.umich.edu substDict = { "targs" : type, 38247639Sgblack@eecs.umich.edu "class_name" : Name } 38257639Sgblack@eecs.umich.edu exec_output += NeonExecDeclare.subst(substDict) 38267639Sgblack@eecs.umich.edu 38277639Sgblack@eecs.umich.edu vextCode = ''' 38287639Sgblack@eecs.umich.edu for (unsigned i = 0; i < eCount; i++) { 38297639Sgblack@eecs.umich.edu unsigned index = i + imm; 38307639Sgblack@eecs.umich.edu if (index < eCount) { 38317639Sgblack@eecs.umich.edu destReg.elements[i] = srcReg1.elements[index]; 38327639Sgblack@eecs.umich.edu } else { 38337639Sgblack@eecs.umich.edu index -= eCount; 38348782Sgblack@eecs.umich.edu if (index >= eCount) { 383510474Sandreas.hansson@arm.com fault = std::make_shared<UndefinedInstruction>(machInst, 383610474Sandreas.hansson@arm.com false, 383710474Sandreas.hansson@arm.com mnemonic); 38388782Sgblack@eecs.umich.edu } else { 38397853SMatt.Horsnell@ARM.com destReg.elements[i] = srcReg2.elements[index]; 38408782Sgblack@eecs.umich.edu } 38417639Sgblack@eecs.umich.edu } 38427639Sgblack@eecs.umich.edu } 38437639Sgblack@eecs.umich.edu ''' 38448206SWilliam.Wang@arm.com buildVext("vext", "NVextD", "SimdMiscOp", ("uint8_t",), 2, vextCode) 38458206SWilliam.Wang@arm.com buildVext("vext", "NVextQ", "SimdMiscOp", ("uint8_t",), 4, vextCode) 38467639Sgblack@eecs.umich.edu 38477760SGiacomo.Gabrielli@arm.com def buildVtbxl(name, Name, opClass, length, isVtbl): 38487639Sgblack@eecs.umich.edu global header_output, decoder_output, exec_output 384910829Sandreas.hansson@arm.com code = simdEnabledCheckCode + ''' 38507639Sgblack@eecs.umich.edu union 38517639Sgblack@eecs.umich.edu { 38527639Sgblack@eecs.umich.edu uint8_t bytes[32]; 385313544Sgabeblack@google.com uint32_t regs[8]; 38547639Sgblack@eecs.umich.edu } table; 38557639Sgblack@eecs.umich.edu 38567639Sgblack@eecs.umich.edu union 38577639Sgblack@eecs.umich.edu { 38587639Sgblack@eecs.umich.edu uint8_t bytes[8]; 385913544Sgabeblack@google.com uint32_t regs[2]; 38607639Sgblack@eecs.umich.edu } destReg, srcReg2; 38617639Sgblack@eecs.umich.edu 38627639Sgblack@eecs.umich.edu const unsigned length = %(length)d; 38637639Sgblack@eecs.umich.edu const bool isVtbl = %(isVtbl)s; 38647639Sgblack@eecs.umich.edu 38658588Sgblack@eecs.umich.edu srcReg2.regs[0] = htog(FpOp2P0_uw); 38668588Sgblack@eecs.umich.edu srcReg2.regs[1] = htog(FpOp2P1_uw); 38677639Sgblack@eecs.umich.edu 38688588Sgblack@eecs.umich.edu destReg.regs[0] = htog(FpDestP0_uw); 38698588Sgblack@eecs.umich.edu destReg.regs[1] = htog(FpDestP1_uw); 38707639Sgblack@eecs.umich.edu ''' % { "length" : length, "isVtbl" : isVtbl } 38717639Sgblack@eecs.umich.edu for reg in range(8): 38727639Sgblack@eecs.umich.edu if reg < length * 2: 38738588Sgblack@eecs.umich.edu code += 'table.regs[%(reg)d] = htog(FpOp1P%(reg)d_uw);\n' % \ 38747639Sgblack@eecs.umich.edu { "reg" : reg } 38757639Sgblack@eecs.umich.edu else: 38767639Sgblack@eecs.umich.edu code += 'table.regs[%(reg)d] = 0;\n' % { "reg" : reg } 38777639Sgblack@eecs.umich.edu code += ''' 38787639Sgblack@eecs.umich.edu for (unsigned i = 0; i < sizeof(destReg); i++) { 38797639Sgblack@eecs.umich.edu uint8_t index = srcReg2.bytes[i]; 38807639Sgblack@eecs.umich.edu if (index < 8 * length) { 38817639Sgblack@eecs.umich.edu destReg.bytes[i] = table.bytes[index]; 38827639Sgblack@eecs.umich.edu } else { 38837639Sgblack@eecs.umich.edu if (isVtbl) 38847639Sgblack@eecs.umich.edu destReg.bytes[i] = 0; 38857639Sgblack@eecs.umich.edu // else destReg.bytes[i] unchanged 38867639Sgblack@eecs.umich.edu } 38877639Sgblack@eecs.umich.edu } 38887639Sgblack@eecs.umich.edu 38898588Sgblack@eecs.umich.edu FpDestP0_uw = gtoh(destReg.regs[0]); 38908588Sgblack@eecs.umich.edu FpDestP1_uw = gtoh(destReg.regs[1]); 38917639Sgblack@eecs.umich.edu ''' 38927639Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 38937639Sgblack@eecs.umich.edu "RegRegRegOp", 38947639Sgblack@eecs.umich.edu { "code": code, 38957760SGiacomo.Gabrielli@arm.com "predicate_test": predicateTest, 38967760SGiacomo.Gabrielli@arm.com "op_class": opClass }, []) 38977639Sgblack@eecs.umich.edu header_output += RegRegRegOpDeclare.subst(iop) 38987639Sgblack@eecs.umich.edu decoder_output += RegRegRegOpConstructor.subst(iop) 38997639Sgblack@eecs.umich.edu exec_output += PredOpExecute.subst(iop) 39007639Sgblack@eecs.umich.edu 39018206SWilliam.Wang@arm.com buildVtbxl("vtbl", "NVtbl1", "SimdMiscOp", 1, "true") 39028206SWilliam.Wang@arm.com buildVtbxl("vtbl", "NVtbl2", "SimdMiscOp", 2, "true") 39038206SWilliam.Wang@arm.com buildVtbxl("vtbl", "NVtbl3", "SimdMiscOp", 3, "true") 39048206SWilliam.Wang@arm.com buildVtbxl("vtbl", "NVtbl4", "SimdMiscOp", 4, "true") 39057639Sgblack@eecs.umich.edu 39068206SWilliam.Wang@arm.com buildVtbxl("vtbx", "NVtbx1", "SimdMiscOp", 1, "false") 39078206SWilliam.Wang@arm.com buildVtbxl("vtbx", "NVtbx2", "SimdMiscOp", 2, "false") 39088206SWilliam.Wang@arm.com buildVtbxl("vtbx", "NVtbx3", "SimdMiscOp", 3, "false") 39098206SWilliam.Wang@arm.com buildVtbxl("vtbx", "NVtbx4", "SimdMiscOp", 4, "false") 39107639Sgblack@eecs.umich.edu}}; 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