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/gem5/src/kern/linux/
H A Devents.hhdiff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info
/gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/
H A Dconfig.inidiff 9924:31ef410b6843 Wed Oct 16 10:44:00 EDT 2013 Steve Reinhardt <steve.reinhardt@amd.com> test: update stats

Update stats for recent changes. Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
H A Dsimoutdiff 9924:31ef410b6843 Wed Oct 16 10:44:00 EDT 2013 Steve Reinhardt <steve.reinhardt@amd.com> test: update stats

Update stats for recent changes. Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
/gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/
H A Dconfig.inidiff 9924:31ef410b6843 Wed Oct 16 10:44:00 EDT 2013 Steve Reinhardt <steve.reinhardt@amd.com> test: update stats

Update stats for recent changes. Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
H A Dsimoutdiff 9924:31ef410b6843 Wed Oct 16 10:44:00 EDT 2013 Steve Reinhardt <steve.reinhardt@amd.com> test: update stats

Update stats for recent changes. Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
/gem5/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/
H A Dconfig.inidiff 9924:31ef410b6843 Wed Oct 16 10:44:00 EDT 2013 Steve Reinhardt <steve.reinhardt@amd.com> test: update stats

Update stats for recent changes. Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
H A Dsimoutdiff 9924:31ef410b6843 Wed Oct 16 10:44:00 EDT 2013 Steve Reinhardt <steve.reinhardt@amd.com> test: update stats

Update stats for recent changes. Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
/gem5/tests/quick/se/00.hello/ref/mips/linux/o3-timing/
H A Dconfig.inidiff 9924:31ef410b6843 Wed Oct 16 10:44:00 EDT 2013 Steve Reinhardt <steve.reinhardt@amd.com> test: update stats

Update stats for recent changes. Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
H A Dsimoutdiff 9924:31ef410b6843 Wed Oct 16 10:44:00 EDT 2013 Steve Reinhardt <steve.reinhardt@amd.com> test: update stats

Update stats for recent changes. Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
/gem5/src/base/loader/
H A Daout_object.ccdiff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info
/gem5/src/cpu/o3/
H A Dfree_list.ccdiff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info
/gem5/src/cpu/
H A Dprofile.ccdiff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info
/gem5/src/sim/
H A Ddebug.ccdiff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info
H A Dstat_control.hhdiff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info
/gem5/tests/configs/
H A Do3-timing-mp.pydiff 9489:172dbcb74a0e Thu Jan 31 07:49:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> mem: Add DDR3 and LPDDR2 DRAM controller configurations

This patch moves the default DRAM parameters from the SimpleDRAM class
to two different subclasses, one for DDR3 and one for LPDDR2. More can
be added as we go forward.

The regressions that previously used the SimpleDRAM are now using
SimpleDDR3 as this is the most similar configuration.
diff 9036:6385cf85bf12 Thu May 31 13:30:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> Bus: Split the bus into a non-coherent and coherent bus

This patch introduces a class hierarchy of buses, a non-coherent one,
and a coherent one, splitting the existing bus functionality. By doing
so it also enables further specialisation of the two types of buses.

A non-coherent bus connects a number of non-snooping masters and
slaves, and routes the request and response packets based on the
address. The request packets issued by the master connected to a
non-coherent bus could still snoop in caches attached to a coherent
bus, as is the case with the I/O bus and memory bus in most system
configurations. No snoops will, however, reach any master on the
non-coherent bus itself. The non-coherent bus can be used as a
template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses,
and is typically used for the I/O buses.

A coherent bus connects a number of (potentially) snooping masters and
slaves, and routes the request and response packets based on the
address, and also forwards all requests to the snoopers and deals with
the snoop responses. The coherent bus can be used as a template for
modelling QPI, HyperTransport, ACE and coherent OCP buses, and is
typically used for the L1-to-L2 buses and as the main system
interconnect.

The configuration scripts are updated to use a NoncoherentBus for all
peripheral and I/O buses.

A bit of minor tidying up has also been done.
diff 3402:db60546818d0 Tue Oct 31 14:33:00 EST 2006 Kevin Lim <ktlim@umich.edu> Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject.

configs/example/fs.py:
configs/example/se.py:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.cc:
src/cpu/thread_state.hh:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing-mp.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
No need for mem parameter any more.
src/cpu/checker/cpu.cc:
Use new constructor for simple thread (no more MemObject parameter).
src/cpu/checker/cpu.hh:
Remove MemObject parameter.
src/cpu/memtest/memtest.hh:
Ports now take in their MemObject owner.
src/cpu/o3/alpha/cpu_builder.cc:
Remove mem parameter.
src/cpu/o3/alpha/cpu_impl.hh:
Remove memory parameter and clean up handling of TranslatingPort.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/params.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_builder.cc:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/simple_params.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/atomic.cc:
Remove memory parameter.
diff 3200:4b072dcc7a57 Mon Oct 09 17:31:00 EDT 2006 Ron Dreslinski <rdreslin@umich.edu> Update configs for cpu_id

tests/configs/o3-timing-mp.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-timing-mp.py:
Update config for cpu_id
/gem5/src/arch/mips/linux/
H A Dprocess.hhdiff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info
/gem5/src/arch/x86/isa/decoder/
H A Done_byte_opcodes.isadiff 4814:d398decc8de8 Mon Jul 30 16:31:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Hook in the new instructions.
diff 4545:03725ca8b7ea Tue Jun 12 12:31:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add in MOV instructions.
diff 4482:7ca486cfc7a6 Thu May 31 09:50:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> x86 work that hadn't been checked in.

src/arch/x86/isa/decoder/one_byte_opcodes.isa:
Give the "MOV" instruction the format of it's arguments. This will likely need to be completely overhauled in the near future.
src/arch/x86/predecoder.cc:
src/arch/x86/predecoder.hh:
Make the predecoder explicitly reset itself rather than counting on it happening naturally.
src/arch/x86/predecoder_tables.cc:
Fix the immediate size table
src/arch/x86/regfile.cc:
nextnpc is bogus
diff 4336:bd6ab22f8e11 Wed Apr 04 10:31:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Reworking how x86's isa description works. I'm adopting the following definitions to make figuring out what's what a little easier:

MicroOp: A single operation actually implemented in hardware.
MacroOp: A collection of microops which are executed as a unit.
Instruction: An architected instruction which can be implemented with a macroop or a microop.
/gem5/tests/long/se/10.mcf/ref/arm/linux/o3-timing/
H A Dconfig.inidiff 9924:31ef410b6843 Wed Oct 16 10:44:00 EDT 2013 Steve Reinhardt <steve.reinhardt@amd.com> test: update stats

Update stats for recent changes. Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
H A Dsimoutdiff 9924:31ef410b6843 Wed Oct 16 10:44:00 EDT 2013 Steve Reinhardt <steve.reinhardt@amd.com> test: update stats

Update stats for recent changes. Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
/gem5/tests/long/se/10.mcf/ref/x86/linux/o3-timing/
H A Dconfig.inidiff 9924:31ef410b6843 Wed Oct 16 10:44:00 EDT 2013 Steve Reinhardt <steve.reinhardt@amd.com> test: update stats

Update stats for recent changes. Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
H A Dsimoutdiff 9924:31ef410b6843 Wed Oct 16 10:44:00 EDT 2013 Steve Reinhardt <steve.reinhardt@amd.com> test: update stats

Update stats for recent changes. Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
/gem5/tests/long/se/20.parser/ref/arm/linux/o3-timing/
H A Dsimoutdiff 9924:31ef410b6843 Wed Oct 16 10:44:00 EDT 2013 Steve Reinhardt <steve.reinhardt@amd.com> test: update stats

Update stats for recent changes. Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
/gem5/tests/long/se/20.parser/ref/x86/linux/o3-timing/
H A Dconfig.inidiff 9924:31ef410b6843 Wed Oct 16 10:44:00 EDT 2013 Steve Reinhardt <steve.reinhardt@amd.com> test: update stats

Update stats for recent changes. Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
/gem5/tests/long/se/20.parser/ref/x86/linux/simple-timing/
H A Dsimoutdiff 9924:31ef410b6843 Wed Oct 16 10:44:00 EDT 2013 Steve Reinhardt <steve.reinhardt@amd.com> test: update stats

Update stats for recent changes. Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
/gem5/tests/long/se/30.eon/ref/arm/linux/o3-timing/
H A Dsimoutdiff 9924:31ef410b6843 Wed Oct 16 10:44:00 EDT 2013 Steve Reinhardt <steve.reinhardt@amd.com> test: update stats

Update stats for recent changes. Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.

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