12SN/A/* 21762SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292665Ssaidi@eecs.umich.edu * Steve Reinhardt 302SN/A */ 312SN/A 3211793Sbrandon.potter@amd.com#include "sim/debug.hh" 3311793Sbrandon.potter@amd.com 342SN/A#include <string> 352SN/A#include <vector> 362SN/A 375882Snate@binkert.org#include "base/debug.hh" 3811793Sbrandon.potter@amd.com#include "cpu/pc_event.hh" 399356Snilay@cs.wisc.edu#include "sim/eventq_impl.hh" 409983Sstever@gmail.com#include "sim/global_event.hh" 4156SN/A#include "sim/sim_events.hh" 428278SAli.Saidi@ARM.com#include "sim/sim_exit.hh" 4311157SDylan.Johnson@ARM.com#include "sim/system.hh" 442SN/A 452SN/Ausing namespace std; 462SN/A 472SN/A// 482SN/A// Debug event: place a breakpoint on the process function and 492SN/A// schedule the event to break at a particular cycle 502SN/A// 519983Sstever@gmail.comstruct DebugBreakEvent : public GlobalEvent 522SN/A{ 539983Sstever@gmail.com DebugBreakEvent(Tick when); 545543Ssaidi@eecs.umich.edu void process(); // process event 555336Shines@cs.fsu.edu virtual const char *description() const; 562SN/A}; 572SN/A 582SN/A// 592SN/A// constructor: schedule at specified time 602SN/A// 619983Sstever@gmail.comDebugBreakEvent::DebugBreakEvent(Tick when) 629983Sstever@gmail.com : GlobalEvent(when, Debug_Break_Pri, AutoDelete) 632SN/A{ 642SN/A} 652SN/A 662SN/A// 672SN/A// handle debug event: set debugger breakpoint on this function 682SN/A// 692SN/Avoid 702SN/ADebugBreakEvent::process() 712SN/A{ 728231Snate@binkert.org Debug::breakpoint(); 732SN/A} 742SN/A 752SN/A 762SN/Aconst char * 775336Shines@cs.fsu.eduDebugBreakEvent::description() const 782SN/A{ 798231Snate@binkert.org return "debug breakpoint"; 802SN/A} 812SN/A 822SN/A// 832SN/A// handy function to schedule DebugBreakEvent on main event queue 842SN/A// (callable from debugger) 852SN/A// 863645Sbinkertn@umich.eduvoid 879960Sandreas.hansson@arm.comschedBreak(Tick when) 882SN/A{ 899983Sstever@gmail.com new DebugBreakEvent(when); 905606Snate@binkert.org warn("need to stop all queues"); 912SN/A} 922SN/A 9311157SDylan.Johnson@ARM.comvoid 9411164SDylan.Johnson@ARM.comschedRelBreak(Tick delta) 9511164SDylan.Johnson@ARM.com{ 9611164SDylan.Johnson@ARM.com schedBreak(curTick() + delta); 9711164SDylan.Johnson@ARM.com} 9811164SDylan.Johnson@ARM.com 9911164SDylan.Johnson@ARM.comvoid 10011157SDylan.Johnson@ARM.combreakAtKernelFunction(const char* funcName) 10111157SDylan.Johnson@ARM.com{ 10211157SDylan.Johnson@ARM.com System* curSystem = System::systemList[0]; 10311157SDylan.Johnson@ARM.com curSystem->addKernelFuncEvent<BreakPCEvent>(funcName, 10411157SDylan.Johnson@ARM.com "GDB scheduled break", true); 10511157SDylan.Johnson@ARM.com} 10611157SDylan.Johnson@ARM.com 1078278SAli.Saidi@ARM.com/// 1088278SAli.Saidi@ARM.com/// Function to cause the simulator to take a checkpoint from the debugger 1098278SAli.Saidi@ARM.com/// 1108278SAli.Saidi@ARM.comvoid 1118278SAli.Saidi@ARM.comtakeCheckpoint(Tick when) 1128278SAli.Saidi@ARM.com{ 1138278SAli.Saidi@ARM.com if (!when) 1148278SAli.Saidi@ARM.com when = curTick() + 1; 1158278SAli.Saidi@ARM.com exitSimLoop("checkpoint", 0, when, 0); 1168278SAli.Saidi@ARM.com} 1178278SAli.Saidi@ARM.com 1183645Sbinkertn@umich.eduvoid 1193645Sbinkertn@umich.edueventqDump() 1202SN/A{ 1219983Sstever@gmail.com for (uint32_t i = 0; i < numMainEventQueues; ++i) { 1229983Sstever@gmail.com mainEventQueue[i]->dump(); 1239983Sstever@gmail.com } 1242SN/A} 1252SN/A 1265512SMichael.Adler@intel.comint remote_gdb_base_port = 7000; 1275512SMichael.Adler@intel.com 1285512SMichael.Adler@intel.comint 1295512SMichael.Adler@intel.comgetRemoteGDBPort() 1305512SMichael.Adler@intel.com{ 1315512SMichael.Adler@intel.com return remote_gdb_base_port; 1325512SMichael.Adler@intel.com} 1335512SMichael.Adler@intel.com 1345512SMichael.Adler@intel.com// Set remote GDB base port. 0 means disable remote GDB. 1355512SMichael.Adler@intel.com// Callable from python. 1365512SMichael.Adler@intel.comvoid 1375512SMichael.Adler@intel.comsetRemoteGDBPort(int port) 1385512SMichael.Adler@intel.com{ 1395512SMichael.Adler@intel.com remote_gdb_base_port = port; 1405512SMichael.Adler@intel.com} 1415512SMichael.Adler@intel.com 142