1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=LinuxAlphaSystem 13children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 dvfs_handler intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain 14boot_cpu_frequency=500 15boot_osflags=root=/dev/hda1 console=ttyS0 16cache_line_size=64 17clk_domain=system.clk_domain 18console=/arm/projectscratch/randd/systems/dist/binaries/console 19default_p_state=UNDEFINED 20eventq_index=0 21exit_on_work_items=false 22init_param=0 23kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux 24kernel_addr_check=true 25load_addr_mask=1099511627775 26load_offset=0 27mem_mode=timing 28mem_ranges=0:134217727:0:0:0:0 29memories=system.physmem 30mmap_using_noreserve=false 31multi_thread=false 32num_work_ids=16 33p_state_clk_gate_bins=20 34p_state_clk_gate_max=1000000000000 35p_state_clk_gate_min=1000 36pal=/arm/projectscratch/randd/systems/dist/binaries/ts_osfpal 37power_model=Null 38readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh 39symbolfile= 40system_rev=1024 41system_type=34 42thermal_components= 43thermal_model=Null 44work_begin_ckpt_count=0 45work_begin_cpu_id_exit=-1 46work_begin_exit_count=0 47work_cpus_ckpt_count=0 48work_end_ckpt_count=0 49work_end_exit_count=0 50work_item_id=-1 51system_port=system.membus.slave[0] 52 53[system.bridge] 54type=Bridge 55clk_domain=system.clk_domain 56default_p_state=UNDEFINED 57delay=50000 58eventq_index=0 59p_state_clk_gate_bins=20 60p_state_clk_gate_max=1000000000000 61p_state_clk_gate_min=1000 62power_model=Null 63ranges=8796093022208:18446744073709551615:0:0:0:0 64req_size=16 65resp_size=16 66master=system.iobus.slave[0] 67slave=system.membus.master[0] 68 69[system.clk_domain] 70type=SrcClockDomain 71clock=1000 72domain_id=-1 73eventq_index=0 74init_perf_level=0 75voltage_domain=system.voltage_domain 76 77[system.cpu] 78type=DerivO3CPU 79children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer 80LFSTSize=1024 81LQEntries=32 82LSQCheckLoads=true 83LSQDepCheckShift=4 84SQEntries=32 85SSITSize=1024 86activity=0 87backComSize=5 88branchPred=system.cpu.branchPred 89cachePorts=200 90checker=Null 91clk_domain=system.cpu_clk_domain 92commitToDecodeDelay=1 93commitToFetchDelay=1 94commitToIEWDelay=1 95commitToRenameDelay=1 96commitWidth=8 97cpu_id=0 98decodeToFetchDelay=1 99decodeToRenameDelay=1 100decodeWidth=8 101default_p_state=UNDEFINED 102dispatchWidth=8 103do_checkpoint_insts=true 104do_quiesce=true 105do_statistics_insts=true 106dtb=system.cpu.dtb 107eventq_index=0 108fetchBufferSize=64 109fetchQueueSize=32 110fetchToDecodeDelay=1 111fetchTrapLatency=1 112fetchWidth=8 113forwardComSize=5 114fuPool=system.cpu.fuPool 115function_trace=false 116function_trace_start=0 117iewToCommitDelay=1 118iewToDecodeDelay=1 119iewToFetchDelay=1 120iewToRenameDelay=1 121interrupts=system.cpu.interrupts 122isa=system.cpu.isa 123issueToExecuteDelay=1 124issueWidth=8 125itb=system.cpu.itb 126max_insts_all_threads=0 127max_insts_any_thread=0 128max_loads_all_threads=0 129max_loads_any_thread=0 130needsTSO=false 131numIQEntries=64 132numPhysCCRegs=0 133numPhysFloatRegs=256 134numPhysIntRegs=256 135numROBEntries=192 136numRobs=1 137numThreads=1 138p_state_clk_gate_bins=20 139p_state_clk_gate_max=1000000000000 140p_state_clk_gate_min=1000 141power_model=Null 142profile=0 143progress_interval=0 144renameToDecodeDelay=1 145renameToFetchDelay=1 146renameToIEWDelay=2 147renameToROBDelay=1 148renameWidth=8 149simpoint_start_insts= 150smtCommitPolicy=RoundRobin 151smtFetchPolicy=SingleThread 152smtIQPolicy=Partitioned 153smtIQThreshold=100 154smtLSQPolicy=Partitioned 155smtLSQThreshold=100 156smtNumFetchingThreads=1 157smtROBPolicy=Partitioned 158smtROBThreshold=100 159socket_id=0 160squashWidth=8 161store_set_clear_period=250000 162switched_out=false 163system=system 164tracer=system.cpu.tracer 165trapLatency=13 166wbWidth=8 167workload= 168dcache_port=system.cpu.dcache.cpu_side 169icache_port=system.cpu.icache.cpu_side 170 171[system.cpu.branchPred] 172type=TournamentBP 173BTBEntries=4096 174BTBTagSize=16 175RASSize=16 176choiceCtrBits=2 177choicePredictorSize=8192 178eventq_index=0 179globalCtrBits=2 180globalPredictorSize=8192 181indirectHashGHR=true 182indirectHashTargets=true 183indirectPathLength=3 184indirectSets=256 185indirectTagSize=16 186indirectWays=2 187instShiftAmt=2 188localCtrBits=2 189localHistoryTableSize=2048 190localPredictorSize=2048 191numThreads=1 192useIndirect=true 193 194[system.cpu.dcache] 195type=Cache 196children=tags 197addr_ranges=0:18446744073709551615:0:0:0:0 198assoc=4 199clk_domain=system.cpu_clk_domain 200clusivity=mostly_incl 201default_p_state=UNDEFINED 202demand_mshr_reserve=1 203eventq_index=0 204hit_latency=2 205is_read_only=false 206max_miss_count=0 207mshrs=4 208p_state_clk_gate_bins=20 209p_state_clk_gate_max=1000000000000 210p_state_clk_gate_min=1000 211power_model=Null 212prefetch_on_access=false 213prefetcher=Null 214response_latency=2 215sequential_access=false 216size=32768 217system=system 218tags=system.cpu.dcache.tags 219tgts_per_mshr=20 220write_buffers=8 221writeback_clean=false 222cpu_side=system.cpu.dcache_port 223mem_side=system.cpu.toL2Bus.slave[1] 224 225[system.cpu.dcache.tags] 226type=LRU 227assoc=4 228block_size=64 229clk_domain=system.cpu_clk_domain 230default_p_state=UNDEFINED 231eventq_index=0 232hit_latency=2 233p_state_clk_gate_bins=20 234p_state_clk_gate_max=1000000000000 235p_state_clk_gate_min=1000 236power_model=Null 237sequential_access=false 238size=32768 239 240[system.cpu.dtb] 241type=AlphaTLB 242eventq_index=0 243size=64 244 245[system.cpu.fuPool] 246type=FUPool 247children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 248FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 249eventq_index=0 250 251[system.cpu.fuPool.FUList0] 252type=FUDesc 253children=opList 254count=6 255eventq_index=0 256opList=system.cpu.fuPool.FUList0.opList 257 258[system.cpu.fuPool.FUList0.opList] 259type=OpDesc 260eventq_index=0 261opClass=IntAlu 262opLat=1 263pipelined=true 264 265[system.cpu.fuPool.FUList1] 266type=FUDesc 267children=opList0 opList1 268count=2 269eventq_index=0 270opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 271 272[system.cpu.fuPool.FUList1.opList0] 273type=OpDesc 274eventq_index=0 275opClass=IntMult 276opLat=3 277pipelined=true 278 279[system.cpu.fuPool.FUList1.opList1] 280type=OpDesc 281eventq_index=0 282opClass=IntDiv 283opLat=20 284pipelined=false 285 286[system.cpu.fuPool.FUList2] 287type=FUDesc 288children=opList0 opList1 opList2 289count=4 290eventq_index=0 291opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 292 293[system.cpu.fuPool.FUList2.opList0] 294type=OpDesc 295eventq_index=0 296opClass=FloatAdd 297opLat=2 298pipelined=true 299 300[system.cpu.fuPool.FUList2.opList1] 301type=OpDesc 302eventq_index=0 303opClass=FloatCmp 304opLat=2 305pipelined=true 306 307[system.cpu.fuPool.FUList2.opList2] 308type=OpDesc 309eventq_index=0 310opClass=FloatCvt 311opLat=2 312pipelined=true 313 314[system.cpu.fuPool.FUList3] 315type=FUDesc 316children=opList0 opList1 opList2 317count=2 318eventq_index=0 319opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 320 321[system.cpu.fuPool.FUList3.opList0] 322type=OpDesc 323eventq_index=0 324opClass=FloatMult 325opLat=4 326pipelined=true 327 328[system.cpu.fuPool.FUList3.opList1] 329type=OpDesc 330eventq_index=0 331opClass=FloatDiv 332opLat=12 333pipelined=false 334 335[system.cpu.fuPool.FUList3.opList2] 336type=OpDesc 337eventq_index=0 338opClass=FloatSqrt 339opLat=24 340pipelined=false 341 342[system.cpu.fuPool.FUList4] 343type=FUDesc 344children=opList 345count=0 346eventq_index=0 347opList=system.cpu.fuPool.FUList4.opList 348 349[system.cpu.fuPool.FUList4.opList] 350type=OpDesc 351eventq_index=0 352opClass=MemRead 353opLat=1 354pipelined=true 355 356[system.cpu.fuPool.FUList5] 357type=FUDesc 358children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 359count=4 360eventq_index=0 361opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 362 363[system.cpu.fuPool.FUList5.opList00] 364type=OpDesc 365eventq_index=0 366opClass=SimdAdd 367opLat=1 368pipelined=true 369 370[system.cpu.fuPool.FUList5.opList01] 371type=OpDesc 372eventq_index=0 373opClass=SimdAddAcc 374opLat=1 375pipelined=true 376 377[system.cpu.fuPool.FUList5.opList02] 378type=OpDesc 379eventq_index=0 380opClass=SimdAlu 381opLat=1 382pipelined=true 383 384[system.cpu.fuPool.FUList5.opList03] 385type=OpDesc 386eventq_index=0 387opClass=SimdCmp 388opLat=1 389pipelined=true 390 391[system.cpu.fuPool.FUList5.opList04] 392type=OpDesc 393eventq_index=0 394opClass=SimdCvt 395opLat=1 396pipelined=true 397 398[system.cpu.fuPool.FUList5.opList05] 399type=OpDesc 400eventq_index=0 401opClass=SimdMisc 402opLat=1 403pipelined=true 404 405[system.cpu.fuPool.FUList5.opList06] 406type=OpDesc 407eventq_index=0 408opClass=SimdMult 409opLat=1 410pipelined=true 411 412[system.cpu.fuPool.FUList5.opList07] 413type=OpDesc 414eventq_index=0 415opClass=SimdMultAcc 416opLat=1 417pipelined=true 418 419[system.cpu.fuPool.FUList5.opList08] 420type=OpDesc 421eventq_index=0 422opClass=SimdShift 423opLat=1 424pipelined=true 425 426[system.cpu.fuPool.FUList5.opList09] 427type=OpDesc 428eventq_index=0 429opClass=SimdShiftAcc 430opLat=1 431pipelined=true 432 433[system.cpu.fuPool.FUList5.opList10] 434type=OpDesc 435eventq_index=0 436opClass=SimdSqrt 437opLat=1 438pipelined=true 439 440[system.cpu.fuPool.FUList5.opList11] 441type=OpDesc 442eventq_index=0 443opClass=SimdFloatAdd 444opLat=1 445pipelined=true 446 447[system.cpu.fuPool.FUList5.opList12] 448type=OpDesc 449eventq_index=0 450opClass=SimdFloatAlu 451opLat=1 452pipelined=true 453 454[system.cpu.fuPool.FUList5.opList13] 455type=OpDesc 456eventq_index=0 457opClass=SimdFloatCmp 458opLat=1 459pipelined=true 460 461[system.cpu.fuPool.FUList5.opList14] 462type=OpDesc 463eventq_index=0 464opClass=SimdFloatCvt 465opLat=1 466pipelined=true 467 468[system.cpu.fuPool.FUList5.opList15] 469type=OpDesc 470eventq_index=0 471opClass=SimdFloatDiv 472opLat=1 473pipelined=true 474 475[system.cpu.fuPool.FUList5.opList16] 476type=OpDesc 477eventq_index=0 478opClass=SimdFloatMisc 479opLat=1 480pipelined=true 481 482[system.cpu.fuPool.FUList5.opList17] 483type=OpDesc 484eventq_index=0 485opClass=SimdFloatMult 486opLat=1 487pipelined=true 488 489[system.cpu.fuPool.FUList5.opList18] 490type=OpDesc 491eventq_index=0 492opClass=SimdFloatMultAcc 493opLat=1 494pipelined=true 495 496[system.cpu.fuPool.FUList5.opList19] 497type=OpDesc 498eventq_index=0 499opClass=SimdFloatSqrt 500opLat=1 501pipelined=true 502 503[system.cpu.fuPool.FUList6] 504type=FUDesc 505children=opList 506count=0 507eventq_index=0 508opList=system.cpu.fuPool.FUList6.opList 509 510[system.cpu.fuPool.FUList6.opList] 511type=OpDesc 512eventq_index=0 513opClass=MemWrite 514opLat=1 515pipelined=true 516 517[system.cpu.fuPool.FUList7] 518type=FUDesc 519children=opList0 opList1 520count=4 521eventq_index=0 522opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 523 524[system.cpu.fuPool.FUList7.opList0] 525type=OpDesc 526eventq_index=0 527opClass=MemRead 528opLat=1 529pipelined=true 530 531[system.cpu.fuPool.FUList7.opList1] 532type=OpDesc 533eventq_index=0 534opClass=MemWrite 535opLat=1 536pipelined=true 537 538[system.cpu.fuPool.FUList8] 539type=FUDesc 540children=opList 541count=1 542eventq_index=0 543opList=system.cpu.fuPool.FUList8.opList 544 545[system.cpu.fuPool.FUList8.opList] 546type=OpDesc 547eventq_index=0 548opClass=IprAccess 549opLat=3 550pipelined=false 551 552[system.cpu.icache] 553type=Cache 554children=tags 555addr_ranges=0:18446744073709551615:0:0:0:0 556assoc=1 557clk_domain=system.cpu_clk_domain 558clusivity=mostly_incl 559default_p_state=UNDEFINED 560demand_mshr_reserve=1 561eventq_index=0 562hit_latency=2 563is_read_only=true 564max_miss_count=0 565mshrs=4 566p_state_clk_gate_bins=20 567p_state_clk_gate_max=1000000000000 568p_state_clk_gate_min=1000 569power_model=Null 570prefetch_on_access=false 571prefetcher=Null 572response_latency=2 573sequential_access=false 574size=32768 575system=system 576tags=system.cpu.icache.tags 577tgts_per_mshr=20 578write_buffers=8 579writeback_clean=true 580cpu_side=system.cpu.icache_port 581mem_side=system.cpu.toL2Bus.slave[0] 582 583[system.cpu.icache.tags] 584type=LRU 585assoc=1 586block_size=64 587clk_domain=system.cpu_clk_domain 588default_p_state=UNDEFINED 589eventq_index=0 590hit_latency=2 591p_state_clk_gate_bins=20 592p_state_clk_gate_max=1000000000000 593p_state_clk_gate_min=1000 594power_model=Null 595sequential_access=false 596size=32768 597 598[system.cpu.interrupts] 599type=AlphaInterrupts 600eventq_index=0 601 602[system.cpu.isa] 603type=AlphaISA 604eventq_index=0 605system=system 606 607[system.cpu.itb] 608type=AlphaTLB 609eventq_index=0 610size=48 611 612[system.cpu.l2cache] 613type=Cache 614children=tags 615addr_ranges=0:18446744073709551615:0:0:0:0 616assoc=8 617clk_domain=system.cpu_clk_domain 618clusivity=mostly_incl 619default_p_state=UNDEFINED 620demand_mshr_reserve=1 621eventq_index=0 622hit_latency=20 623is_read_only=false 624max_miss_count=0 625mshrs=20 626p_state_clk_gate_bins=20 627p_state_clk_gate_max=1000000000000 628p_state_clk_gate_min=1000 629power_model=Null 630prefetch_on_access=false 631prefetcher=Null 632response_latency=20 633sequential_access=false 634size=4194304 635system=system 636tags=system.cpu.l2cache.tags 637tgts_per_mshr=12 638write_buffers=8 639writeback_clean=false 640cpu_side=system.cpu.toL2Bus.master[0] 641mem_side=system.membus.slave[1] 642 643[system.cpu.l2cache.tags] 644type=LRU 645assoc=8 646block_size=64 647clk_domain=system.cpu_clk_domain 648default_p_state=UNDEFINED 649eventq_index=0 650hit_latency=20 651p_state_clk_gate_bins=20 652p_state_clk_gate_max=1000000000000 653p_state_clk_gate_min=1000 654power_model=Null 655sequential_access=false 656size=4194304 657 658[system.cpu.toL2Bus] 659type=CoherentXBar 660children=snoop_filter 661clk_domain=system.cpu_clk_domain 662default_p_state=UNDEFINED 663eventq_index=0 664forward_latency=0 665frontend_latency=1 666p_state_clk_gate_bins=20 667p_state_clk_gate_max=1000000000000 668p_state_clk_gate_min=1000 669point_of_coherency=false 670power_model=Null 671response_latency=1 672snoop_filter=system.cpu.toL2Bus.snoop_filter 673snoop_response_latency=1 674system=system 675use_default_range=false 676width=32 677master=system.cpu.l2cache.cpu_side 678slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 679 680[system.cpu.toL2Bus.snoop_filter] 681type=SnoopFilter 682eventq_index=0 683lookup_latency=0 684max_capacity=8388608 685system=system 686 687[system.cpu.tracer] 688type=ExeTracer 689eventq_index=0 690 691[system.cpu_clk_domain] 692type=SrcClockDomain 693clock=500 694domain_id=-1 695eventq_index=0 696init_perf_level=0 697voltage_domain=system.voltage_domain 698 699[system.disk0] 700type=IdeDisk 701children=image 702delay=1000000 703driveID=master 704eventq_index=0 705image=system.disk0.image 706 707[system.disk0.image] 708type=CowDiskImage 709children=child 710child=system.disk0.image.child 711eventq_index=0 712image_file= 713read_only=false 714table_size=65536 715 716[system.disk0.image.child] 717type=RawDiskImage 718eventq_index=0 719image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img 720read_only=true 721 722[system.disk2] 723type=IdeDisk 724children=image 725delay=1000000 726driveID=master 727eventq_index=0 728image=system.disk2.image 729 730[system.disk2.image] 731type=CowDiskImage 732children=child 733child=system.disk2.image.child 734eventq_index=0 735image_file= 736read_only=false 737table_size=65536 738 739[system.disk2.image.child] 740type=RawDiskImage 741eventq_index=0 742image_file=/arm/projectscratch/randd/systems/dist/disks/linux-bigswap2.img 743read_only=true 744 745[system.dvfs_handler] 746type=DVFSHandler 747domains= 748enable=false 749eventq_index=0 750sys_clk_domain=system.clk_domain 751transition_latency=100000000 752 753[system.intrctrl] 754type=IntrControl 755eventq_index=0 756sys=system 757 758[system.iobus] 759type=NoncoherentXBar 760clk_domain=system.clk_domain 761default_p_state=UNDEFINED 762eventq_index=0 763forward_latency=1 764frontend_latency=2 765p_state_clk_gate_bins=20 766p_state_clk_gate_max=1000000000000 767p_state_clk_gate_min=1000 768power_model=Null 769response_latency=2 770use_default_range=false 771width=16 772master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side 773slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma 774 775[system.iocache] 776type=Cache 777children=tags 778addr_ranges=0:134217727:0:0:0:0 779assoc=8 780clk_domain=system.clk_domain 781clusivity=mostly_incl 782default_p_state=UNDEFINED 783demand_mshr_reserve=1 784eventq_index=0 785hit_latency=50 786is_read_only=false 787max_miss_count=0 788mshrs=20 789p_state_clk_gate_bins=20 790p_state_clk_gate_max=1000000000000 791p_state_clk_gate_min=1000 792power_model=Null 793prefetch_on_access=false 794prefetcher=Null 795response_latency=50 796sequential_access=false 797size=1024 798system=system 799tags=system.iocache.tags 800tgts_per_mshr=12 801write_buffers=8 802writeback_clean=false 803cpu_side=system.iobus.master[27] 804mem_side=system.membus.slave[2] 805 806[system.iocache.tags] 807type=LRU 808assoc=8 809block_size=64 810clk_domain=system.clk_domain 811default_p_state=UNDEFINED 812eventq_index=0 813hit_latency=50 814p_state_clk_gate_bins=20 815p_state_clk_gate_max=1000000000000 816p_state_clk_gate_min=1000 817power_model=Null 818sequential_access=false 819size=1024 820 821[system.membus] 822type=CoherentXBar 823children=badaddr_responder snoop_filter 824clk_domain=system.clk_domain 825default_p_state=UNDEFINED 826eventq_index=0 827forward_latency=4 828frontend_latency=3 829p_state_clk_gate_bins=20 830p_state_clk_gate_max=1000000000000 831p_state_clk_gate_min=1000 832point_of_coherency=true 833power_model=Null 834response_latency=2 835snoop_filter=system.membus.snoop_filter 836snoop_response_latency=4 837system=system 838use_default_range=false 839width=16 840default=system.membus.badaddr_responder.pio 841master=system.bridge.slave system.physmem.port 842slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side 843 844[system.membus.badaddr_responder] 845type=IsaFake 846clk_domain=system.clk_domain 847default_p_state=UNDEFINED 848eventq_index=0 849fake_mem=false 850p_state_clk_gate_bins=20 851p_state_clk_gate_max=1000000000000 852p_state_clk_gate_min=1000 853pio_addr=0 854pio_latency=100000 855pio_size=8 856power_model=Null 857ret_bad_addr=true 858ret_data16=65535 859ret_data32=4294967295 860ret_data64=18446744073709551615 861ret_data8=255 862system=system 863update_data=false 864warn_access= 865pio=system.membus.default 866 867[system.membus.snoop_filter] 868type=SnoopFilter 869eventq_index=0 870lookup_latency=1 871max_capacity=8388608 872system=system 873 874[system.physmem] 875type=DRAMCtrl 876IDD0=0.055000 877IDD02=0.000000 878IDD2N=0.032000 879IDD2N2=0.000000 880IDD2P0=0.000000 881IDD2P02=0.000000 882IDD2P1=0.032000 883IDD2P12=0.000000 884IDD3N=0.038000 885IDD3N2=0.000000 886IDD3P0=0.000000 887IDD3P02=0.000000 888IDD3P1=0.038000 889IDD3P12=0.000000 890IDD4R=0.157000 891IDD4R2=0.000000 892IDD4W=0.125000 893IDD4W2=0.000000 894IDD5=0.235000 895IDD52=0.000000 896IDD6=0.020000 897IDD62=0.000000 898VDD=1.500000 899VDD2=0.000000 900activation_limit=4 901addr_mapping=RoRaBaCoCh 902bank_groups_per_rank=0 903banks_per_rank=8 904burst_length=8 905channels=1 906clk_domain=system.clk_domain 907conf_table_reported=true 908default_p_state=UNDEFINED 909device_bus_width=8 910device_rowbuffer_size=1024 911device_size=536870912 912devices_per_rank=8 913dll=true 914eventq_index=0 915in_addr_map=true 916kvm_map=true 917max_accesses_per_row=16 918mem_sched_policy=frfcfs 919min_writes_per_switch=16 920null=false 921p_state_clk_gate_bins=20 922p_state_clk_gate_max=1000000000000 923p_state_clk_gate_min=1000 924page_policy=open_adaptive 925power_model=Null 926range=0:134217727:0:0:0:0 927ranks_per_channel=2 928read_buffer_size=32 929static_backend_latency=10000 930static_frontend_latency=10000 931tBURST=5000 932tCCD_L=0 933tCK=1250 934tCL=13750 935tCS=2500 936tRAS=35000 937tRCD=13750 938tREFI=7800000 939tRFC=260000 940tRP=13750 941tRRD=6000 942tRRD_L=0 943tRTP=7500 944tRTW=2500 945tWR=15000 946tWTR=7500 947tXAW=30000 948tXP=6000 949tXPDLL=0 950tXS=270000 951tXSDLL=0 952write_buffer_size=64 953write_high_thresh_perc=85 954write_low_thresh_perc=50 955port=system.membus.master[1] 956 957[system.simple_disk] 958type=SimpleDisk 959children=disk 960disk=system.simple_disk.disk 961eventq_index=0 962system=system 963 964[system.simple_disk.disk] 965type=RawDiskImage 966eventq_index=0 967image_file=/arm/projectscratch/randd/systems/dist/disks/linux-latest.img 968read_only=true 969 970[system.terminal] 971type=Terminal 972eventq_index=0 973intr_control=system.intrctrl 974number=0 975output=true 976port=3456 977 978[system.tsunami] 979type=Tsunami 980children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip uart 981eventq_index=0 982intrctrl=system.intrctrl 983system=system 984 985[system.tsunami.backdoor] 986type=AlphaBackdoor 987clk_domain=system.clk_domain 988cpu=system.cpu 989default_p_state=UNDEFINED 990disk=system.simple_disk 991eventq_index=0 992p_state_clk_gate_bins=20 993p_state_clk_gate_max=1000000000000 994p_state_clk_gate_min=1000 995pio_addr=8804682956800 996pio_latency=100000 997platform=system.tsunami 998power_model=Null 999system=system 1000terminal=system.terminal 1001pio=system.iobus.master[24] 1002 1003[system.tsunami.cchip] 1004type=TsunamiCChip 1005clk_domain=system.clk_domain 1006default_p_state=UNDEFINED 1007eventq_index=0 1008p_state_clk_gate_bins=20 1009p_state_clk_gate_max=1000000000000 1010p_state_clk_gate_min=1000 1011pio_addr=8803072344064 1012pio_latency=100000 1013power_model=Null 1014system=system 1015tsunami=system.tsunami 1016pio=system.iobus.master[0] 1017 1018[system.tsunami.ethernet] 1019type=NSGigE 1020BAR0=1 1021BAR0LegacyIO=false 1022BAR0Size=256 1023BAR1=0 1024BAR1LegacyIO=false 1025BAR1Size=4096 1026BAR2=0 1027BAR2LegacyIO=false 1028BAR2Size=0 1029BAR3=0 1030BAR3LegacyIO=false 1031BAR3Size=0 1032BAR4=0 1033BAR4LegacyIO=false 1034BAR4Size=0 1035BAR5=0 1036BAR5LegacyIO=false 1037BAR5Size=0 1038BIST=0 1039CacheLineSize=0 1040CapabilityPtr=0 1041CardbusCIS=0 1042ClassCode=2 1043Command=0 1044DeviceID=34 1045ExpansionROM=0 1046HeaderType=0 1047InterruptLine=30 1048InterruptPin=1 1049LatencyTimer=0 1050LegacyIOBase=0 1051MSICAPBaseOffset=0 1052MSICAPCapId=0 1053MSICAPMaskBits=0 1054MSICAPMsgAddr=0 1055MSICAPMsgCtrl=0 1056MSICAPMsgData=0 1057MSICAPMsgUpperAddr=0 1058MSICAPNextCapability=0 1059MSICAPPendingBits=0 1060MSIXCAPBaseOffset=0 1061MSIXCAPCapId=0 1062MSIXCAPNextCapability=0 1063MSIXMsgCtrl=0 1064MSIXPbaOffset=0 1065MSIXTableOffset=0 1066MaximumLatency=52 1067MinimumGrant=176 1068PMCAPBaseOffset=0 1069PMCAPCapId=0 1070PMCAPCapabilities=0 1071PMCAPCtrlStatus=0 1072PMCAPNextCapability=0 1073PXCAPBaseOffset=0 1074PXCAPCapId=0 1075PXCAPCapabilities=0 1076PXCAPDevCap2=0 1077PXCAPDevCapabilities=0 1078PXCAPDevCtrl=0 1079PXCAPDevCtrl2=0 1080PXCAPDevStatus=0 1081PXCAPLinkCap=0 1082PXCAPLinkCtrl=0 1083PXCAPLinkStatus=0 1084PXCAPNextCapability=0 1085ProgIF=0 1086Revision=0 1087Status=656 1088SubClassCode=0 1089SubsystemID=0 1090SubsystemVendorID=0 1091VendorID=4107 1092clk_domain=system.clk_domain 1093config_latency=20000 1094default_p_state=UNDEFINED 1095dma_data_free=false 1096dma_desc_free=false 1097dma_no_allocate=true 1098dma_read_delay=0 1099dma_read_factor=0 1100dma_write_delay=0 1101dma_write_factor=0 1102eventq_index=0 1103hardware_address=00:90:00:00:00:01 1104host=system.tsunami.pchip 1105intr_delay=10000000 1106p_state_clk_gate_bins=20 1107p_state_clk_gate_max=1000000000000 1108p_state_clk_gate_min=1000 1109pci_bus=0 1110pci_dev=1 1111pci_func=0 1112pio_latency=30000 1113power_model=Null 1114rss=false 1115rx_delay=1000000 1116rx_fifo_size=524288 1117rx_filter=true 1118rx_thread=false 1119system=system 1120tx_delay=1000000 1121tx_fifo_size=524288 1122tx_thread=false 1123dma=system.iobus.slave[2] 1124pio=system.iobus.master[26] 1125 1126[system.tsunami.fake_OROM] 1127type=IsaFake 1128clk_domain=system.clk_domain 1129default_p_state=UNDEFINED 1130eventq_index=0 1131fake_mem=false 1132p_state_clk_gate_bins=20 1133p_state_clk_gate_max=1000000000000 1134p_state_clk_gate_min=1000 1135pio_addr=8796093677568 1136pio_latency=100000 1137pio_size=393216 1138power_model=Null 1139ret_bad_addr=false 1140ret_data16=65535 1141ret_data32=4294967295 1142ret_data64=18446744073709551615 1143ret_data8=255 1144system=system 1145update_data=false 1146warn_access= 1147pio=system.iobus.master[8] 1148 1149[system.tsunami.fake_ata0] 1150type=IsaFake 1151clk_domain=system.clk_domain 1152default_p_state=UNDEFINED 1153eventq_index=0 1154fake_mem=false 1155p_state_clk_gate_bins=20 1156p_state_clk_gate_max=1000000000000 1157p_state_clk_gate_min=1000 1158pio_addr=8804615848432 1159pio_latency=100000 1160pio_size=8 1161power_model=Null 1162ret_bad_addr=false 1163ret_data16=65535 1164ret_data32=4294967295 1165ret_data64=18446744073709551615 1166ret_data8=255 1167system=system 1168update_data=false 1169warn_access= 1170pio=system.iobus.master[19] 1171 1172[system.tsunami.fake_ata1] 1173type=IsaFake 1174clk_domain=system.clk_domain 1175default_p_state=UNDEFINED 1176eventq_index=0 1177fake_mem=false 1178p_state_clk_gate_bins=20 1179p_state_clk_gate_max=1000000000000 1180p_state_clk_gate_min=1000 1181pio_addr=8804615848304 1182pio_latency=100000 1183pio_size=8 1184power_model=Null 1185ret_bad_addr=false 1186ret_data16=65535 1187ret_data32=4294967295 1188ret_data64=18446744073709551615 1189ret_data8=255 1190system=system 1191update_data=false 1192warn_access= 1193pio=system.iobus.master[20] 1194 1195[system.tsunami.fake_pnp_addr] 1196type=IsaFake 1197clk_domain=system.clk_domain 1198default_p_state=UNDEFINED 1199eventq_index=0 1200fake_mem=false 1201p_state_clk_gate_bins=20 1202p_state_clk_gate_max=1000000000000 1203p_state_clk_gate_min=1000 1204pio_addr=8804615848569 1205pio_latency=100000 1206pio_size=8 1207power_model=Null 1208ret_bad_addr=false 1209ret_data16=65535 1210ret_data32=4294967295 1211ret_data64=18446744073709551615 1212ret_data8=255 1213system=system 1214update_data=false 1215warn_access= 1216pio=system.iobus.master[9] 1217 1218[system.tsunami.fake_pnp_read0] 1219type=IsaFake 1220clk_domain=system.clk_domain 1221default_p_state=UNDEFINED 1222eventq_index=0 1223fake_mem=false 1224p_state_clk_gate_bins=20 1225p_state_clk_gate_max=1000000000000 1226p_state_clk_gate_min=1000 1227pio_addr=8804615848451 1228pio_latency=100000 1229pio_size=8 1230power_model=Null 1231ret_bad_addr=false 1232ret_data16=65535 1233ret_data32=4294967295 1234ret_data64=18446744073709551615 1235ret_data8=255 1236system=system 1237update_data=false 1238warn_access= 1239pio=system.iobus.master[11] 1240 1241[system.tsunami.fake_pnp_read1] 1242type=IsaFake 1243clk_domain=system.clk_domain 1244default_p_state=UNDEFINED 1245eventq_index=0 1246fake_mem=false 1247p_state_clk_gate_bins=20 1248p_state_clk_gate_max=1000000000000 1249p_state_clk_gate_min=1000 1250pio_addr=8804615848515 1251pio_latency=100000 1252pio_size=8 1253power_model=Null 1254ret_bad_addr=false 1255ret_data16=65535 1256ret_data32=4294967295 1257ret_data64=18446744073709551615 1258ret_data8=255 1259system=system 1260update_data=false 1261warn_access= 1262pio=system.iobus.master[12] 1263 1264[system.tsunami.fake_pnp_read2] 1265type=IsaFake 1266clk_domain=system.clk_domain 1267default_p_state=UNDEFINED 1268eventq_index=0 1269fake_mem=false 1270p_state_clk_gate_bins=20 1271p_state_clk_gate_max=1000000000000 1272p_state_clk_gate_min=1000 1273pio_addr=8804615848579 1274pio_latency=100000 1275pio_size=8 1276power_model=Null 1277ret_bad_addr=false 1278ret_data16=65535 1279ret_data32=4294967295 1280ret_data64=18446744073709551615 1281ret_data8=255 1282system=system 1283update_data=false 1284warn_access= 1285pio=system.iobus.master[13] 1286 1287[system.tsunami.fake_pnp_read3] 1288type=IsaFake 1289clk_domain=system.clk_domain 1290default_p_state=UNDEFINED 1291eventq_index=0 1292fake_mem=false 1293p_state_clk_gate_bins=20 1294p_state_clk_gate_max=1000000000000 1295p_state_clk_gate_min=1000 1296pio_addr=8804615848643 1297pio_latency=100000 1298pio_size=8 1299power_model=Null 1300ret_bad_addr=false 1301ret_data16=65535 1302ret_data32=4294967295 1303ret_data64=18446744073709551615 1304ret_data8=255 1305system=system 1306update_data=false 1307warn_access= 1308pio=system.iobus.master[14] 1309 1310[system.tsunami.fake_pnp_read4] 1311type=IsaFake 1312clk_domain=system.clk_domain 1313default_p_state=UNDEFINED 1314eventq_index=0 1315fake_mem=false 1316p_state_clk_gate_bins=20 1317p_state_clk_gate_max=1000000000000 1318p_state_clk_gate_min=1000 1319pio_addr=8804615848707 1320pio_latency=100000 1321pio_size=8 1322power_model=Null 1323ret_bad_addr=false 1324ret_data16=65535 1325ret_data32=4294967295 1326ret_data64=18446744073709551615 1327ret_data8=255 1328system=system 1329update_data=false 1330warn_access= 1331pio=system.iobus.master[15] 1332 1333[system.tsunami.fake_pnp_read5] 1334type=IsaFake 1335clk_domain=system.clk_domain 1336default_p_state=UNDEFINED 1337eventq_index=0 1338fake_mem=false 1339p_state_clk_gate_bins=20 1340p_state_clk_gate_max=1000000000000 1341p_state_clk_gate_min=1000 1342pio_addr=8804615848771 1343pio_latency=100000 1344pio_size=8 1345power_model=Null 1346ret_bad_addr=false 1347ret_data16=65535 1348ret_data32=4294967295 1349ret_data64=18446744073709551615 1350ret_data8=255 1351system=system 1352update_data=false 1353warn_access= 1354pio=system.iobus.master[16] 1355 1356[system.tsunami.fake_pnp_read6] 1357type=IsaFake 1358clk_domain=system.clk_domain 1359default_p_state=UNDEFINED 1360eventq_index=0 1361fake_mem=false 1362p_state_clk_gate_bins=20 1363p_state_clk_gate_max=1000000000000 1364p_state_clk_gate_min=1000 1365pio_addr=8804615848835 1366pio_latency=100000 1367pio_size=8 1368power_model=Null 1369ret_bad_addr=false 1370ret_data16=65535 1371ret_data32=4294967295 1372ret_data64=18446744073709551615 1373ret_data8=255 1374system=system 1375update_data=false 1376warn_access= 1377pio=system.iobus.master[17] 1378 1379[system.tsunami.fake_pnp_read7] 1380type=IsaFake 1381clk_domain=system.clk_domain 1382default_p_state=UNDEFINED 1383eventq_index=0 1384fake_mem=false 1385p_state_clk_gate_bins=20 1386p_state_clk_gate_max=1000000000000 1387p_state_clk_gate_min=1000 1388pio_addr=8804615848899 1389pio_latency=100000 1390pio_size=8 1391power_model=Null 1392ret_bad_addr=false 1393ret_data16=65535 1394ret_data32=4294967295 1395ret_data64=18446744073709551615 1396ret_data8=255 1397system=system 1398update_data=false 1399warn_access= 1400pio=system.iobus.master[18] 1401 1402[system.tsunami.fake_pnp_write] 1403type=IsaFake 1404clk_domain=system.clk_domain 1405default_p_state=UNDEFINED 1406eventq_index=0 1407fake_mem=false 1408p_state_clk_gate_bins=20 1409p_state_clk_gate_max=1000000000000 1410p_state_clk_gate_min=1000 1411pio_addr=8804615850617 1412pio_latency=100000 1413pio_size=8 1414power_model=Null 1415ret_bad_addr=false 1416ret_data16=65535 1417ret_data32=4294967295 1418ret_data64=18446744073709551615 1419ret_data8=255 1420system=system 1421update_data=false 1422warn_access= 1423pio=system.iobus.master[10] 1424 1425[system.tsunami.fake_ppc] 1426type=IsaFake 1427clk_domain=system.clk_domain 1428default_p_state=UNDEFINED 1429eventq_index=0 1430fake_mem=false 1431p_state_clk_gate_bins=20 1432p_state_clk_gate_max=1000000000000 1433p_state_clk_gate_min=1000 1434pio_addr=8804615848891 1435pio_latency=100000 1436pio_size=8 1437power_model=Null 1438ret_bad_addr=false 1439ret_data16=65535 1440ret_data32=4294967295 1441ret_data64=18446744073709551615 1442ret_data8=255 1443system=system 1444update_data=false 1445warn_access= 1446pio=system.iobus.master[7] 1447 1448[system.tsunami.fake_sm_chip] 1449type=IsaFake 1450clk_domain=system.clk_domain 1451default_p_state=UNDEFINED 1452eventq_index=0 1453fake_mem=false 1454p_state_clk_gate_bins=20 1455p_state_clk_gate_max=1000000000000 1456p_state_clk_gate_min=1000 1457pio_addr=8804615848816 1458pio_latency=100000 1459pio_size=8 1460power_model=Null 1461ret_bad_addr=false 1462ret_data16=65535 1463ret_data32=4294967295 1464ret_data64=18446744073709551615 1465ret_data8=255 1466system=system 1467update_data=false 1468warn_access= 1469pio=system.iobus.master[2] 1470 1471[system.tsunami.fake_uart1] 1472type=IsaFake 1473clk_domain=system.clk_domain 1474default_p_state=UNDEFINED 1475eventq_index=0 1476fake_mem=false 1477p_state_clk_gate_bins=20 1478p_state_clk_gate_max=1000000000000 1479p_state_clk_gate_min=1000 1480pio_addr=8804615848696 1481pio_latency=100000 1482pio_size=8 1483power_model=Null 1484ret_bad_addr=false 1485ret_data16=65535 1486ret_data32=4294967295 1487ret_data64=18446744073709551615 1488ret_data8=255 1489system=system 1490update_data=false 1491warn_access= 1492pio=system.iobus.master[3] 1493 1494[system.tsunami.fake_uart2] 1495type=IsaFake 1496clk_domain=system.clk_domain 1497default_p_state=UNDEFINED 1498eventq_index=0 1499fake_mem=false 1500p_state_clk_gate_bins=20 1501p_state_clk_gate_max=1000000000000 1502p_state_clk_gate_min=1000 1503pio_addr=8804615848936 1504pio_latency=100000 1505pio_size=8 1506power_model=Null 1507ret_bad_addr=false 1508ret_data16=65535 1509ret_data32=4294967295 1510ret_data64=18446744073709551615 1511ret_data8=255 1512system=system 1513update_data=false 1514warn_access= 1515pio=system.iobus.master[4] 1516 1517[system.tsunami.fake_uart3] 1518type=IsaFake 1519clk_domain=system.clk_domain 1520default_p_state=UNDEFINED 1521eventq_index=0 1522fake_mem=false 1523p_state_clk_gate_bins=20 1524p_state_clk_gate_max=1000000000000 1525p_state_clk_gate_min=1000 1526pio_addr=8804615848680 1527pio_latency=100000 1528pio_size=8 1529power_model=Null 1530ret_bad_addr=false 1531ret_data16=65535 1532ret_data32=4294967295 1533ret_data64=18446744073709551615 1534ret_data8=255 1535system=system 1536update_data=false 1537warn_access= 1538pio=system.iobus.master[5] 1539 1540[system.tsunami.fake_uart4] 1541type=IsaFake 1542clk_domain=system.clk_domain 1543default_p_state=UNDEFINED 1544eventq_index=0 1545fake_mem=false 1546p_state_clk_gate_bins=20 1547p_state_clk_gate_max=1000000000000 1548p_state_clk_gate_min=1000 1549pio_addr=8804615848944 1550pio_latency=100000 1551pio_size=8 1552power_model=Null 1553ret_bad_addr=false 1554ret_data16=65535 1555ret_data32=4294967295 1556ret_data64=18446744073709551615 1557ret_data8=255 1558system=system 1559update_data=false 1560warn_access= 1561pio=system.iobus.master[6] 1562 1563[system.tsunami.fb] 1564type=BadDevice 1565clk_domain=system.clk_domain 1566default_p_state=UNDEFINED 1567devicename=FrameBuffer 1568eventq_index=0 1569p_state_clk_gate_bins=20 1570p_state_clk_gate_max=1000000000000 1571p_state_clk_gate_min=1000 1572pio_addr=8804615848912 1573pio_latency=100000 1574power_model=Null 1575system=system 1576pio=system.iobus.master[21] 1577 1578[system.tsunami.ide] 1579type=IdeController 1580BAR0=1 1581BAR0LegacyIO=false 1582BAR0Size=8 1583BAR1=1 1584BAR1LegacyIO=false 1585BAR1Size=4 1586BAR2=1 1587BAR2LegacyIO=false 1588BAR2Size=8 1589BAR3=1 1590BAR3LegacyIO=false 1591BAR3Size=4 1592BAR4=1 1593BAR4LegacyIO=false 1594BAR4Size=16 1595BAR5=1 1596BAR5LegacyIO=false 1597BAR5Size=0 1598BIST=0 1599CacheLineSize=0 1600CapabilityPtr=0 1601CardbusCIS=0 1602ClassCode=1 1603Command=0 1604DeviceID=28945 1605ExpansionROM=0 1606HeaderType=0 1607InterruptLine=31 1608InterruptPin=1 1609LatencyTimer=0 1610LegacyIOBase=0 1611MSICAPBaseOffset=0 1612MSICAPCapId=0 1613MSICAPMaskBits=0 1614MSICAPMsgAddr=0 1615MSICAPMsgCtrl=0 1616MSICAPMsgData=0 1617MSICAPMsgUpperAddr=0 1618MSICAPNextCapability=0 1619MSICAPPendingBits=0 1620MSIXCAPBaseOffset=0 1621MSIXCAPCapId=0 1622MSIXCAPNextCapability=0 1623MSIXMsgCtrl=0 1624MSIXPbaOffset=0 1625MSIXTableOffset=0 1626MaximumLatency=0 1627MinimumGrant=0 1628PMCAPBaseOffset=0 1629PMCAPCapId=0 1630PMCAPCapabilities=0 1631PMCAPCtrlStatus=0 1632PMCAPNextCapability=0 1633PXCAPBaseOffset=0 1634PXCAPCapId=0 1635PXCAPCapabilities=0 1636PXCAPDevCap2=0 1637PXCAPDevCapabilities=0 1638PXCAPDevCtrl=0 1639PXCAPDevCtrl2=0 1640PXCAPDevStatus=0 1641PXCAPLinkCap=0 1642PXCAPLinkCtrl=0 1643PXCAPLinkStatus=0 1644PXCAPNextCapability=0 1645ProgIF=133 1646Revision=0 1647Status=640 1648SubClassCode=1 1649SubsystemID=0 1650SubsystemVendorID=0 1651VendorID=32902 1652clk_domain=system.clk_domain 1653config_latency=20000 1654ctrl_offset=0 1655default_p_state=UNDEFINED 1656disks=system.disk0 system.disk2 1657eventq_index=0 1658host=system.tsunami.pchip 1659io_shift=0 1660p_state_clk_gate_bins=20 1661p_state_clk_gate_max=1000000000000 1662p_state_clk_gate_min=1000 1663pci_bus=0 1664pci_dev=0 1665pci_func=0 1666pio_latency=30000 1667power_model=Null 1668system=system 1669dma=system.iobus.slave[1] 1670pio=system.iobus.master[25] 1671 1672[system.tsunami.io] 1673type=TsunamiIO 1674clk_domain=system.clk_domain 1675default_p_state=UNDEFINED 1676eventq_index=0 1677frequency=976562500 1678p_state_clk_gate_bins=20 1679p_state_clk_gate_max=1000000000000 1680p_state_clk_gate_min=1000 1681pio_addr=8804615847936 1682pio_latency=100000 1683power_model=Null 1684system=system 1685time=Thu Jan 1 00:00:00 2009 1686tsunami=system.tsunami 1687year_is_bcd=false 1688pio=system.iobus.master[22] 1689 1690[system.tsunami.pchip] 1691type=TsunamiPChip 1692clk_domain=system.clk_domain 1693conf_base=8804649402368 1694conf_device_bits=8 1695conf_size=16777216 1696default_p_state=UNDEFINED 1697eventq_index=0 1698p_state_clk_gate_bins=20 1699p_state_clk_gate_max=1000000000000 1700p_state_clk_gate_min=1000 1701pci_dma_base=0 1702pci_mem_base=8796093022208 1703pci_pio_base=8804615847936 1704pio_addr=8802535473152 1705pio_latency=100000 1706platform=system.tsunami 1707power_model=Null 1708system=system 1709tsunami=system.tsunami 1710pio=system.iobus.master[1] 1711 1712[system.tsunami.uart] 1713type=Uart8250 1714clk_domain=system.clk_domain 1715default_p_state=UNDEFINED 1716eventq_index=0 1717p_state_clk_gate_bins=20 1718p_state_clk_gate_max=1000000000000 1719p_state_clk_gate_min=1000 1720pio_addr=8804615848952 1721pio_latency=100000 1722platform=system.tsunami 1723power_model=Null 1724system=system 1725terminal=system.terminal 1726pio=system.iobus.master[23] 1727 1728[system.voltage_domain] 1729type=VoltageDomain 1730eventq_index=0 1731voltage=1.000000 1732 1733