Searched hist:31 (Results 351 - 375 of 1011) sorted by relevance
/gem5/src/mem/cache/prefetch/ | ||
H A D | tagged.hh | diff 10623:b9646f4546ad Tue Dec 23 09:31:00 EST 2014 Mitch Hayenga <mitch.hayenga@arm.com> mem: Rework the structuring of the prefetchers Re-organizes the prefetcher class structure. Previously the BasePrefetcher forced multiple assumptions on the prefetchers that inherited from it. This patch makes the BasePrefetcher class truly representative of base functionality. For example, the base class no longer enforces FIFO order. Instead, prefetchers with FIFO requests (like the existing stride and tagged prefetchers) now inherit from a new QueuedPrefetcher base class. Finally, the stride-based prefetcher now assumes a custimizable lookup table (sets/ways) rather than the previous fully associative structure. |
/gem5/src/mem/slicc/ast/ | ||
H A D | PeekStatementAST.py | diff 10231:cb2e6950956d Sat May 31 21:00:00 EDT 2014 Steve Reinhardt <steve.reinhardt@amd.com> style: eliminate equality tests with true and false Using '== true' in a boolean expression is totally redundant, and using '== false' is pretty verbose (and arguably less readable in most cases) compared to '!'. It's somewhat of a pet peeve, perhaps, but I had some time waiting for some tests to run and decided to clean these up. Unfortunately, SLICC appears not to have the '!' operator, so I had to leave the '== false' tests in the SLICC code. |
/gem5/util/ | ||
H A D | git-pre-commit.py | diff 11716:95a34c2188f2 Fri Nov 25 05:31:00 EST 2016 Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com> util: git pre-commit hook to check staged files This patch updates the git-pre-commit hook to check the files as they will be after the commit, instead of as they are currently, this way we prevent the undesired situation: - unstylish modification of a file - stage said file for commit - try to commit and fail due to style - fix style, forgetting staging changes - try to commit and fail, as although the changes staged are not styly, the current content of the file is. Change-Id: I5cc3f783375d9e4162e310e176103ebbf0a59023 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [andreas.sandberg@arm.com: Rebased ontop of latest gem5] |
H A D | qdo | diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info |
/gem5/src/base/ | ||
H A D | circular_queue.hh | diff 14036:64006596f613 Fri May 31 12:39:00 EDT 2019 Daniel R. Carvalho <odanrc@yahoo.com.br> base: Fix missing headers to CircularQueue CircularQueue is currently throwing compilation errors when creating a derived class. assert() needs <cassert> ptrdiff_t needs <cstddef> (u)intX_t need <cstdint> random_access_iterator_tag needs <iterator> is_same, enable_if and others need <type_traits> Change-Id: I77a78e7b13f7a8b8e7e8b2b872065d78d1ab815a Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19089 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
/gem5/src/base/loader/ | ||
H A D | hex_file.cc | diff 10231:cb2e6950956d Sat May 31 21:00:00 EDT 2014 Steve Reinhardt <steve.reinhardt@amd.com> style: eliminate equality tests with true and false Using '== true' in a boolean expression is totally redundant, and using '== false' is pretty verbose (and arguably less readable in most cases) compared to '!'. It's somewhat of a pet peeve, perhaps, but I had some time waiting for some tests to run and decided to clean these up. Unfortunately, SLICC appears not to have the '!' operator, so I had to leave the '== false' tests in the SLICC code. |
/gem5/src/mem/ | ||
H A D | addr_mapper.hh | diff 9814:7ad2b0186a32 Thu Jul 18 08:31:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> mem: Set the cache line size on a system level This patch removes the notion of a peer block size and instead sets the cache line size on the system level. Previously the size was set per cache, and communicated through the interconnect. There were plenty checks to ensure that everyone had the same size specified, and these checks are now removed. Another benefit that is not yet harnessed is that the cache line size is now known at construction time, rather than after the port binding. Hence, the block size can be locally stored and does not have to be queried every time it is used. A follow-on patch updates the configuration scripts accordingly. |
/gem5/src/mem/cache/tags/ | ||
H A D | compressed_tags.hh | diff 13946:8e96e9be7f2c Tue Jun 19 11:31:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Add co-allocation function to compressed tags Implement a co-allocation function in compressed tags, so that compressed blocks can be co-allocated in a superblock. Co-allocation is possible when compression ratio (CR) blocks that share a superblock tag can be compressed to up to (100/CR)% of their size. Change-Id: I937cc1fcbb488e70309cb5478c12db65f1b4b23f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11411 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
H A D | compressed_tags.cc | diff 13946:8e96e9be7f2c Tue Jun 19 11:31:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Add co-allocation function to compressed tags Implement a co-allocation function in compressed tags, so that compressed blocks can be co-allocated in a superblock. Co-allocation is possible when compression ratio (CR) blocks that share a superblock tag can be compressed to up to (100/CR)% of their size. Change-Id: I937cc1fcbb488e70309cb5478c12db65f1b4b23f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11411 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
H A D | sector_blk.hh | 13224:1e74ea6ffe51 Thu Oct 11 08:31:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Move sector_blks to tags folder Move sector_blks.hh and sector_blks.cc to the tags folder, as its usage scope is restricted to the tags, and caches should not be aware of them. Change-Id: Ia7a71f51ec251d827872daf108c87da543a0ba57 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13417 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
/gem5/src/dev/arm/ | ||
H A D | smmu_v3_cmdexec.cc | diff 14065:f925f90bda01 Mon Jun 24 11:31:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Remove un-needed Q_CONS_PROD_MASK macro Change-Id: I858d7eea088bbdd2dc12123e21e59991c896597f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19310 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
H A D | smmu_v3_defs.hh | diff 14065:f925f90bda01 Mon Jun 24 11:31:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Remove un-needed Q_CONS_PROD_MASK macro Change-Id: I858d7eea088bbdd2dc12123e21e59991c896597f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19310 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
H A D | smmu_v3_slaveifc.hh | diff 14252:1659a606447f Fri Sep 06 19:31:00 EDT 2019 Gabe Black <gabeblack@google.com> dev: Scrub out some lingering uses of MemObject. MemObject doesn't do anything any more, and is basically just an alias for ClockedObject. Change-Id: Ic0e1658609e4e1d7f4b829fbc421f222e4869dee Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20719 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> |
/gem5/src/mem/ruby/slicc_interface/ | ||
H A D | AbstractEntry.hh | diff 8645:89929730804b Sat Dec 31 19:44:00 EST 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Shuffle some of the included files This patch adds and removes included files from some of the files so as to organize remove some false dependencies and include some files directly instead of transitively. |
/gem5/ext/pybind11/include/pybind11/ | ||
H A D | pybind11.h | diff 12894:6fdceb5c835f Tue Jul 31 12:22:00 EDT 2018 Jason Lowe-Power <jason@lowepower.com> ext: Cherry-pick pybind change to support GCC 8 GCC 8's -Wcast-function-type didn't like this line in pybind. Rather than updating pybind to the HEAD, we'll wait for a new release. The last release was in April and didn't include this change. See https://github.com/pybind/pybind11/pull/1396. Change-Id: I199c3023487d5a73a745396df8e7fcd6635a146c Reported-by: Thawra Kadeed <kadeed@ida.ing.tu-bs.de> Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/11909 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> |
/gem5/src/arch/alpha/isa/ | ||
H A D | decoder.isa | diff 7720:65d338a8dba4 Sun Oct 31 03:07:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC. diff 4828:768d4cf6b0dc Tue Jul 31 20:34:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add a flag to indicate an instruction triggers a syscall in SE mode. diff 3467:497be1067705 Tue Oct 31 18:59:00 EST 2006 Gabe Black <gblack@eecs.umich.edu> Arg! diff 3466:a7358b293100 Tue Oct 31 18:51:00 EST 2006 Gabe Black <gblack@eecs.umich.edu> More typos! I need to get nfs to work. diff 3465:18abcc7191ff Tue Oct 31 18:39:00 EST 2006 Gabe Black <gblack@eecs.umich.edu> Fix another typo diff 3464:2692df606f73 Tue Oct 31 18:19:00 EST 2006 Gabe Black <gblack@eecs.umich.edu> Check for out of range IPR values as well. diff 3462:ad2989480f70 Tue Oct 31 17:50:00 EST 2006 Gabe Black <gblack@eecs.umich.edu> Make two simple utility functions to determine if a MiscReg index corresponding to an IPR is readable or writable. diff 3458:acd55e0207f8 Tue Oct 31 16:18:00 EST 2006 Gabe Black <gblack@eecs.umich.edu> Forgot to change the index. diff 3457:7479ebe49444 Tue Oct 31 16:02:00 EST 2006 Gabe Black <gblack@eecs.umich.edu> Make the IPRs use regular miscreg indexes, and make a table or two to find the miscreg index of a specific IPR. diff 3454:26850ac19a39 Tue Oct 31 03:37:00 EST 2006 Gabe Black <gblack@eecs.umich.edu> Move IntrFlag into the MiscRegFile and get rid of specialized accessor functions. |
/gem5/src/cpu/o3/ | ||
H A D | mem_dep_unit.cc | diff 8737:770ccf3af571 Tue Jan 31 00:05:00 EST 2012 Koan-Sin Tan <koansin.tan@gmail.com> clang: Enable compiling gem5 using clang 2.9 and 3.0 This patch adds the necessary flags to the SConstruct and SConscript files for compiling using clang 2.9 and later (on Ubuntu et al and OSX XCode 4.2), and also cleans up a bunch of compiler warnings found by clang. Most of the warnings are related to hidden virtual functions, comparisons with unsigneds >= 0, and if-statements with empty bodies. A number of mismatches between struct and class are also fixed. clang 2.8 is not working as it has problems with class names that occur in multiple namespaces (e.g. Statistics in kernel_stats.hh). clang has a bug (http://llvm.org/bugs/show_bug.cgi?id=7247) which causes confusion between the container std::set and the function Packet::set, and this is currently addressed by not including the entire namespace std, but rather selecting e.g. "using std::vector" in the appropriate places. diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info |
/gem5/ | ||
H A D | README | diff 5193:5485f026271e Wed Oct 31 01:21:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> RELEASE: First cut of updated release files for 2.0b4 diff 1869:792d73aad8d6 Mon Sep 05 16:31:00 EDT 2005 Steve Reinhardt <stever@eecs.umich.edu> Regression tests now run under scons! For example, 'scons ALPHA_SE/test/opt/quick' will build ALPHA_SE/m5.opt if necessary and run all the self-identified "quick" tests on it. Other possibilities: - Run just test1: scons ALPHA_SE/test/opt/test1 - Run all tests: scons ALPHA_SE/test/opt - Run all tests on debug build: scons ALPHA_SE/test/debug - Update test1 reference outputs in m5-test: scons update_ref=y ALPHA_SE/test/opt/test1 The proper tests will be selected based on the setting of FULL_SYSTEM, ALPHA_TLASER, etc. README: Update directions to use scons-based test invocation. SConscript: Return list of generated build environments to SConstruct so it can associate tests with each of them. Set 'M5Binary' attribute on each env to record name of generated binary to be tested. build/SConstruct: - Support invoking m5-test tests via scons. - Add new non-sticky option category, for 'update_ref'. - Move existing "sticky" option definitions out of build_dir loop. Someday we can generate help text from these. - Make 'CC' and 'CXX' sticky options; use environment vars as defaults if available. - Make config builder more scons-y. python/m5/__init__.py: Make AddToPath() correctly handle relative path arguments. Assumes that sys.path[0] has the directory where the current Python file lives; new m5execfile() function sets this up properly for exec'd files. |
/gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/ | ||
H A D | stats.txt | diff 11502:e273e86a873d Tue May 31 06:07:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update for snoop filter tweak diff 9490:e6a09d97bdc9 Thu Jan 31 07:49:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default. |
/gem5/tests/configs/ | ||
H A D | o3-timing-checker.py | diff 9489:172dbcb74a0e Thu Jan 31 07:49:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> mem: Add DDR3 and LPDDR2 DRAM controller configurations This patch moves the default DRAM parameters from the SimpleDRAM class to two different subclasses, one for DDR3 and one for LPDDR2. More can be added as we go forward. The regressions that previously used the SimpleDRAM are now using SimpleDDR3 as this is the most similar configuration. diff 9036:6385cf85bf12 Thu May 31 13:30:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> Bus: Split the bus into a non-coherent and coherent bus This patch introduces a class hierarchy of buses, a non-coherent one, and a coherent one, splitting the existing bus functionality. By doing so it also enables further specialisation of the two types of buses. A non-coherent bus connects a number of non-snooping masters and slaves, and routes the request and response packets based on the address. The request packets issued by the master connected to a non-coherent bus could still snoop in caches attached to a coherent bus, as is the case with the I/O bus and memory bus in most system configurations. No snoops will, however, reach any master on the non-coherent bus itself. The non-coherent bus can be used as a template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses, and is typically used for the I/O buses. A coherent bus connects a number of (potentially) snooping masters and slaves, and routes the request and response packets based on the address, and also forwards all requests to the snoopers and deals with the snoop responses. The coherent bus can be used as a template for modelling QPI, HyperTransport, ACE and coherent OCP buses, and is typically used for the L1-to-L2 buses and as the main system interconnect. The configuration scripts are updated to use a NoncoherentBus for all peripheral and I/O buses. A bit of minor tidying up has also been done. |
/gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/ | ||
H A D | stats.txt | diff 11507:be6065c1d8d2 Tue May 31 11:55:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update and fix e273e86a873d diff 11502:e273e86a873d Tue May 31 06:07:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update for snoop filter tweak |
/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ | ||
H A D | stats.txt | diff 11502:e273e86a873d Tue May 31 06:07:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update for snoop filter tweak diff 10628:c9b7e0c69f88 Tue Dec 23 09:31:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller. |
/gem5/tests/quick/se/00.hello/ref/arm/linux/minor-timing/ | ||
H A D | stats.txt | diff 11502:e273e86a873d Tue May 31 06:07:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update for snoop filter tweak diff 10628:c9b7e0c69f88 Tue Dec 23 09:31:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller. |
/gem5/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/ | ||
H A D | stats.txt | diff 11502:e273e86a873d Tue May 31 06:07:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update for snoop filter tweak diff 10628:c9b7e0c69f88 Tue Dec 23 09:31:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller. |
/gem5/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/ | ||
H A D | stats.txt | diff 11502:e273e86a873d Tue May 31 06:07:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update for snoop filter tweak diff 10628:c9b7e0c69f88 Tue Dec 23 09:31:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller. |
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