Searched hist:31 (Results 276 - 300 of 1011) sorted by relevance
/gem5/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/ | ||
H A D | stats.txt | diff 11502:e273e86a873d Tue May 31 06:07:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update for snoop filter tweak diff 10628:c9b7e0c69f88 Tue Dec 23 09:31:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller. diff 9490:e6a09d97bdc9 Thu Jan 31 07:49:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default. |
/gem5/tests/long/se/10.mcf/ref/x86/linux/simple-timing/ | ||
H A D | stats.txt | diff 11507:be6065c1d8d2 Tue May 31 11:55:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update and fix e273e86a873d diff 11502:e273e86a873d Tue May 31 06:07:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update for snoop filter tweak diff 9924:31ef410b6843 Wed Oct 16 10:44:00 EDT 2013 Steve Reinhardt <steve.reinhardt@amd.com> test: update stats Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses. |
/gem5/tests/long/se/20.parser/ref/arm/linux/simple-timing/ | ||
H A D | stats.txt | diff 11507:be6065c1d8d2 Tue May 31 11:55:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update and fix e273e86a873d diff 11502:e273e86a873d Tue May 31 06:07:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update for snoop filter tweak diff 10628:c9b7e0c69f88 Tue Dec 23 09:31:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller. |
/gem5/tests/long/se/20.parser/ref/x86/linux/simple-timing/ | ||
H A D | stats.txt | diff 11507:be6065c1d8d2 Tue May 31 11:55:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update and fix e273e86a873d diff 11502:e273e86a873d Tue May 31 06:07:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update for snoop filter tweak diff 9924:31ef410b6843 Wed Oct 16 10:44:00 EDT 2013 Steve Reinhardt <steve.reinhardt@amd.com> test: update stats Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses. |
/gem5/tests/long/se/30.eon/ref/arm/linux/simple-timing/ | ||
H A D | stats.txt | diff 11507:be6065c1d8d2 Tue May 31 11:55:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update and fix e273e86a873d diff 11502:e273e86a873d Tue May 31 06:07:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update for snoop filter tweak diff 10628:c9b7e0c69f88 Tue Dec 23 09:31:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller. |
/gem5/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/ | ||
H A D | stats.txt | diff 11507:be6065c1d8d2 Tue May 31 11:55:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update and fix e273e86a873d diff 11502:e273e86a873d Tue May 31 06:07:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update for snoop filter tweak diff 10628:c9b7e0c69f88 Tue Dec 23 09:31:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller. |
/gem5/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/ | ||
H A D | stats.txt | diff 11507:be6065c1d8d2 Tue May 31 11:55:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update and fix e273e86a873d diff 11502:e273e86a873d Tue May 31 06:07:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update for snoop filter tweak diff 10628:c9b7e0c69f88 Tue Dec 23 09:31:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller. |
/gem5/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/ | ||
H A D | stats.txt | diff 11507:be6065c1d8d2 Tue May 31 11:55:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update and fix e273e86a873d diff 11502:e273e86a873d Tue May 31 06:07:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update for snoop filter tweak diff 9924:31ef410b6843 Wed Oct 16 10:44:00 EDT 2013 Steve Reinhardt <steve.reinhardt@amd.com> test: update stats Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses. |
/gem5/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ | ||
H A D | stats.txt | diff 11502:e273e86a873d Tue May 31 06:07:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update for snoop filter tweak diff 10628:c9b7e0c69f88 Tue Dec 23 09:31:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller. diff 9924:31ef410b6843 Wed Oct 16 10:44:00 EDT 2013 Steve Reinhardt <steve.reinhardt@amd.com> test: update stats Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses. |
/gem5/src/base/ | ||
H A D | pollevent.cc | diff 12164:6a4fd7d604b1 Mon Jul 31 18:31:00 EDT 2017 Gabe Black <gabeblack@google.com> base: Give more information when setting up asynchronous IO fails. When asynchronous IO fails, gem5 currently just says it failed and quits, and doesn't give any more information about which step failed, or what specifically about it failed. This change adds two helpers which will attempt the fcntl, check for error conditions, and in the event of a failure, include a message describing the error code and what the arguments to fcntl were. Change-Id: I316478172ab2aefd3788279dbc12744791385cd5 Reviewed-on: https://gem5-review.googlesource.com/4320 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> diff 12164:6a4fd7d604b1 Mon Jul 31 18:31:00 EDT 2017 Gabe Black <gabeblack@google.com> base: Give more information when setting up asynchronous IO fails. When asynchronous IO fails, gem5 currently just says it failed and quits, and doesn't give any more information about which step failed, or what specifically about it failed. This change adds two helpers which will attempt the fcntl, check for error conditions, and in the event of a failure, include a message describing the error code and what the arguments to fcntl were. Change-Id: I316478172ab2aefd3788279dbc12744791385cd5 Reviewed-on: https://gem5-review.googlesource.com/4320 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com> diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info |
H A D | random.cc | diff 8658:f1a69b7246f7 Mon Jan 09 19:08:00 EST 2012 Dam Sunwoo <dam.sunwoo@arm.com> Base: Fixed shift amount in genrand() to work with large numbers The previous version didn't work correctly with max integer values (2^31-1 for 32-bit, 2^63-1 for 64bit version), causing "shift" to become -1. For smaller numbers, it wouldn't have caused functional errors, but would have resulted in more than necessary loops in the while loop. Special-cased cases when (max + 1 == 0) to prevent the ceilLog2 functions from failing. diff 5190:fc46e0d647b6 Wed Oct 31 01:21:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Base: Rework the way M5 provides and creates random numbers. diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info |
H A D | pollevent.hh | diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info |
/gem5/src/dev/ | ||
H A D | isa_fake.cc | diff 5192:582e583f8e7e Wed Oct 31 01:21:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Traceflags: Add SCons function to created a traceflag instead of having one file with them all. diff 3357:0963b8a38b5e Sat Oct 21 03:31:00 EDT 2006 Nathan Binkert <binkertn@umich.edu> Missing case diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info |
/gem5/src/arch/mips/isa/formats/ | ||
H A D | mt.isa | diff 8607:5fb918115c07 Mon Oct 31 04:09:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> GCC: Get everything working with gcc 4.6.1. And by "everything" I mean all the quick regressions. diff 6383:31c067ae3331 Wed Jul 22 02:38:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Format the register index constants like the other ISAs. Also a few more style fixes. diff 5202:ff56fa8c2091 Wed Oct 31 21:04:00 EDT 2007 Steve Reinhardt <stever@gmail.com> String constant const-ness changes to placate g++ 4.2. Also some bug fixes in MIPS ISA uncovered by g++ warnings (Python string compares don't work in C++!). |
/gem5/src/mem/ | ||
H A D | comm_monitor.hh | diff 13573:3223a8c1c3dd Wed Nov 14 11:31:00 EST 2018 Sascha Bischoff <sascha.bischoff@arm.com> mem: Add tryTiming suppport to CommMonitor The CommMonitor did not support tryTiming, which resulted in gem5 panicing if the CommMonitor was used. With this change, we update the CommMonitor pass through the tryTiming() calls. Change-Id: I86810170e5e10a0c5d63af76fc4a6ab70710d2fb Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15736 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> diff 10615:cd8aae15f89a Tue Dec 23 09:31:00 EST 2014 Kanishk Sugand <kanishk.sugand@arm.com> mem: Add stack distance statistics to the CommMonitor This patch adds the stack distance calculator to the CommMonitor. The stats are disabled by default. diff 9814:7ad2b0186a32 Thu Jul 18 08:31:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> mem: Set the cache line size on a system level This patch removes the notion of a peer block size and instead sets the cache line size on the system level. Previously the size was set per cache, and communicated through the interconnect. There were plenty checks to ensure that everyone had the same size specified, and these checks are now removed. Another benefit that is not yet harnessed is that the cache line size is now known at construction time, rather than after the port binding. Hence, the block size can be locally stored and does not have to be queried every time it is used. A follow-on patch updates the configuration scripts accordingly. |
/gem5/src/cpu/o3/ | ||
H A D | rob.cc | diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info |
/gem5/src/mem/slicc/ast/ | ||
H A D | IsValidPtrExprAST.py | diff 8192:be38f7b6ad9e Thu Mar 31 20:18:00 EDT 2011 Lisa Hsu <Lisa.Hsu@amd.com> Ruby: Simplify SLICC and Entry/TBE handling. Before this changeset, all local variables of type Entry and TBE were considered to be pointers, but an immediate use of said variables would not be automatically deferenced in SLICC-generated code. Instead, deferences occurred when such variables were passed to functions, and were automatically dereferenced in the bodies of the functions (e.g. the implicitly passed cache_entry). This is a more general way to do it, which leaves in place the assumption that parameters to functions and local variables of type AbstractCacheEntry and TBE are always pointers, but instead of dereferencing to access member variables on a contextual basis, the dereferencing automatically occurs on a type basis at the moment a member is being accessed. So, now, things you can do that you couldn't before include: Entry foo := getCacheEntry(address); cache_entry.DataBlk := foo.DataBlk; or cache_entry.DataBlk := getCacheEntry(address).DataBlk; or even cache_entry.DataBlk := static_cast(Entry, pointer, cache.lookup(address)).DataBlk; |
H A D | ActionDeclAST.py | diff 8192:be38f7b6ad9e Thu Mar 31 20:18:00 EDT 2011 Lisa Hsu <Lisa.Hsu@amd.com> Ruby: Simplify SLICC and Entry/TBE handling. Before this changeset, all local variables of type Entry and TBE were considered to be pointers, but an immediate use of said variables would not be automatically deferenced in SLICC-generated code. Instead, deferences occurred when such variables were passed to functions, and were automatically dereferenced in the bodies of the functions (e.g. the implicitly passed cache_entry). This is a more general way to do it, which leaves in place the assumption that parameters to functions and local variables of type AbstractCacheEntry and TBE are always pointers, but instead of dereferencing to access member variables on a contextual basis, the dereferencing automatically occurs on a type basis at the moment a member is being accessed. So, now, things you can do that you couldn't before include: Entry foo := getCacheEntry(address); cache_entry.DataBlk := foo.DataBlk; or cache_entry.DataBlk := getCacheEntry(address).DataBlk; or even cache_entry.DataBlk := static_cast(Entry, pointer, cache.lookup(address)).DataBlk; |
/gem5/tests/configs/ | ||
H A D | simple-atomic-dummychecker.py | diff 9036:6385cf85bf12 Thu May 31 13:30:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> Bus: Split the bus into a non-coherent and coherent bus This patch introduces a class hierarchy of buses, a non-coherent one, and a coherent one, splitting the existing bus functionality. By doing so it also enables further specialisation of the two types of buses. A non-coherent bus connects a number of non-snooping masters and slaves, and routes the request and response packets based on the address. The request packets issued by the master connected to a non-coherent bus could still snoop in caches attached to a coherent bus, as is the case with the I/O bus and memory bus in most system configurations. No snoops will, however, reach any master on the non-coherent bus itself. The non-coherent bus can be used as a template for modelling PCI, PCIe, and non-coherent AMBA and OCP buses, and is typically used for the I/O buses. A coherent bus connects a number of (potentially) snooping masters and slaves, and routes the request and response packets based on the address, and also forwards all requests to the snoopers and deals with the snoop responses. The coherent bus can be used as a template for modelling QPI, HyperTransport, ACE and coherent OCP buses, and is typically used for the L1-to-L2 buses and as the main system interconnect. The configuration scripts are updated to use a NoncoherentBus for all peripheral and I/O buses. A bit of minor tidying up has also been done. |
/gem5/src/arch/x86/isa/ | ||
H A D | main.isa | diff 4336:bd6ab22f8e11 Wed Apr 04 10:31:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Reworking how x86's isa description works. I'm adopting the following definitions to make figuring out what's what a little easier: MicroOp: A single operation actually implemented in hardware. MacroOp: A collection of microops which are executed as a unit. Instruction: An architected instruction which can be implemented with a macroop or a microop. |
/gem5/util/stats/ | ||
H A D | display.py | diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info |
/gem5/src/sim/ | ||
H A D | debug.hh | diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info |
/gem5/src/base/loader/ | ||
H A D | ecoff_object.hh | diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info |
H A D | aout_object.hh | diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info |
/gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/ | ||
H A D | stats.txt | diff 11507:be6065c1d8d2 Tue May 31 11:55:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update and fix e273e86a873d diff 11502:e273e86a873d Tue May 31 06:07:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update for snoop filter tweak diff 10628:c9b7e0c69f88 Tue Dec 23 09:31:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for decoder, TLB, prefetcher and DRAM changes Changes due to speculative execution of an unaligned PC, introduction of TLB stats, changes and re-work of the prefetcher, and the introduction of rank-wise refresh in the DRAM controller. diff 9490:e6a09d97bdc9 Thu Jan 31 07:49:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for regressions using SimpleDDR3 This patch updates the regression stats to reflect that they are using the SimpleDDR3 controller by default. |
Completed in 82 milliseconds