12968SN/A 22968SN/A---------- Begin Simulation Statistics ---------- 311680SCurtis.Dunham@arm.comsim_seconds 1.966742 # Number of seconds simulated 411754Sandreas.hansson@arm.comsim_ticks 1966742176000 # Number of ticks simulated 511754Sandreas.hansson@arm.comfinal_tick 1966742176000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68721SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711754Sandreas.hansson@arm.comhost_inst_rate 1742915 # Simulator instruction rate (inst/s) 811754Sandreas.hansson@arm.comhost_op_rate 1742915 # Simulator op (including micro ops) rate (op/s) 911754Sandreas.hansson@arm.comhost_tick_rate 56229643103 # Simulator tick rate (ticks/s) 1011754Sandreas.hansson@arm.comhost_mem_usage 335876 # Number of bytes of host memory used 1111754Sandreas.hansson@arm.comhost_seconds 34.98 # Real time elapsed on the host 1211754Sandreas.hansson@arm.comsim_insts 60961842 # Number of instructions simulated 1311754Sandreas.hansson@arm.comsim_ops 60961842 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611754Sandreas.hansson@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 1711754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 796800 # Number of bytes read from this memory 1811754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 24828736 # Number of bytes read from this memory 1911754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 62272 # Number of bytes read from this memory 2011754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 430784 # Number of bytes read from this memory 2110352Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 2211754Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 26119552 # Number of bytes read from this memory 2311754Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 796800 # Number of instructions bytes read from this memory 2411754Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 62272 # Number of instructions bytes read from this memory 2511754Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 859072 # Number of instructions bytes read from this memory 2611754Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 7774400 # Number of bytes written to this memory 2711754Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7774400 # Number of bytes written to this memory 2811754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 12450 # Number of read requests responded to by this memory 2911754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 387949 # Number of read requests responded to by this memory 3011754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 973 # Number of read requests responded to by this memory 3111754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 6731 # Number of read requests responded to by this memory 3210352Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory 3311754Sandreas.hansson@arm.comsystem.physmem.num_reads::total 408118 # Number of read requests responded to by this memory 3411754Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 121475 # Number of write requests responded to by this memory 3511754Sandreas.hansson@arm.comsystem.physmem.num_writes::total 121475 # Number of write requests responded to by this memory 3611754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 405137 # Total read bandwidth from this memory (bytes/s) 3711754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 12624296 # Total read bandwidth from this memory (bytes/s) 3811754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 31663 # Total read bandwidth from this memory (bytes/s) 3911754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 219034 # Total read bandwidth from this memory (bytes/s) 4011680SCurtis.Dunham@arm.comsystem.physmem.bw_read::tsunami.ide 488 # Total read bandwidth from this memory (bytes/s) 4111754Sandreas.hansson@arm.comsystem.physmem.bw_read::total 13280618 # Total read bandwidth from this memory (bytes/s) 4211754Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 405137 # Instruction read bandwidth from this memory (bytes/s) 4311754Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 31663 # Instruction read bandwidth from this memory (bytes/s) 4411754Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 436800 # Instruction read bandwidth from this memory (bytes/s) 4511754Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 3952933 # Write bandwidth from this memory (bytes/s) 4611754Sandreas.hansson@arm.comsystem.physmem.bw_write::total 3952933 # Write bandwidth from this memory (bytes/s) 4711754Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 3952933 # Total bandwidth to/from this memory (bytes/s) 4811754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 405137 # Total bandwidth to/from this memory (bytes/s) 4911754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 12624296 # Total bandwidth to/from this memory (bytes/s) 5011754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 31663 # Total bandwidth to/from this memory (bytes/s) 5111754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 219034 # Total bandwidth to/from this memory (bytes/s) 5211680SCurtis.Dunham@arm.comsystem.physmem.bw_total::tsunami.ide 488 # Total bandwidth to/from this memory (bytes/s) 5311754Sandreas.hansson@arm.comsystem.physmem.bw_total::total 17233551 # Total bandwidth to/from this memory (bytes/s) 5411754Sandreas.hansson@arm.comsystem.physmem.readReqs 408118 # Number of read requests accepted 5511754Sandreas.hansson@arm.comsystem.physmem.writeReqs 121475 # Number of write requests accepted 5611754Sandreas.hansson@arm.comsystem.physmem.readBursts 408118 # Number of DRAM read bursts, including those serviced by the write queue 5711754Sandreas.hansson@arm.comsystem.physmem.writeBursts 121475 # Number of DRAM write bursts, including those merged in the write queue 5811754Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 26112384 # Total number of bytes read from DRAM 5911680SCurtis.Dunham@arm.comsystem.physmem.bytesReadWrQ 7168 # Total number of bytes read from write queue 6011754Sandreas.hansson@arm.comsystem.physmem.bytesWritten 7772672 # Total number of bytes written to DRAM 6111754Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 26119552 # Total read bytes from the system interface side 6211754Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 7774400 # Total written bytes from the system interface side 6311680SCurtis.Dunham@arm.comsystem.physmem.servicedByWrQ 112 # Number of DRAM read bursts serviced by the write queue 6410892Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 6511336Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 6611680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 25299 # Per bank write bursts 6711680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::1 25599 # Per bank write bursts 6811680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::2 25910 # Per bank write bursts 6911680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::3 25657 # Per bank write bursts 7011680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::4 25586 # Per bank write bursts 7111680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::5 25177 # Per bank write bursts 7211680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::6 26012 # Per bank write bursts 7311680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::7 25110 # Per bank write bursts 7411680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::8 25002 # Per bank write bursts 7511680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::9 25326 # Per bank write bursts 7611754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 25349 # Per bank write bursts 7711680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 25350 # Per bank write bursts 7811754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 25737 # Per bank write bursts 7911754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 25386 # Per bank write bursts 8011680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::14 25673 # Per bank write bursts 8111754Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 25833 # Per bank write bursts 8211680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::0 7888 # Per bank write bursts 8311680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::1 7973 # Per bank write bursts 8411680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::2 7891 # Per bank write bursts 8511680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::3 7697 # Per bank write bursts 8611680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::4 7528 # Per bank write bursts 8711680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::5 7375 # Per bank write bursts 8811680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::6 8079 # Per bank write bursts 8911680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::7 7030 # Per bank write bursts 9011680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::8 7056 # Per bank write bursts 9111680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::9 7058 # Per bank write bursts 9211754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 7244 # Per bank write bursts 9311680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::11 7671 # Per bank write bursts 9411680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::12 7657 # Per bank write bursts 9511754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 7545 # Per bank write bursts 9611680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::14 7813 # Per bank write bursts 9711754Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 7943 # Per bank write bursts 989978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 9911680SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 71 # Number of times write queue was full causing retry 10011754Sandreas.hansson@arm.comsystem.physmem.totGap 1966734882500 # Total gap between requests 1019978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 1029978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 1039978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 1049978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 1059978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 1069978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 10711754Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 408118 # Read request sizes (log2) 1089978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 1099978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 1109978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 1119978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 1129978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 1139978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 11411754Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 121475 # Write request sizes (log2) 11511754Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 407913 # What read queue length does an incoming req see 11611680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::1 80 # What read queue length does an incoming req see 11710352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see 11810352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 11910352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 12010352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 12110352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 12210352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 12310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 12410352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 12510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 12610352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 12710352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 12810352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 12910352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 13010352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 13110352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 13210352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 13310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 13410352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 13510352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 14710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 14810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 14910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 15010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 15110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 15210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 15310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 15410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 15510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 15610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 15710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 16211754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 1645 # What write queue length does an incoming req see 16311754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 2764 # What write queue length does an incoming req see 16411754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 5743 # What write queue length does an incoming req see 16511754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 5834 # What write queue length does an incoming req see 16611754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 6413 # What write queue length does an incoming req see 16711754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 6550 # What write queue length does an incoming req see 16811754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 7349 # What write queue length does an incoming req see 16911754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 8420 # What write queue length does an incoming req see 17011754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 6966 # What write queue length does an incoming req see 17111754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 7388 # What write queue length does an incoming req see 17211754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 8059 # What write queue length does an incoming req see 17311680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::26 7676 # What write queue length does an incoming req see 17411754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 6925 # What write queue length does an incoming req see 17511754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 7056 # What write queue length does an incoming req see 17611754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 6260 # What write queue length does an incoming req see 17711754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 6183 # What write queue length does an incoming req see 17811754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 5977 # What write queue length does an incoming req see 17911754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 5774 # What write queue length does an incoming req see 18011754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 413 # What write queue length does an incoming req see 18111754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 397 # What write queue length does an incoming req see 18211754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 270 # What write queue length does an incoming req see 18311754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 303 # What write queue length does an incoming req see 18411754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 235 # What write queue length does an incoming req see 18511754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 266 # What write queue length does an incoming req see 18611754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 267 # What write queue length does an incoming req see 18711754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 294 # What write queue length does an incoming req see 18811754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 275 # What write queue length does an incoming req see 18911754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 293 # What write queue length does an incoming req see 19011680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 315 # What write queue length does an incoming req see 19111754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 348 # What write queue length does an incoming req see 19211754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 316 # What write queue length does an incoming req see 19311754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 305 # What write queue length does an incoming req see 19411754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 300 # What write queue length does an incoming req see 19511754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 295 # What write queue length does an incoming req see 19611754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 291 # What write queue length does an incoming req see 19711754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 248 # What write queue length does an incoming req see 19811680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 188 # What write queue length does an incoming req see 19911754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 210 # What write queue length does an incoming req see 20011754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 218 # What write queue length does an incoming req see 20111754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 201 # What write queue length does an incoming req see 20211754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 236 # What write queue length does an incoming req see 20311754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 336 # What write queue length does an incoming req see 20411680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 265 # What write queue length does an incoming req see 20511754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 197 # What write queue length does an incoming req see 20611754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 360 # What write queue length does an incoming req see 20711754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 360 # What write queue length does an incoming req see 20811754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 197 # What write queue length does an incoming req see 20911754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 123 # What write queue length does an incoming req see 21011754Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 156 # What write queue length does an incoming req see 21111754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 65997 # Bytes accessed per row activation 21211754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 513.433277 # Bytes accessed per row activation 21311754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 309.806046 # Bytes accessed per row activation 21411754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 413.661980 # Bytes accessed per row activation 21511754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 15519 23.51% 23.51% # Bytes accessed per row activation 21611754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 12333 18.69% 42.20% # Bytes accessed per row activation 21711754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 4691 7.11% 49.31% # Bytes accessed per row activation 21811754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 3281 4.97% 54.28% # Bytes accessed per row activation 21911754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 3296 4.99% 59.28% # Bytes accessed per row activation 22011754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 1531 2.32% 61.60% # Bytes accessed per row activation 22111754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 1650 2.50% 64.10% # Bytes accessed per row activation 22211754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 1071 1.62% 65.72% # Bytes accessed per row activation 22311754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 22625 34.28% 100.00% # Bytes accessed per row activation 22411754Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 65997 # Bytes accessed per row activation 22511754Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 5403 # Reads before turning the bus around for writes 22611754Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 75.512863 # Reads before turning the bus around for writes 22711754Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 2871.806103 # Reads before turning the bus around for writes 22811754Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-8191 5400 99.94% 99.94% # Reads before turning the bus around for writes 22910726Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes 23010726Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes 23110726Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes 23211754Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 5403 # Reads before turning the bus around for writes 23311754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 5403 # Writes before turning the bus around for reads 23411754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 22.477883 # Writes before turning the bus around for reads 23511754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 18.790649 # Writes before turning the bus around for reads 23611754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 24.259878 # Writes before turning the bus around for reads 23711754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-23 4886 90.43% 90.43% # Writes before turning the bus around for reads 23811754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-31 27 0.50% 90.93% # Writes before turning the bus around for reads 23911754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-39 174 3.22% 94.15% # Writes before turning the bus around for reads 24011754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-47 7 0.13% 94.28% # Writes before turning the bus around for reads 24111754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-55 5 0.09% 94.37% # Writes before turning the bus around for reads 24211754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-63 18 0.33% 94.71% # Writes before turning the bus around for reads 24311754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-71 10 0.19% 94.89% # Writes before turning the bus around for reads 24411680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::72-79 2 0.04% 94.93% # Writes before turning the bus around for reads 24511754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-87 26 0.48% 95.41% # Writes before turning the bus around for reads 24611754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::88-95 6 0.11% 95.52% # Writes before turning the bus around for reads 24711754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::96-103 152 2.81% 98.33% # Writes before turning the bus around for reads 24811754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::104-111 23 0.43% 98.76% # Writes before turning the bus around for reads 24911754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-119 4 0.07% 98.83% # Writes before turning the bus around for reads 25011680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::120-127 3 0.06% 98.89% # Writes before turning the bus around for reads 25111680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::128-135 4 0.07% 98.96% # Writes before turning the bus around for reads 25211680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::136-143 5 0.09% 99.06% # Writes before turning the bus around for reads 25311680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::144-151 2 0.04% 99.09% # Writes before turning the bus around for reads 25411680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::152-159 1 0.02% 99.11% # Writes before turning the bus around for reads 25511680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::160-167 1 0.02% 99.13% # Writes before turning the bus around for reads 25611754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::168-175 5 0.09% 99.22% # Writes before turning the bus around for reads 25711754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::176-183 7 0.13% 99.35% # Writes before turning the bus around for reads 25811754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::184-191 10 0.19% 99.54% # Writes before turning the bus around for reads 25911680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::192-199 7 0.13% 99.67% # Writes before turning the bus around for reads 26011754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::200-207 3 0.06% 99.72% # Writes before turning the bus around for reads 26111754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::208-215 1 0.02% 99.74% # Writes before turning the bus around for reads 26211754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::216-223 6 0.11% 99.85% # Writes before turning the bus around for reads 26311754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::224-231 4 0.07% 99.93% # Writes before turning the bus around for reads 26411680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::256-263 2 0.04% 99.96% # Writes before turning the bus around for reads 26511680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::264-271 1 0.02% 99.98% # Writes before turning the bus around for reads 26611680SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::336-343 1 0.02% 100.00% # Writes before turning the bus around for reads 26711754Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 5403 # Writes before turning the bus around for reads 26811754Sandreas.hansson@arm.comsystem.physmem.totQLat 6253232750 # Total ticks spent queuing 26911754Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 13903345250 # Total ticks spent from burst creation until serviced by the DRAM 27011754Sandreas.hansson@arm.comsystem.physmem.totBusLat 2040030000 # Total ticks spent in databus transfers 27111754Sandreas.hansson@arm.comsystem.physmem.avgQLat 15326.33 # Average queueing delay per DRAM burst 2729978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 27311754Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 34076.33 # Average memory access latency per DRAM burst 27411680SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 13.28 # Average DRAM read bandwidth in MiByte/s 27511680SCurtis.Dunham@arm.comsystem.physmem.avgWrBW 3.95 # Average achieved write bandwidth in MiByte/s 27611680SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 13.28 # Average system read bandwidth in MiByte/s 27711680SCurtis.Dunham@arm.comsystem.physmem.avgWrBWSys 3.95 # Average system write bandwidth in MiByte/s 2789978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 27910892Sandreas.hansson@arm.comsystem.physmem.busUtil 0.13 # Data bus utilization in percentage 28010352Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads 28110726Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 28210352Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 28311754Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 22.81 # Average write queue length when enqueuing 28411754Sandreas.hansson@arm.comsystem.physmem.readRowHits 365871 # Number of row buffer hits during reads 28511680SCurtis.Dunham@arm.comsystem.physmem.writeRowHits 97586 # Number of row buffer hits during writes 28611754Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 89.67 # Row buffer hit rate for reads 28711754Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 80.33 # Row buffer hit rate for writes 28811754Sandreas.hansson@arm.comsystem.physmem.avgGap 3713672.35 # Average gap between requests 28911680SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 87.53 # Row buffer hit rate, read and write combined 29011754Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 236455380 # Energy for activate commands per rank (pJ) 29111754Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 125679015 # Energy for precharge commands per rank (pJ) 29211680SCurtis.Dunham@arm.comsystem.physmem_0.readEnergy 1459059000 # Energy for read commands per rank (pJ) 29311680SCurtis.Dunham@arm.comsystem.physmem_0.writeEnergy 320826420 # Energy for write commands per rank (pJ) 29411754Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 5647926960.000001 # Energy for refresh commands per rank (pJ) 29511754Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 5154923820 # Energy for active background per rank (pJ) 29611754Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 376838880 # Energy for precharge background per rank (pJ) 29711754Sandreas.hansson@arm.comsystem.physmem_0.actPowerDownEnergy 13418648160 # Energy for active power-down per rank (pJ) 29811754Sandreas.hansson@arm.comsystem.physmem_0.prePowerDownEnergy 6443555040 # Energy for precharge power-down per rank (pJ) 29911754Sandreas.hansson@arm.comsystem.physmem_0.selfRefreshEnergy 458974810065 # Energy for self refresh per rank (pJ) 30011754Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 492161345970 # Total energy per rank (pJ) 30111754Sandreas.hansson@arm.comsystem.physmem_0.averagePower 250.241923 # Core power per rank (mW) 30211754Sandreas.hansson@arm.comsystem.physmem_0.totalIdleTime 1954449369000 # Total Idle time Per DRAM Rank 30311754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 631981750 # Time in different power states 30411754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 2402382000 # Time in different power states 30511754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::SREF 1908243357500 # Time in different power states 30611754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 16780134250 # Time in different power states 30711754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 9257305750 # Time in different power states 30811754Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 29427014750 # Time in different power states 30911754Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 234763200 # Energy for activate commands per rank (pJ) 31011754Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 124779600 # Energy for precharge commands per rank (pJ) 31111754Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 1454103840 # Energy for read commands per rank (pJ) 31211754Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 313132140 # Energy for write commands per rank (pJ) 31311754Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 5778230640.000001 # Energy for refresh commands per rank (pJ) 31411754Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 5151828720 # Energy for active background per rank (pJ) 31511754Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 364649760 # Energy for precharge background per rank (pJ) 31611754Sandreas.hansson@arm.comsystem.physmem_1.actPowerDownEnergy 13829543490 # Energy for active power-down per rank (pJ) 31711754Sandreas.hansson@arm.comsystem.physmem_1.prePowerDownEnergy 6726228480 # Energy for precharge power-down per rank (pJ) 31811754Sandreas.hansson@arm.comsystem.physmem_1.selfRefreshEnergy 458595076560 # Energy for self refresh per rank (pJ) 31911754Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 492575015880 # Total energy per rank (pJ) 32011754Sandreas.hansson@arm.comsystem.physmem_1.averagePower 250.452256 # Core power per rank (mW) 32111754Sandreas.hansson@arm.comsystem.physmem_1.totalIdleTime 1954420956750 # Total Idle time Per DRAM Rank 32211754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 598934250 # Time in different power states 32311754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 2457676000 # Time in different power states 32411754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::SREF 1906644575500 # Time in different power states 32511754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 17516296750 # Time in different power states 32611754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 9196775500 # Time in different power states 32711754Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 30327918000 # Time in different power states 32811754Sandreas.hansson@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 32911754Sandreas.hansson@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 33010036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 3318721SN/Asystem.cpu0.dtb.fetch_hits 0 # ITB hits 3328721SN/Asystem.cpu0.dtb.fetch_misses 0 # ITB misses 3338721SN/Asystem.cpu0.dtb.fetch_acv 0 # ITB acv 3348721SN/Asystem.cpu0.dtb.fetch_accesses 0 # ITB accesses 33511754Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 7479524 # DTB read hits 33611680SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_misses 7764 # DTB read misses 3379289Sandreas.hansson@arm.comsystem.cpu0.dtb.read_acv 210 # DTB read access violations 33811680SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_accesses 524068 # DTB read accesses 33911754Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 5079926 # DTB write hits 34011680SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_misses 909 # DTB write misses 34111680SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_acv 133 # DTB write access violations 34211680SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_accesses 202594 # DTB write accesses 34311754Sandreas.hansson@arm.comsystem.cpu0.dtb.data_hits 12559450 # DTB hits 34411680SCurtis.Dunham@arm.comsystem.cpu0.dtb.data_misses 8673 # DTB misses 34511680SCurtis.Dunham@arm.comsystem.cpu0.dtb.data_acv 343 # DTB access violations 34611680SCurtis.Dunham@arm.comsystem.cpu0.dtb.data_accesses 726662 # DTB accesses 34711754Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_hits 3638587 # ITB hits 34811680SCurtis.Dunham@arm.comsystem.cpu0.itb.fetch_misses 3984 # ITB misses 3499289Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_acv 184 # ITB acv 35011754Sandreas.hansson@arm.comsystem.cpu0.itb.fetch_accesses 3642571 # ITB accesses 3518721SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 3528721SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 3538721SN/Asystem.cpu0.itb.read_acv 0 # DTB read access violations 3548721SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 3558721SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 3568721SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 3578721SN/Asystem.cpu0.itb.write_acv 0 # DTB write access violations 3588721SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 3596024SN/Asystem.cpu0.itb.data_hits 0 # DTB hits 3606024SN/Asystem.cpu0.itb.data_misses 0 # DTB misses 3618721SN/Asystem.cpu0.itb.data_acv 0 # DTB access violations 3628721SN/Asystem.cpu0.itb.data_accesses 0 # DTB accesses 36311754Sandreas.hansson@arm.comsystem.cpu0.numPwrStateTransitions 13586 # Number of power state transitions 36411754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::samples 6793 # Distribution of time spent in the clock gated state 36511754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::mean 272328046.518475 # Distribution of time spent in the clock gated state 36611754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::stdev 432907003.390448 # Distribution of time spent in the clock gated state 36711754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::1000-5e+10 6793 100.00% 100.00% # Distribution of time spent in the clock gated state 36811754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::min_value 169000 # Distribution of time spent in the clock gated state 36911530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state 37011754Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::total 6793 # Distribution of time spent in the clock gated state 37111754Sandreas.hansson@arm.comsystem.cpu0.pwrStateResidencyTicks::ON 116817756000 # Cumulative time (in ticks) in various power states 37211754Sandreas.hansson@arm.comsystem.cpu0.pwrStateResidencyTicks::CLK_GATED 1849924420000 # Cumulative time (in ticks) in various power states 37311754Sandreas.hansson@arm.comsystem.cpu0.numCycles 3933484352 # number of cpu cycles simulated 3748721SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 3758721SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 3762968SN/Asystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 37711754Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 6793 # number of quiesce instructions executed 37811754Sandreas.hansson@arm.comsystem.cpu0.kern.inst.hwrei 163848 # number of hwrei instructions executed 37911754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::0 56217 40.17% 40.17% # number of times we switched to this ipl 38011680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_count::21 131 0.09% 40.26% # number of times we switched to this ipl 38111680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_count::22 1975 1.41% 41.67% # number of times we switched to this ipl 38211680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_count::30 433 0.31% 41.98% # number of times we switched to this ipl 38311680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_count::31 81195 58.02% 100.00% # number of times we switched to this ipl 38411754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_count::total 139951 # number of times we switched to this ipl 38511754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::0 55705 49.07% 49.07% # number of times we switched to this ipl from a different ipl 38611680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl 38711680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_good::22 1975 1.74% 50.93% # number of times we switched to this ipl from a different ipl 38811680SCurtis.Dunham@arm.comsystem.cpu0.kern.ipl_good::30 433 0.38% 51.31% # number of times we switched to this ipl from a different ipl 38911754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::31 55272 48.69% 100.00% # number of times we switched to this ipl from a different ipl 39011754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_good::total 113516 # number of times we switched to this ipl from a different ipl 39111754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::0 1903162232500 96.77% 96.77% # number of cycles we spent at this ipl 39211754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::21 93267000 0.00% 96.77% # number of cycles we spent at this ipl 39311754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::22 789745000 0.04% 96.81% # number of cycles we spent at this ipl 39411754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::30 321096500 0.02% 96.83% # number of cycles we spent at this ipl 39511754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::31 62375109000 3.17% 100.00% # number of cycles we spent at this ipl 39611754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_ticks::total 1966741450000 # number of cycles we spent at this ipl 39711754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::0 0.990892 # fraction of swpipl calls that actually changed the ipl 3986127SN/Asystem.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 3996127SN/Asystem.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 4006127SN/Asystem.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 40111754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::31 0.680732 # fraction of swpipl calls that actually changed the ipl 40211754Sandreas.hansson@arm.comsystem.cpu0.kern.ipl_used::total 0.811112 # fraction of swpipl calls that actually changed the ipl 4038721SN/Asystem.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 40411680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::wripir 525 0.35% 0.36% # number of callpals executed 40511680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::wrmces 1 0.00% 0.36% # number of callpals executed 40611680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::wrfen 1 0.00% 0.36% # number of callpals executed 40711680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::wrvptptr 1 0.00% 0.36% # number of callpals executed 40811754Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpctx 3063 2.07% 2.43% # number of callpals executed 40911680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::tbi 51 0.03% 2.46% # number of callpals executed 41011680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::wrent 7 0.00% 2.46% # number of callpals executed 41111754Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::swpipl 132999 89.79% 92.25% # number of callpals executed 41211680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::rdps 6513 4.40% 96.65% # number of callpals executed 41311680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::wrkgp 1 0.00% 96.65% # number of callpals executed 41411680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::wrusp 4 0.00% 96.65% # number of callpals executed 41511680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::rdusp 9 0.01% 96.66% # number of callpals executed 41611680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::whami 2 0.00% 96.66% # number of callpals executed 41711680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::rti 4412 2.98% 99.64% # number of callpals executed 41811680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::callsys 394 0.27% 99.91% # number of callpals executed 41911680SCurtis.Dunham@arm.comsystem.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed 42011754Sandreas.hansson@arm.comsystem.cpu0.kern.callpal::total 148123 # number of callpals executed 42111754Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::kernel 6987 # number of protection mode switches 42211754Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch::user 1370 # number of protection mode switches 4238721SN/Asystem.cpu0.kern.mode_switch::idle 0 # number of protection mode switches 42411754Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::kernel 1369 42511754Sandreas.hansson@arm.comsystem.cpu0.kern.mode_good::user 1370 4268721SN/Asystem.cpu0.kern.mode_good::idle 0 42711754Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::kernel 0.195935 # fraction of useful protection mode switches 4288721SN/Asystem.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 4298983Snate@binkert.orgsystem.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches 43011754Sandreas.hansson@arm.comsystem.cpu0.kern.mode_switch_good::total 0.327749 # fraction of useful protection mode switches 43111754Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::kernel 1962822047500 99.80% 99.80% # number of ticks spent at the given mode 43211754Sandreas.hansson@arm.comsystem.cpu0.kern.mode_ticks::user 3919400500 0.20% 100.00% # number of ticks spent at the given mode 4338721SN/Asystem.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode 43411754Sandreas.hansson@arm.comsystem.cpu0.kern.swap_context 3064 # number of times the context was actually changed 43511754Sandreas.hansson@arm.comsystem.cpu0.committedInsts 47693300 # Number of instructions committed 43611754Sandreas.hansson@arm.comsystem.cpu0.committedOps 47693300 # Number of ops (including micro ops) committed 43711754Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 44245928 # Number of integer alu accesses 43811754Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 210005 # Number of float alu accesses 43911754Sandreas.hansson@arm.comsystem.cpu0.num_func_calls 1191022 # number of times a function call or return occured 44011754Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 5607802 # number of instructions that are conditional controls 44111754Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 44245928 # number of integer instructions 44211754Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 210005 # number of float instructions 44311754Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 60860766 # number of times the integer registers were read 44411754Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 32957591 # number of times the integer registers were written 44511754Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 102620 # number of times the floating registers were read 44611754Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 104398 # number of times the floating registers were written 44711754Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 12600240 # number of memory refs 44811754Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 7507148 # Number of load instructions 44911754Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 5093092 # Number of store instructions 45011754Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles 3699848839.998118 # Number of idle cycles 45111754Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles 233635512.001881 # Number of busy cycles 45211754Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.059397 # Percentage of non-idle cycles 45311754Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.940603 # Percentage of idle cycles 45411754Sandreas.hansson@arm.comsystem.cpu0.Branches 7183589 # Number of branches fetched 45511754Sandreas.hansson@arm.comsystem.cpu0.op_class::No_OpClass 2715591 5.69% 5.69% # Class of executed instruction 45611754Sandreas.hansson@arm.comsystem.cpu0.op_class::IntAlu 31389831 65.80% 71.50% # Class of executed instruction 45711754Sandreas.hansson@arm.comsystem.cpu0.op_class::IntMult 52060 0.11% 71.61% # Class of executed instruction 45811680SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntDiv 0 0.00% 71.61% # Class of executed instruction 45911754Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 26674 0.06% 71.66% # Class of executed instruction 46011680SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 71.66% # Class of executed instruction 46111680SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 71.66% # Class of executed instruction 46211680SCurtis.Dunham@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 71.66% # Class of executed instruction 46311687Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMultAcc 0 0.00% 71.66% # Class of executed instruction 46411754Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 1883 0.00% 71.67% # Class of executed instruction 46511754Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMisc 0 0.00% 71.67% # Class of executed instruction 46611754Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 71.67% # Class of executed instruction 46711754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 71.67% # Class of executed instruction 46811754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 71.67% # Class of executed instruction 46911754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 71.67% # Class of executed instruction 47011754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 71.67% # Class of executed instruction 47111754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 71.67% # Class of executed instruction 47211754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 71.67% # Class of executed instruction 47311754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 71.67% # Class of executed instruction 47411754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 71.67% # Class of executed instruction 47511754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 71.67% # Class of executed instruction 47611754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 71.67% # Class of executed instruction 47711754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 71.67% # Class of executed instruction 47811754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 71.67% # Class of executed instruction 47911754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 71.67% # Class of executed instruction 48011754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 71.67% # Class of executed instruction 48111754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 71.67% # Class of executed instruction 48211754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 71.67% # Class of executed instruction 48311754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMisc 0 0.00% 71.67% # Class of executed instruction 48411754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 71.67% # Class of executed instruction 48511754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.67% # Class of executed instruction 48611754Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.67% # Class of executed instruction 48711754Sandreas.hansson@arm.comsystem.cpu0.op_class::MemRead 7588720 15.91% 87.57% # Class of executed instruction 48811754Sandreas.hansson@arm.comsystem.cpu0.op_class::MemWrite 5010315 10.50% 98.08% # Class of executed instruction 48911754Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMemRead 92556 0.19% 98.27% # Class of executed instruction 49011754Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMemWrite 88892 0.19% 98.46% # Class of executed instruction 49111754Sandreas.hansson@arm.comsystem.cpu0.op_class::IprAccess 735794 1.54% 100.00% # Class of executed instruction 49211201Sandreas.hansson@arm.comsystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 49311754Sandreas.hansson@arm.comsystem.cpu0.op_class::total 47702316 # Class of executed instruction 49411754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 49511754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 1183155 # number of replacements 49611754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 505.237754 # Cycle average of tags in use 49711754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 11370167 # Total number of references to valid blocks. 49811754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 1183667 # Sample count of references to valid blocks. 49911754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 9.605883 # Average number of references to valid blocks. 50011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.warmup_cycle 121324500 # Cycle when the warmup percentage was hit. 50111754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 505.237754 # Average occupied blocks per requestor 50211754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.986792 # Average percentage of cache occupancy 50311754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.986792 # Average percentage of cache occupancy 50411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 50511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id 50611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id 50711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id 50811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 50911754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 51474763 # Number of tag accesses 51011754Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 51474763 # Number of data accesses 51111754Sandreas.hansson@arm.comsystem.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 51211754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 6401125 # number of ReadReq hits 51311754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 6401125 # number of ReadReq hits 51411754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 4669512 # number of WriteReq hits 51511754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 4669512 # number of WriteReq hits 51611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 138994 # number of LoadLockedReq hits 51711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 138994 # number of LoadLockedReq hits 51811754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 146310 # number of StoreCondReq hits 51911754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 146310 # number of StoreCondReq hits 52011754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 11070637 # number of demand (read+write) hits 52111754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 11070637 # number of demand (read+write) hits 52211754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 11070637 # number of overall hits 52311754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 11070637 # number of overall hits 52411754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 938392 # number of ReadReq misses 52511754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 938392 # number of ReadReq misses 52611754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 255335 # number of WriteReq misses 52711754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 255335 # number of WriteReq misses 52811754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13590 # number of LoadLockedReq misses 52911754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 13590 # number of LoadLockedReq misses 53011680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 5728 # number of StoreCondReq misses 53111680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 5728 # number of StoreCondReq misses 53211754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 1193727 # number of demand (read+write) misses 53311754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 1193727 # number of demand (read+write) misses 53411754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 1193727 # number of overall misses 53511754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 1193727 # number of overall misses 53611754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 31214419000 # number of ReadReq miss cycles 53711754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 31214419000 # number of ReadReq miss cycles 53811754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 12662507500 # number of WriteReq miss cycles 53911754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 12662507500 # number of WriteReq miss cycles 54011754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150368000 # number of LoadLockedReq miss cycles 54111754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 150368000 # number of LoadLockedReq miss cycles 54211754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 31952500 # number of StoreCondReq miss cycles 54311754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 31952500 # number of StoreCondReq miss cycles 54411754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 43876926500 # number of demand (read+write) miss cycles 54511754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::total 43876926500 # number of demand (read+write) miss cycles 54611754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 43876926500 # number of overall miss cycles 54711754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::total 43876926500 # number of overall miss cycles 54811754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 7339517 # number of ReadReq accesses(hits+misses) 54911754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 7339517 # number of ReadReq accesses(hits+misses) 55011754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 4924847 # number of WriteReq accesses(hits+misses) 55111754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 4924847 # number of WriteReq accesses(hits+misses) 55211754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 152584 # number of LoadLockedReq accesses(hits+misses) 55311754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 152584 # number of LoadLockedReq accesses(hits+misses) 55411754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 152038 # number of StoreCondReq accesses(hits+misses) 55511754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 152038 # number of StoreCondReq accesses(hits+misses) 55611754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 12264364 # number of demand (read+write) accesses 55711754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 12264364 # number of demand (read+write) accesses 55811754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 12264364 # number of overall (read+write) accesses 55911754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 12264364 # number of overall (read+write) accesses 56011754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127855 # miss rate for ReadReq accesses 56111754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.127855 # miss rate for ReadReq accesses 56211754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051846 # miss rate for WriteReq accesses 56311754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.051846 # miss rate for WriteReq accesses 56411754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.089066 # miss rate for LoadLockedReq accesses 56511754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.089066 # miss rate for LoadLockedReq accesses 56611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.037675 # miss rate for StoreCondReq accesses 56711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.037675 # miss rate for StoreCondReq accesses 56811754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.097333 # miss rate for demand accesses 56911754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.097333 # miss rate for demand accesses 57011754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.097333 # miss rate for overall accesses 57111754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.097333 # miss rate for overall accesses 57211754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 33263.730935 # average ReadReq miss latency 57311754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 33263.730935 # average ReadReq miss latency 57411754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 49591.742221 # average WriteReq miss latency 57511754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 49591.742221 # average WriteReq miss latency 57611754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11064.606328 # average LoadLockedReq miss latency 57711754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11064.606328 # average LoadLockedReq miss latency 57811754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5578.299581 # average StoreCondReq miss latency 57911754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5578.299581 # average StoreCondReq miss latency 58011754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36756.248707 # average overall miss latency 58111754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 36756.248707 # average overall miss latency 58211754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36756.248707 # average overall miss latency 58311754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 36756.248707 # average overall miss latency 58410585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 58510585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 58610585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 58710585Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 58810585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 58910585Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 59011754Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 681263 # number of writebacks 59111754Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 681263 # number of writebacks 59211754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938392 # number of ReadReq MSHR misses 59311754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 938392 # number of ReadReq MSHR misses 59411754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 255335 # number of WriteReq MSHR misses 59511754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 255335 # number of WriteReq MSHR misses 59611754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13590 # number of LoadLockedReq MSHR misses 59711754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 13590 # number of LoadLockedReq MSHR misses 59811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5728 # number of StoreCondReq MSHR misses 59911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 5728 # number of StoreCondReq MSHR misses 60011754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 1193727 # number of demand (read+write) MSHR misses 60111754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 1193727 # number of demand (read+write) MSHR misses 60211754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 1193727 # number of overall MSHR misses 60311754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 1193727 # number of overall MSHR misses 60411680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7073 # number of ReadReq MSHR uncacheable 60511680SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::total 7073 # number of ReadReq MSHR uncacheable 60611680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10752 # number of WriteReq MSHR uncacheable 60711680SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::total 10752 # number of WriteReq MSHR uncacheable 60811680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17825 # number of overall MSHR uncacheable misses 60911680SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::total 17825 # number of overall MSHR uncacheable misses 61011754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 30276027000 # number of ReadReq MSHR miss cycles 61111754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 30276027000 # number of ReadReq MSHR miss cycles 61211754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 12407172500 # number of WriteReq MSHR miss cycles 61311754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 12407172500 # number of WriteReq MSHR miss cycles 61411754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 136778000 # number of LoadLockedReq MSHR miss cycles 61511754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136778000 # number of LoadLockedReq MSHR miss cycles 61611754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 26224500 # number of StoreCondReq MSHR miss cycles 61711754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 26224500 # number of StoreCondReq MSHR miss cycles 61811754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 42683199500 # number of demand (read+write) MSHR miss cycles 61911754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 42683199500 # number of demand (read+write) MSHR miss cycles 62011754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 42683199500 # number of overall MSHR miss cycles 62111754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 42683199500 # number of overall MSHR miss cycles 62211754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1572134500 # number of ReadReq MSHR uncacheable cycles 62311754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1572134500 # number of ReadReq MSHR uncacheable cycles 62411754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1572134500 # number of overall MSHR uncacheable cycles 62511754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 1572134500 # number of overall MSHR uncacheable cycles 62611754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127855 # mshr miss rate for ReadReq accesses 62711754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127855 # mshr miss rate for ReadReq accesses 62811754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051846 # mshr miss rate for WriteReq accesses 62911754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051846 # mshr miss rate for WriteReq accesses 63011754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.089066 # mshr miss rate for LoadLockedReq accesses 63111754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.089066 # mshr miss rate for LoadLockedReq accesses 63211680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.037675 # mshr miss rate for StoreCondReq accesses 63311680SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.037675 # mshr miss rate for StoreCondReq accesses 63411754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097333 # mshr miss rate for demand accesses 63511754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.097333 # mshr miss rate for demand accesses 63611754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097333 # mshr miss rate for overall accesses 63711754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.097333 # mshr miss rate for overall accesses 63811754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32263.730935 # average ReadReq mshr miss latency 63911754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32263.730935 # average ReadReq mshr miss latency 64011754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48591.742221 # average WriteReq mshr miss latency 64111754Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48591.742221 # average WriteReq mshr miss latency 64211754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10064.606328 # average LoadLockedReq mshr miss latency 64311754Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10064.606328 # average LoadLockedReq mshr miss latency 64411754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4578.299581 # average StoreCondReq mshr miss latency 64511754Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4578.299581 # average StoreCondReq mshr miss latency 64611754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35756.248707 # average overall mshr miss latency 64711754Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 35756.248707 # average overall mshr miss latency 64811754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35756.248707 # average overall mshr miss latency 64911754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 35756.248707 # average overall mshr miss latency 65011754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222272.656581 # average ReadReq mshr uncacheable latency 65111754Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222272.656581 # average ReadReq mshr uncacheable latency 65211754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 88198.288920 # average overall mshr uncacheable latency 65311754Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 88198.288920 # average overall mshr uncacheable latency 65411754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 65511754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 692168 # number of replacements 65611680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tagsinuse 507.922544 # Cycle average of tags in use 65711754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 47009511 # Total number of references to valid blocks. 65811754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 692680 # Sample count of references to valid blocks. 65911754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 67.866130 # Average number of references to valid blocks. 66011754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 44813247500 # Cycle when the warmup percentage was hit. 66111680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 507.922544 # Average occupied blocks per requestor 66211680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.992036 # Average percentage of cache occupancy 66311680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.992036 # Average percentage of cache occupancy 66410726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 66511680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id 66611680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 66711680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 435 # Occupied blocks per task id 66811680SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id 66910726Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 67011754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 48395123 # Number of tag accesses 67111754Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 48395123 # Number of data accesses 67211754Sandreas.hansson@arm.comsystem.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 67311754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 47009511 # number of ReadReq hits 67411754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 47009511 # number of ReadReq hits 67511754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 47009511 # number of demand (read+write) hits 67611754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 47009511 # number of demand (read+write) hits 67711754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 47009511 # number of overall hits 67811754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 47009511 # number of overall hits 67911754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 692806 # number of ReadReq misses 68011754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 692806 # number of ReadReq misses 68111754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 692806 # number of demand (read+write) misses 68211754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 692806 # number of demand (read+write) misses 68311754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 692806 # number of overall misses 68411754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 692806 # number of overall misses 68511754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10342349000 # number of ReadReq miss cycles 68611754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 10342349000 # number of ReadReq miss cycles 68711754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 10342349000 # number of demand (read+write) miss cycles 68811754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::total 10342349000 # number of demand (read+write) miss cycles 68911754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 10342349000 # number of overall miss cycles 69011754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::total 10342349000 # number of overall miss cycles 69111754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 47702317 # number of ReadReq accesses(hits+misses) 69211754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 47702317 # number of ReadReq accesses(hits+misses) 69311754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 47702317 # number of demand (read+write) accesses 69411754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 47702317 # number of demand (read+write) accesses 69511754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 47702317 # number of overall (read+write) accesses 69611754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 47702317 # number of overall (read+write) accesses 69711754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014524 # miss rate for ReadReq accesses 69811754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.014524 # miss rate for ReadReq accesses 69911754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.014524 # miss rate for demand accesses 70011754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.014524 # miss rate for demand accesses 70111754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.014524 # miss rate for overall accesses 70211754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.014524 # miss rate for overall accesses 70311754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14928.203566 # average ReadReq miss latency 70411754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 14928.203566 # average ReadReq miss latency 70511754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14928.203566 # average overall miss latency 70611754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 14928.203566 # average overall miss latency 70711754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14928.203566 # average overall miss latency 70811754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 14928.203566 # average overall miss latency 70910585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 71010585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 71110585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 71210585Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 71310585Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 71410585Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 71511754Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::writebacks 692168 # number of writebacks 71611754Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::total 692168 # number of writebacks 71711754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 692806 # number of ReadReq MSHR misses 71811754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 692806 # number of ReadReq MSHR misses 71911754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 692806 # number of demand (read+write) MSHR misses 72011754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::total 692806 # number of demand (read+write) MSHR misses 72111754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 692806 # number of overall MSHR misses 72211754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::total 692806 # number of overall MSHR misses 72311754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9649543000 # number of ReadReq MSHR miss cycles 72411754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 9649543000 # number of ReadReq MSHR miss cycles 72511754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9649543000 # number of demand (read+write) MSHR miss cycles 72611754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 9649543000 # number of demand (read+write) MSHR miss cycles 72711754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9649543000 # number of overall MSHR miss cycles 72811754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 9649543000 # number of overall MSHR miss cycles 72911754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for ReadReq accesses 73011754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014524 # mshr miss rate for ReadReq accesses 73111754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for demand accesses 73211754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.014524 # mshr miss rate for demand accesses 73311754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014524 # mshr miss rate for overall accesses 73411754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.014524 # mshr miss rate for overall accesses 73511754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13928.203566 # average ReadReq mshr miss latency 73611754Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13928.203566 # average ReadReq mshr miss latency 73711754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13928.203566 # average overall mshr miss latency 73811754Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 13928.203566 # average overall mshr miss latency 73911754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13928.203566 # average overall mshr miss latency 74011754Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 13928.203566 # average overall mshr miss latency 74110585Sandreas.hansson@arm.comsystem.cpu1.dtb.fetch_hits 0 # ITB hits 74210585Sandreas.hansson@arm.comsystem.cpu1.dtb.fetch_misses 0 # ITB misses 74310585Sandreas.hansson@arm.comsystem.cpu1.dtb.fetch_acv 0 # ITB acv 74410585Sandreas.hansson@arm.comsystem.cpu1.dtb.fetch_accesses 0 # ITB accesses 74511754Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 2442461 # DTB read hits 74611680SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_misses 2621 # DTB read misses 74710585Sandreas.hansson@arm.comsystem.cpu1.dtb.read_acv 0 # DTB read access violations 74811680SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_accesses 205338 # DTB read accesses 74911754Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 1749247 # DTB write hits 75011680SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_misses 236 # DTB write misses 75111680SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_acv 24 # DTB write access violations 75211680SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_accesses 89740 # DTB write accesses 75311754Sandreas.hansson@arm.comsystem.cpu1.dtb.data_hits 4191708 # DTB hits 75411680SCurtis.Dunham@arm.comsystem.cpu1.dtb.data_misses 2857 # DTB misses 75511680SCurtis.Dunham@arm.comsystem.cpu1.dtb.data_acv 24 # DTB access violations 75611680SCurtis.Dunham@arm.comsystem.cpu1.dtb.data_accesses 295078 # DTB accesses 75711754Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_hits 1826964 # ITB hits 75811680SCurtis.Dunham@arm.comsystem.cpu1.itb.fetch_misses 1064 # ITB misses 75910585Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_acv 0 # ITB acv 76011754Sandreas.hansson@arm.comsystem.cpu1.itb.fetch_accesses 1828028 # ITB accesses 76110585Sandreas.hansson@arm.comsystem.cpu1.itb.read_hits 0 # DTB read hits 76210585Sandreas.hansson@arm.comsystem.cpu1.itb.read_misses 0 # DTB read misses 76310585Sandreas.hansson@arm.comsystem.cpu1.itb.read_acv 0 # DTB read access violations 76410585Sandreas.hansson@arm.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 76510585Sandreas.hansson@arm.comsystem.cpu1.itb.write_hits 0 # DTB write hits 76610585Sandreas.hansson@arm.comsystem.cpu1.itb.write_misses 0 # DTB write misses 76710585Sandreas.hansson@arm.comsystem.cpu1.itb.write_acv 0 # DTB write access violations 76810585Sandreas.hansson@arm.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 76910585Sandreas.hansson@arm.comsystem.cpu1.itb.data_hits 0 # DTB hits 77010585Sandreas.hansson@arm.comsystem.cpu1.itb.data_misses 0 # DTB misses 77110585Sandreas.hansson@arm.comsystem.cpu1.itb.data_acv 0 # DTB access violations 77210585Sandreas.hansson@arm.comsystem.cpu1.itb.data_accesses 0 # DTB accesses 77311680SCurtis.Dunham@arm.comsystem.cpu1.numPwrStateTransitions 5609 # Number of power state transitions 77411680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::samples 2805 # Distribution of time spent in the clock gated state 77511754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::mean 692201198.395722 # Distribution of time spent in the clock gated state 77611754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::stdev 417085998.942743 # Distribution of time spent in the clock gated state 77711680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::1000-5e+10 2805 100.00% 100.00% # Distribution of time spent in the clock gated state 77811754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::min_value 61500 # Distribution of time spent in the clock gated state 77911754Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::max_value 974672500 # Distribution of time spent in the clock gated state 78011680SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::total 2805 # Distribution of time spent in the clock gated state 78111754Sandreas.hansson@arm.comsystem.cpu1.pwrStateResidencyTicks::ON 25117814500 # Cumulative time (in ticks) in various power states 78211754Sandreas.hansson@arm.comsystem.cpu1.pwrStateResidencyTicks::CLK_GATED 1941624361500 # Cumulative time (in ticks) in various power states 78311754Sandreas.hansson@arm.comsystem.cpu1.numCycles 3931646343 # number of cpu cycles simulated 78410585Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 78510585Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 78610585Sandreas.hansson@arm.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 78711680SCurtis.Dunham@arm.comsystem.cpu1.kern.inst.quiesce 2805 # number of quiesce instructions executed 78811754Sandreas.hansson@arm.comsystem.cpu1.kern.inst.hwrei 79704 # number of hwrei instructions executed 78911754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::0 27198 38.42% 38.42% # number of times we switched to this ipl 79011680SCurtis.Dunham@arm.comsystem.cpu1.kern.ipl_count::22 1969 2.78% 41.20% # number of times we switched to this ipl 79111680SCurtis.Dunham@arm.comsystem.cpu1.kern.ipl_count::30 525 0.74% 41.94% # number of times we switched to this ipl 79211754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::31 41099 58.06% 100.00% # number of times we switched to this ipl 79311754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_count::total 70791 # number of times we switched to this ipl 79411754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::0 26333 48.20% 48.20% # number of times we switched to this ipl from a different ipl 79511680SCurtis.Dunham@arm.comsystem.cpu1.kern.ipl_good::22 1969 3.60% 51.80% # number of times we switched to this ipl from a different ipl 79611680SCurtis.Dunham@arm.comsystem.cpu1.kern.ipl_good::30 525 0.96% 52.76% # number of times we switched to this ipl from a different ipl 79711754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::31 25808 47.24% 100.00% # number of times we switched to this ipl from a different ipl 79811754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_good::total 54635 # number of times we switched to this ipl from a different ipl 79911754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::0 1909855455500 97.15% 97.15% # number of cycles we spent at this ipl 80011754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::22 731138500 0.04% 97.19% # number of cycles we spent at this ipl 80111754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::30 371933000 0.02% 97.21% # number of cycles we spent at this ipl 80211754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::31 54864614500 2.79% 100.00% # number of cycles we spent at this ipl 80311754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_ticks::total 1965823141500 # number of cycles we spent at this ipl 80411754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::0 0.968196 # fraction of swpipl calls that actually changed the ipl 80510585Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 80610585Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl 80711754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::31 0.627947 # fraction of swpipl calls that actually changed the ipl 80811754Sandreas.hansson@arm.comsystem.cpu1.kern.ipl_used::total 0.771779 # fraction of swpipl calls that actually changed the ipl 80910585Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 81011680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::wripir 433 0.59% 0.59% # number of callpals executed 81111245Sandreas.sandberg@arm.comsystem.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed 81211606Sandreas.sandberg@arm.comsystem.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed 81311680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::swpctx 2016 2.75% 3.35% # number of callpals executed 81411680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::tbi 3 0.00% 3.35% # number of callpals executed 81511680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::wrent 7 0.01% 3.36% # number of callpals executed 81611754Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::swpipl 64571 88.14% 91.50% # number of callpals executed 81711680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::rdps 2334 3.19% 94.68% # number of callpals executed 81811680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::wrkgp 1 0.00% 94.68% # number of callpals executed 81911680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::wrusp 3 0.00% 94.69% # number of callpals executed 82011680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::whami 3 0.00% 94.69% # number of callpals executed 82111680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::rti 3725 5.08% 99.78% # number of callpals executed 82211680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed 82311680SCurtis.Dunham@arm.comsystem.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed 82410585Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed 82511754Sandreas.hansson@arm.comsystem.cpu1.kern.callpal::total 73263 # number of callpals executed 82611680SCurtis.Dunham@arm.comsystem.cpu1.kern.mode_switch::kernel 1964 # number of protection mode switches 82711680SCurtis.Dunham@arm.comsystem.cpu1.kern.mode_switch::user 367 # number of protection mode switches 82811680SCurtis.Dunham@arm.comsystem.cpu1.kern.mode_switch::idle 2923 # number of protection mode switches 82911680SCurtis.Dunham@arm.comsystem.cpu1.kern.mode_good::kernel 816 83011680SCurtis.Dunham@arm.comsystem.cpu1.kern.mode_good::user 367 83111680SCurtis.Dunham@arm.comsystem.cpu1.kern.mode_good::idle 449 83211680SCurtis.Dunham@arm.comsystem.cpu1.kern.mode_switch_good::kernel 0.415479 # fraction of useful protection mode switches 83310585Sandreas.hansson@arm.comsystem.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 83411680SCurtis.Dunham@arm.comsystem.cpu1.kern.mode_switch_good::idle 0.153609 # fraction of useful protection mode switches 83511680SCurtis.Dunham@arm.comsystem.cpu1.kern.mode_switch_good::total 0.310620 # fraction of useful protection mode switches 83611754Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::kernel 18379231500 0.94% 0.94% # number of ticks spent at the given mode 83711754Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::user 1492112000 0.08% 1.01% # number of ticks spent at the given mode 83811754Sandreas.hansson@arm.comsystem.cpu1.kern.mode_ticks::idle 1945079443000 98.99% 100.00% # number of ticks spent at the given mode 83911680SCurtis.Dunham@arm.comsystem.cpu1.kern.swap_context 2017 # number of times the context was actually changed 84011754Sandreas.hansson@arm.comsystem.cpu1.committedInsts 13268542 # Number of instructions committed 84111754Sandreas.hansson@arm.comsystem.cpu1.committedOps 13268542 # Number of ops (including micro ops) committed 84211754Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses 12224320 # Number of integer alu accesses 84311680SCurtis.Dunham@arm.comsystem.cpu1.num_fp_alu_accesses 175144 # Number of float alu accesses 84411754Sandreas.hansson@arm.comsystem.cpu1.num_func_calls 423403 # number of times a function call or return occured 84511754Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts 1315333 # number of instructions that are conditional controls 84611754Sandreas.hansson@arm.comsystem.cpu1.num_int_insts 12224320 # number of integer instructions 84711680SCurtis.Dunham@arm.comsystem.cpu1.num_fp_insts 175144 # number of float instructions 84811754Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads 16795598 # number of times the integer registers were read 84911754Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes 8988647 # number of times the integer registers were written 85011680SCurtis.Dunham@arm.comsystem.cpu1.num_fp_register_reads 90944 # number of times the floating registers were read 85111680SCurtis.Dunham@arm.comsystem.cpu1.num_fp_register_writes 92918 # number of times the floating registers were written 85211754Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs 4214775 # number of memory refs 85311754Sandreas.hansson@arm.comsystem.cpu1.num_load_insts 2456291 # Number of load instructions 85411754Sandreas.hansson@arm.comsystem.cpu1.num_store_insts 1758484 # Number of store instructions 85511754Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles 3881434187.727123 # Number of idle cycles 85611754Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles 50212155.272877 # Number of busy cycles 85711754Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.012771 # Percentage of non-idle cycles 85811754Sandreas.hansson@arm.comsystem.cpu1.idle_fraction 0.987229 # Percentage of idle cycles 85911754Sandreas.hansson@arm.comsystem.cpu1.Branches 1898911 # Number of branches fetched 86011754Sandreas.hansson@arm.comsystem.cpu1.op_class::No_OpClass 719210 5.42% 5.42% # Class of executed instruction 86111754Sandreas.hansson@arm.comsystem.cpu1.op_class::IntAlu 7860972 59.23% 64.65% # Class of executed instruction 86211754Sandreas.hansson@arm.comsystem.cpu1.op_class::IntMult 22603 0.17% 64.82% # Class of executed instruction 86311680SCurtis.Dunham@arm.comsystem.cpu1.op_class::IntDiv 0 0.00% 64.82% # Class of executed instruction 86411680SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatAdd 13252 0.10% 64.92% # Class of executed instruction 86511680SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 64.92% # Class of executed instruction 86611680SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 64.92% # Class of executed instruction 86711680SCurtis.Dunham@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 64.92% # Class of executed instruction 86811687Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMultAcc 0 0.00% 64.92% # Class of executed instruction 86911754Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatDiv 1759 0.01% 64.93% # Class of executed instruction 87011754Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMisc 0 0.00% 64.93% # Class of executed instruction 87111754Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 64.93% # Class of executed instruction 87211754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 64.93% # Class of executed instruction 87311754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 64.93% # Class of executed instruction 87411754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 64.93% # Class of executed instruction 87511754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 64.93% # Class of executed instruction 87611754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 64.93% # Class of executed instruction 87711754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 64.93% # Class of executed instruction 87811754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 64.93% # Class of executed instruction 87911754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 64.93% # Class of executed instruction 88011754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 64.93% # Class of executed instruction 88111754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 64.93% # Class of executed instruction 88211754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 64.93% # Class of executed instruction 88311754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 64.93% # Class of executed instruction 88411754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 64.93% # Class of executed instruction 88511754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 64.93% # Class of executed instruction 88611754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 64.93% # Class of executed instruction 88711754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 64.93% # Class of executed instruction 88811754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMisc 0 0.00% 64.93% # Class of executed instruction 88911754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 64.93% # Class of executed instruction 89011754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.93% # Class of executed instruction 89111754Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.93% # Class of executed instruction 89211754Sandreas.hansson@arm.comsystem.cpu1.op_class::MemRead 2447819 18.44% 83.38% # Class of executed instruction 89311754Sandreas.hansson@arm.comsystem.cpu1.op_class::MemWrite 1681290 12.67% 96.05% # Class of executed instruction 89411687Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMemRead 81935 0.62% 96.67% # Class of executed instruction 89511687Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMemWrite 78198 0.59% 97.25% # Class of executed instruction 89611754Sandreas.hansson@arm.comsystem.cpu1.op_class::IprAccess 364385 2.75% 100.00% # Class of executed instruction 89711201Sandreas.hansson@arm.comsystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 89811754Sandreas.hansson@arm.comsystem.cpu1.op_class::total 13271423 # Class of executed instruction 89911754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 90011754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 162127 # number of replacements 90111754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 484.320008 # Cycle average of tags in use 90211754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 4015090 # Total number of references to valid blocks. 90311754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 162456 # Sample count of references to valid blocks. 90411754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 24.714938 # Average number of references to valid blocks. 90511754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 72636345500 # Cycle when the warmup percentage was hit. 90611754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 484.320008 # Average occupied blocks per requestor 90711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.945938 # Average percentage of cache occupancy 90811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.945938 # Average percentage of cache occupancy 90911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 329 # Occupied blocks per task id 91011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id 91111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::3 297 # Occupied blocks per task id 91211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.642578 # Percentage of cache occupancy per task id 91311754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 16996743 # Number of tag accesses 91411754Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 16996743 # Number of data accesses 91511754Sandreas.hansson@arm.comsystem.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 91611754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 2273788 # number of ReadReq hits 91711754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 2273788 # number of ReadReq hits 91811754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 1634135 # number of WriteReq hits 91911754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 1634135 # number of WriteReq hits 92011754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 51915 # number of LoadLockedReq hits 92111754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 51915 # number of LoadLockedReq hits 92211754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 52085 # number of StoreCondReq hits 92311754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 52085 # number of StoreCondReq hits 92411754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 3907923 # number of demand (read+write) hits 92511754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 3907923 # number of demand (read+write) hits 92611754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 3907923 # number of overall hits 92711754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 3907923 # number of overall hits 92811754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 118690 # number of ReadReq misses 92911754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 118690 # number of ReadReq misses 93011754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 58791 # number of WriteReq misses 93111754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 58791 # number of WriteReq misses 93211754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 9152 # number of LoadLockedReq misses 93311754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 9152 # number of LoadLockedReq misses 93411754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 6117 # number of StoreCondReq misses 93511754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 6117 # number of StoreCondReq misses 93611754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 177481 # number of demand (read+write) misses 93711754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 177481 # number of demand (read+write) misses 93811754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 177481 # number of overall misses 93911754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 177481 # number of overall misses 94011754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1467443500 # number of ReadReq miss cycles 94111754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 1467443500 # number of ReadReq miss cycles 94211754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1300528500 # number of WriteReq miss cycles 94311754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 1300528500 # number of WriteReq miss cycles 94411754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 84062000 # number of LoadLockedReq miss cycles 94511754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 84062000 # number of LoadLockedReq miss cycles 94611754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 34151000 # number of StoreCondReq miss cycles 94711754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 34151000 # number of StoreCondReq miss cycles 94811754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 2767972000 # number of demand (read+write) miss cycles 94911754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::total 2767972000 # number of demand (read+write) miss cycles 95011754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 2767972000 # number of overall miss cycles 95111754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::total 2767972000 # number of overall miss cycles 95211754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 2392478 # number of ReadReq accesses(hits+misses) 95311754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 2392478 # number of ReadReq accesses(hits+misses) 95411754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 1692926 # number of WriteReq accesses(hits+misses) 95511754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 1692926 # number of WriteReq accesses(hits+misses) 95611754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 61067 # number of LoadLockedReq accesses(hits+misses) 95711754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 61067 # number of LoadLockedReq accesses(hits+misses) 95811754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 58202 # number of StoreCondReq accesses(hits+misses) 95911754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 58202 # number of StoreCondReq accesses(hits+misses) 96011754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 4085404 # number of demand (read+write) accesses 96111754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 4085404 # number of demand (read+write) accesses 96211754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 4085404 # number of overall (read+write) accesses 96311754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 4085404 # number of overall (read+write) accesses 96411754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049610 # miss rate for ReadReq accesses 96511754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.049610 # miss rate for ReadReq accesses 96611754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034727 # miss rate for WriteReq accesses 96711754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.034727 # miss rate for WriteReq accesses 96811754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149868 # miss rate for LoadLockedReq accesses 96911754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.149868 # miss rate for LoadLockedReq accesses 97011754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105099 # miss rate for StoreCondReq accesses 97111754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.105099 # miss rate for StoreCondReq accesses 97211754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.043443 # miss rate for demand accesses 97311754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.043443 # miss rate for demand accesses 97411754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.043443 # miss rate for overall accesses 97511754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.043443 # miss rate for overall accesses 97611754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12363.665852 # average ReadReq miss latency 97711754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 12363.665852 # average ReadReq miss latency 97811754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22121.217533 # average WriteReq miss latency 97911754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 22121.217533 # average WriteReq miss latency 98011754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9185.096154 # average LoadLockedReq miss latency 98111754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9185.096154 # average LoadLockedReq miss latency 98211754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5582.965506 # average StoreCondReq miss latency 98311754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5582.965506 # average StoreCondReq miss latency 98411754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15595.877869 # average overall miss latency 98511754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 15595.877869 # average overall miss latency 98611754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15595.877869 # average overall miss latency 98711754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 15595.877869 # average overall miss latency 98810585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 98910585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 99010585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 99110585Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 99210585Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 99310585Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 99411754Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 111642 # number of writebacks 99511754Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 111642 # number of writebacks 99611754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118690 # number of ReadReq MSHR misses 99711754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 118690 # number of ReadReq MSHR misses 99811754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 58791 # number of WriteReq MSHR misses 99911754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 58791 # number of WriteReq MSHR misses 100011754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9152 # number of LoadLockedReq MSHR misses 100111754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 9152 # number of LoadLockedReq MSHR misses 100211754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 6117 # number of StoreCondReq MSHR misses 100311754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 6117 # number of StoreCondReq MSHR misses 100411754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 177481 # number of demand (read+write) MSHR misses 100511754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 177481 # number of demand (read+write) MSHR misses 100611754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 177481 # number of overall MSHR misses 100711754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 177481 # number of overall MSHR misses 100811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 125 # number of ReadReq MSHR uncacheable 100911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::total 125 # number of ReadReq MSHR uncacheable 101011680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3371 # number of WriteReq MSHR uncacheable 101111680SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::total 3371 # number of WriteReq MSHR uncacheable 101211680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3496 # number of overall MSHR uncacheable misses 101311680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::total 3496 # number of overall MSHR uncacheable misses 101411754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1348753500 # number of ReadReq MSHR miss cycles 101511754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 1348753500 # number of ReadReq MSHR miss cycles 101611754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1241737500 # number of WriteReq MSHR miss cycles 101711754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 1241737500 # number of WriteReq MSHR miss cycles 101811754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74910000 # number of LoadLockedReq MSHR miss cycles 101911754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 74910000 # number of LoadLockedReq MSHR miss cycles 102011754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 28034000 # number of StoreCondReq MSHR miss cycles 102111754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 28034000 # number of StoreCondReq MSHR miss cycles 102211754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2590491000 # number of demand (read+write) MSHR miss cycles 102311754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 2590491000 # number of demand (read+write) MSHR miss cycles 102411754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2590491000 # number of overall MSHR miss cycles 102511754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 2590491000 # number of overall MSHR miss cycles 102611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 26291000 # number of ReadReq MSHR uncacheable cycles 102711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 26291000 # number of ReadReq MSHR uncacheable cycles 102811680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 26291000 # number of overall MSHR uncacheable cycles 102911680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 26291000 # number of overall MSHR uncacheable cycles 103011754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049610 # mshr miss rate for ReadReq accesses 103111754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049610 # mshr miss rate for ReadReq accesses 103211754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034727 # mshr miss rate for WriteReq accesses 103311754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034727 # mshr miss rate for WriteReq accesses 103411754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.149868 # mshr miss rate for LoadLockedReq accesses 103511754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.149868 # mshr miss rate for LoadLockedReq accesses 103611754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105099 # mshr miss rate for StoreCondReq accesses 103711754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105099 # mshr miss rate for StoreCondReq accesses 103811754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043443 # mshr miss rate for demand accesses 103911754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.043443 # mshr miss rate for demand accesses 104011754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043443 # mshr miss rate for overall accesses 104111754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.043443 # mshr miss rate for overall accesses 104211754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11363.665852 # average ReadReq mshr miss latency 104311754Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11363.665852 # average ReadReq mshr miss latency 104411754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21121.217533 # average WriteReq mshr miss latency 104511754Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21121.217533 # average WriteReq mshr miss latency 104611754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8185.096154 # average LoadLockedReq mshr miss latency 104711754Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8185.096154 # average LoadLockedReq mshr miss latency 104811754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4582.965506 # average StoreCondReq mshr miss latency 104911754Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4582.965506 # average StoreCondReq mshr miss latency 105011754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14595.877869 # average overall mshr miss latency 105111754Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 14595.877869 # average overall mshr miss latency 105211754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14595.877869 # average overall mshr miss latency 105311754Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 14595.877869 # average overall mshr miss latency 105411680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 210328 # average ReadReq mshr uncacheable latency 105511680SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 210328 # average ReadReq mshr uncacheable latency 105611680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 7520.308924 # average overall mshr uncacheable latency 105711680SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 7520.308924 # average overall mshr uncacheable latency 105811754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 105911754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 326560 # number of replacements 106011754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 445.783409 # Cycle average of tags in use 106111754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 12944312 # Total number of references to valid blocks. 106211754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 327071 # Sample count of references to valid blocks. 106311754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 39.576459 # Average number of references to valid blocks. 106411754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 1960887860500 # Cycle when the warmup percentage was hit. 106511754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 445.783409 # Average occupied blocks per requestor 106611680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.870671 # Average percentage of cache occupancy 106711680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.870671 # Average percentage of cache occupancy 106811680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 106911680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id 107011680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::3 434 # Occupied blocks per task id 107111680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id 107211680SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 107311754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 13598534 # Number of tag accesses 107411754Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 13598534 # Number of data accesses 107511754Sandreas.hansson@arm.comsystem.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 107611754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 12944312 # number of ReadReq hits 107711754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 12944312 # number of ReadReq hits 107811754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 12944312 # number of demand (read+write) hits 107911754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 12944312 # number of demand (read+write) hits 108011754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 12944312 # number of overall hits 108111754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 12944312 # number of overall hits 108211754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 327111 # number of ReadReq misses 108311754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 327111 # number of ReadReq misses 108411754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 327111 # number of demand (read+write) misses 108511754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 327111 # number of demand (read+write) misses 108611754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 327111 # number of overall misses 108711754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 327111 # number of overall misses 108811754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4448984500 # number of ReadReq miss cycles 108911754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 4448984500 # number of ReadReq miss cycles 109011754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 4448984500 # number of demand (read+write) miss cycles 109111754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::total 4448984500 # number of demand (read+write) miss cycles 109211754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 4448984500 # number of overall miss cycles 109311754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::total 4448984500 # number of overall miss cycles 109411754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 13271423 # number of ReadReq accesses(hits+misses) 109511754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 13271423 # number of ReadReq accesses(hits+misses) 109611754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 13271423 # number of demand (read+write) accesses 109711754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 13271423 # number of demand (read+write) accesses 109811754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 13271423 # number of overall (read+write) accesses 109911754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 13271423 # number of overall (read+write) accesses 110011754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024648 # miss rate for ReadReq accesses 110111754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.024648 # miss rate for ReadReq accesses 110211754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.024648 # miss rate for demand accesses 110311754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.024648 # miss rate for demand accesses 110411754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.024648 # miss rate for overall accesses 110511754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.024648 # miss rate for overall accesses 110611754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13600.840388 # average ReadReq miss latency 110711754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 13600.840388 # average ReadReq miss latency 110811754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13600.840388 # average overall miss latency 110911754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 13600.840388 # average overall miss latency 111011754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13600.840388 # average overall miss latency 111111754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 13600.840388 # average overall miss latency 111210585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 111310585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 111410585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 111510585Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 111610585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 111710585Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 111811754Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::writebacks 326560 # number of writebacks 111911754Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::total 326560 # number of writebacks 112011754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 327111 # number of ReadReq MSHR misses 112111754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 327111 # number of ReadReq MSHR misses 112211754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 327111 # number of demand (read+write) MSHR misses 112311754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::total 327111 # number of demand (read+write) MSHR misses 112411754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 327111 # number of overall MSHR misses 112511754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::total 327111 # number of overall MSHR misses 112611754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4121873500 # number of ReadReq MSHR miss cycles 112711754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 4121873500 # number of ReadReq MSHR miss cycles 112811754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4121873500 # number of demand (read+write) MSHR miss cycles 112911754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 4121873500 # number of demand (read+write) MSHR miss cycles 113011754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4121873500 # number of overall MSHR miss cycles 113111754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 4121873500 # number of overall MSHR miss cycles 113211754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024648 # mshr miss rate for ReadReq accesses 113311754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024648 # mshr miss rate for ReadReq accesses 113411754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024648 # mshr miss rate for demand accesses 113511754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.024648 # mshr miss rate for demand accesses 113611754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024648 # mshr miss rate for overall accesses 113711754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.024648 # mshr miss rate for overall accesses 113811754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12600.840388 # average ReadReq mshr miss latency 113911754Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12600.840388 # average ReadReq mshr miss latency 114011754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12600.840388 # average overall mshr miss latency 114111754Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 12600.840388 # average overall mshr miss latency 114211754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12600.840388 # average overall mshr miss latency 114311754Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 12600.840388 # average overall mshr miss latency 114410585Sandreas.hansson@arm.comsystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 114510585Sandreas.hansson@arm.comsystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 114610585Sandreas.hansson@arm.comsystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 114710585Sandreas.hansson@arm.comsystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 114810585Sandreas.hansson@arm.comsystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 114910585Sandreas.hansson@arm.comsystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 115010585Sandreas.hansson@arm.comsystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 115110585Sandreas.hansson@arm.comsystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 115210585Sandreas.hansson@arm.comsystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 115310585Sandreas.hansson@arm.comsystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 115410585Sandreas.hansson@arm.comsystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 115510585Sandreas.hansson@arm.comsystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 115611754Sandreas.hansson@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 115711680SCurtis.Dunham@arm.comsystem.iobus.trans_dist::ReadReq 7376 # Transaction distribution 115811680SCurtis.Dunham@arm.comsystem.iobus.trans_dist::ReadResp 7376 # Transaction distribution 115911680SCurtis.Dunham@arm.comsystem.iobus.trans_dist::WriteReq 55675 # Transaction distribution 116011680SCurtis.Dunham@arm.comsystem.iobus.trans_dist::WriteResp 55675 # Transaction distribution 116111680SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 14036 # Packet count per connected master and slave (bytes) 116211680SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes) 116310585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 116410585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 116511502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 116611502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) 116711502SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2474 # Packet count per connected master and slave (bytes) 116811356Skrinat01@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 116910585Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 117011680SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.bridge.master::total 42642 # Packet count per connected master and slave (bytes) 117111680SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) 117211680SCurtis.Dunham@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes) 117311680SCurtis.Dunham@arm.comsystem.iobus.pkt_count::total 126102 # Packet count per connected master and slave (bytes) 117411680SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 56144 # Cumulative packet size per connected master and slave (bytes) 117511680SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes) 117610585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 117710585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 117811502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 117911502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) 118011502SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9876 # Cumulative packet size per connected master and slave (bytes) 118111356Skrinat01@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 118210585Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 118311680SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.bridge.master::total 82394 # Cumulative packet size per connected master and slave (bytes) 118411680SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) 118511680SCurtis.Dunham@arm.comsystem.iobus.pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes) 118611680SCurtis.Dunham@arm.comsystem.iobus.pkt_size::total 2744042 # Cumulative packet size per connected master and slave (bytes) 118711680SCurtis.Dunham@arm.comsystem.iobus.reqLayer0.occupancy 15108500 # Layer occupancy (ticks) 118810585Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 118911754Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 758500 # Layer occupancy (ticks) 119010585Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 119111201Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 9500 # Layer occupancy (ticks) 119210585Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 119311201Sandreas.hansson@arm.comsystem.iobus.reqLayer6.occupancy 10000 # Layer occupancy (ticks) 119410585Sandreas.hansson@arm.comsystem.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 119511680SCurtis.Dunham@arm.comsystem.iobus.reqLayer22.occupancy 174000 # Layer occupancy (ticks) 119610585Sandreas.hansson@arm.comsystem.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 119711680SCurtis.Dunham@arm.comsystem.iobus.reqLayer23.occupancy 15840500 # Layer occupancy (ticks) 119810585Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 119911502SCurtis.Dunham@arm.comsystem.iobus.reqLayer24.occupancy 2459000 # Layer occupancy (ticks) 120010585Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 120111680SCurtis.Dunham@arm.comsystem.iobus.reqLayer25.occupancy 6051000 # Layer occupancy (ticks) 120210585Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 120311502SCurtis.Dunham@arm.comsystem.iobus.reqLayer26.occupancy 82500 # Layer occupancy (ticks) 120410585Sandreas.hansson@arm.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 120511754Sandreas.hansson@arm.comsystem.iobus.reqLayer27.occupancy 216236013 # Layer occupancy (ticks) 120610585Sandreas.hansson@arm.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 120711680SCurtis.Dunham@arm.comsystem.iobus.respLayer0.occupancy 28519000 # Layer occupancy (ticks) 120810585Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 120911680SCurtis.Dunham@arm.comsystem.iobus.respLayer1.occupancy 41956000 # Layer occupancy (ticks) 121010585Sandreas.hansson@arm.comsystem.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 121111754Sandreas.hansson@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 121211680SCurtis.Dunham@arm.comsystem.iocache.tags.replacements 41698 # number of replacements 121311754Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 0.568425 # Cycle average of tags in use 121410585Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 121511680SCurtis.Dunham@arm.comsystem.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. 121610585Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 121711754Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 1760410358000 # Cycle when the warmup percentage was hit. 121811754Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide 0.568425 # Average occupied blocks per requestor 121911754Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::tsunami.ide 0.035527 # Average percentage of cache occupancy 122011754Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.035527 # Average percentage of cache occupancy 122110585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 122210585Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 122310585Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 122411680SCurtis.Dunham@arm.comsystem.iocache.tags.tag_accesses 375570 # Number of tag accesses 122511680SCurtis.Dunham@arm.comsystem.iocache.tags.data_accesses 375570 # Number of data accesses 122611754Sandreas.hansson@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 122711680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses 122811680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_misses::total 178 # number of ReadReq misses 122910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 123010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses 123111680SCurtis.Dunham@arm.comsystem.iocache.demand_misses::tsunami.ide 41730 # number of demand (read+write) misses 123211680SCurtis.Dunham@arm.comsystem.iocache.demand_misses::total 41730 # number of demand (read+write) misses 123311680SCurtis.Dunham@arm.comsystem.iocache.overall_misses::tsunami.ide 41730 # number of overall misses 123411680SCurtis.Dunham@arm.comsystem.iocache.overall_misses::total 41730 # number of overall misses 123511680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_miss_latency::tsunami.ide 22412883 # number of ReadReq miss cycles 123611680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_miss_latency::total 22412883 # number of ReadReq miss cycles 123711754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::tsunami.ide 4955951130 # number of WriteLineReq miss cycles 123811754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::total 4955951130 # number of WriteLineReq miss cycles 123911754Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::tsunami.ide 4978364013 # number of demand (read+write) miss cycles 124011754Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 4978364013 # number of demand (read+write) miss cycles 124111754Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::tsunami.ide 4978364013 # number of overall miss cycles 124211754Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 4978364013 # number of overall miss cycles 124311680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) 124411680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) 124510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 124610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) 124711680SCurtis.Dunham@arm.comsystem.iocache.demand_accesses::tsunami.ide 41730 # number of demand (read+write) accesses 124811680SCurtis.Dunham@arm.comsystem.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses 124911680SCurtis.Dunham@arm.comsystem.iocache.overall_accesses::tsunami.ide 41730 # number of overall (read+write) accesses 125011680SCurtis.Dunham@arm.comsystem.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses 125110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 125210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 125310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 125410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 125510585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 125610585Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 125710585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 125810585Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 125911680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_miss_latency::tsunami.ide 125915.073034 # average ReadReq miss latency 126011680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 125915.073034 # average ReadReq miss latency 126111754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 119271.061080 # average WriteLineReq miss latency 126211754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 119271.061080 # average WriteLineReq miss latency 126311754Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::tsunami.ide 119299.401222 # average overall miss latency 126411754Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 119299.401222 # average overall miss latency 126511754Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::tsunami.ide 119299.401222 # average overall miss latency 126611754Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 119299.401222 # average overall miss latency 126711680SCurtis.Dunham@arm.comsystem.iocache.blocked_cycles::no_mshrs 1665 # number of cycles access was blocked 126810585Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 126911680SCurtis.Dunham@arm.comsystem.iocache.blocked::no_mshrs 10 # number of cycles access was blocked 127010585Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 127111680SCurtis.Dunham@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 166.500000 # average number of cycles each access was blocked 127210585Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 127311245Sandreas.sandberg@arm.comsystem.iocache.writebacks::writebacks 41520 # number of writebacks 127411245Sandreas.sandberg@arm.comsystem.iocache.writebacks::total 41520 # number of writebacks 127511680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses 127611680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses 127710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses 127810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses 127911680SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_misses::tsunami.ide 41730 # number of demand (read+write) MSHR misses 128011680SCurtis.Dunham@arm.comsystem.iocache.demand_mshr_misses::total 41730 # number of demand (read+write) MSHR misses 128111680SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_misses::tsunami.ide 41730 # number of overall MSHR misses 128211680SCurtis.Dunham@arm.comsystem.iocache.overall_mshr_misses::total 41730 # number of overall MSHR misses 128311680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13512883 # number of ReadReq MSHR miss cycles 128411680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 13512883 # number of ReadReq MSHR miss cycles 128511754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2875898127 # number of WriteLineReq MSHR miss cycles 128611754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 2875898127 # number of WriteLineReq MSHR miss cycles 128711754Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::tsunami.ide 2889411010 # number of demand (read+write) MSHR miss cycles 128811754Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 2889411010 # number of demand (read+write) MSHR miss cycles 128911754Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::tsunami.ide 2889411010 # number of overall MSHR miss cycles 129011754Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 2889411010 # number of overall MSHR miss cycles 129110585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 129210585Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 129310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses 129410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 129510585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 129610585Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 129710585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 129810585Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 129911680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 75915.073034 # average ReadReq mshr miss latency 130011680SCurtis.Dunham@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 75915.073034 # average ReadReq mshr miss latency 130111754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 69212.026545 # average WriteLineReq mshr miss latency 130211754Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 69212.026545 # average WriteLineReq mshr miss latency 130311754Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69240.618500 # average overall mshr miss latency 130411754Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 69240.618500 # average overall mshr miss latency 130511754Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69240.618500 # average overall mshr miss latency 130611754Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 69240.618500 # average overall mshr miss latency 130711754Sandreas.hansson@arm.comsystem.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 130811754Sandreas.hansson@arm.comsystem.l2c.tags.replacements 342924 # number of replacements 130911754Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 65389.954347 # Cycle average of tags in use 131011754Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 3989934 # Total number of references to valid blocks. 131111754Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 408445 # Sample count of references to valid blocks. 131211754Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 9.768596 # Average number of references to valid blocks. 131311754Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 7750508000 # Cycle when the warmup percentage was hit. 131411754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 285.827021 # Average occupied blocks per requestor 131511754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 4794.067634 # Average occupied blocks per requestor 131611754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 59305.224879 # Average occupied blocks per requestor 131711754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 165.844219 # Average occupied blocks per requestor 131811754Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 838.990595 # Average occupied blocks per requestor 131911680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::writebacks 0.004361 # Average percentage of cache occupancy 132011754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.073152 # Average percentage of cache occupancy 132111754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.904926 # Average percentage of cache occupancy 132211754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.002531 # Average percentage of cache occupancy 132311754Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.012802 # Average percentage of cache occupancy 132411680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::total 0.997772 # Average percentage of cache occupancy 132511680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 65521 # Occupied blocks per task id 132611680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id 132711680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 697 # Occupied blocks per task id 132811680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1597 # Occupied blocks per task id 132911680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 6182 # Occupied blocks per task id 133011680SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 57022 # Occupied blocks per task id 133111680SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.999771 # Percentage of cache occupancy per task id 133211754Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 35598107 # Number of tag accesses 133311754Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 35598107 # Number of data accesses 133411754Sandreas.hansson@arm.comsystem.l2c.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 133511754Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::writebacks 792905 # number of WritebackDirty hits 133611754Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::total 792905 # number of WritebackDirty hits 133711754Sandreas.hansson@arm.comsystem.l2c.WritebackClean_hits::writebacks 747283 # number of WritebackClean hits 133811754Sandreas.hansson@arm.comsystem.l2c.WritebackClean_hits::total 747283 # number of WritebackClean hits 133911754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 3151 # number of UpgradeReq hits 134011754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 2387 # number of UpgradeReq hits 134111754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 5538 # number of UpgradeReq hits 134211754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 946 # number of SCUpgradeReq hits 134311754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 957 # number of SCUpgradeReq hits 134411754Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 1903 # number of SCUpgradeReq hits 134511754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 128511 # number of ReadExReq hits 134611754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 43286 # number of ReadExReq hits 134711754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 171797 # number of ReadExReq hits 134811754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_hits::cpu0.inst 680335 # number of ReadCleanReq hits 134911754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_hits::cpu1.inst 326126 # number of ReadCleanReq hits 135011754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_hits::total 1006461 # number of ReadCleanReq hits 135111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 663262 # number of ReadSharedReq hits 135211754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 108452 # number of ReadSharedReq hits 135311754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::total 771714 # number of ReadSharedReq hits 135411754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 680335 # number of demand (read+write) hits 135511754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 791773 # number of demand (read+write) hits 135611754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 326126 # number of demand (read+write) hits 135711754Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 151738 # number of demand (read+write) hits 135811754Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 1949972 # number of demand (read+write) hits 135911754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 680335 # number of overall hits 136011754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 791773 # number of overall hits 136111754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 326126 # number of overall hits 136211754Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 151738 # number of overall hits 136311754Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 1949972 # number of overall hits 136411606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 5 # number of UpgradeReq misses 136511606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 1 # number of UpgradeReq misses 136611606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_misses::total 6 # number of UpgradeReq misses 136711754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 116816 # number of ReadExReq misses 136811680SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 6419 # number of ReadExReq misses 136911754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 123235 # number of ReadExReq misses 137011754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_misses::cpu0.inst 12450 # number of ReadCleanReq misses 137111754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_misses::cpu1.inst 984 # number of ReadCleanReq misses 137211754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_misses::total 13434 # number of ReadCleanReq misses 137311680SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 271517 # number of ReadSharedReq misses 137411754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 339 # number of ReadSharedReq misses 137511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::total 271856 # number of ReadSharedReq misses 137611754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 12450 # number of demand (read+write) misses 137711754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 388333 # number of demand (read+write) misses 137811754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 984 # number of demand (read+write) misses 137911754Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 6758 # number of demand (read+write) misses 138011754Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 408525 # number of demand (read+write) misses 138111754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 12450 # number of overall misses 138211754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 388333 # number of overall misses 138311754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 984 # number of overall misses 138411754Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 6758 # number of overall misses 138511754Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 408525 # number of overall misses 138611606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 300000 # number of UpgradeReq miss cycles 138711680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 28500 # number of UpgradeReq miss cycles 138811680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_latency::total 328500 # number of UpgradeReq miss cycles 138911754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 10623244500 # number of ReadExReq miss cycles 139011754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 659466000 # number of ReadExReq miss cycles 139111754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::total 11282710500 # number of ReadExReq miss cycles 139211754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_miss_latency::cpu0.inst 1281529500 # number of ReadCleanReq miss cycles 139311754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_miss_latency::cpu1.inst 100368000 # number of ReadCleanReq miss cycles 139411754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_miss_latency::total 1381897500 # number of ReadCleanReq miss cycles 139511754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 21945590000 # number of ReadSharedReq miss cycles 139611754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 41766500 # number of ReadSharedReq miss cycles 139711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::total 21987356500 # number of ReadSharedReq miss cycles 139811754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 1281529500 # number of demand (read+write) miss cycles 139911754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.data 32568834500 # number of demand (read+write) miss cycles 140011754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 100368000 # number of demand (read+write) miss cycles 140111754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.data 701232500 # number of demand (read+write) miss cycles 140211754Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::total 34651964500 # number of demand (read+write) miss cycles 140311754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 1281529500 # number of overall miss cycles 140411754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.data 32568834500 # number of overall miss cycles 140511754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 100368000 # number of overall miss cycles 140611754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.data 701232500 # number of overall miss cycles 140711754Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::total 34651964500 # number of overall miss cycles 140811754Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 792905 # number of WritebackDirty accesses(hits+misses) 140911754Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::total 792905 # number of WritebackDirty accesses(hits+misses) 141011754Sandreas.hansson@arm.comsystem.l2c.WritebackClean_accesses::writebacks 747283 # number of WritebackClean accesses(hits+misses) 141111754Sandreas.hansson@arm.comsystem.l2c.WritebackClean_accesses::total 747283 # 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number of ReadReq MSHR uncacheable cycles 155111680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 24728000 # number of ReadReq MSHR uncacheable cycles 155211680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::total 1508409000 # number of ReadReq MSHR uncacheable cycles 155311680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.data 1483681000 # number of overall MSHR uncacheable cycles 155411680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.data 24728000 # number of overall MSHR uncacheable cycles 155511680SCurtis.Dunham@arm.comsystem.l2c.overall_mshr_uncacheable_latency::total 1508409000 # number of overall MSHR uncacheable cycles 155610892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 155710892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 155811754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.001584 # mshr miss rate for UpgradeReq accesses 155911754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.000419 # mshr miss rate for UpgradeReq accesses 156011754Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.001082 # mshr miss rate for UpgradeReq accesses 156111754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.476164 # mshr miss rate for ReadExReq accesses 156211754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.129142 # mshr miss rate for ReadExReq accesses 156311754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.417700 # mshr miss rate for ReadExReq accesses 156411754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.017971 # mshr miss rate for ReadCleanReq accesses 156511754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.002975 # mshr miss rate for ReadCleanReq accesses 156611754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_mshr_miss_rate::total 0.013161 # mshr miss rate for ReadCleanReq accesses 156711754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.290461 # mshr miss rate for ReadSharedReq accesses 156811754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.003116 # mshr miss rate for ReadSharedReq accesses 156911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::total 0.260506 # mshr miss rate for ReadSharedReq accesses 157011754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.017971 # mshr miss rate for demand accesses 157111754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.329066 # mshr miss rate for demand accesses 157211754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.002975 # mshr miss rate for demand accesses 157311754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.042638 # mshr miss rate for demand accesses 157411754Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.173209 # mshr miss rate for demand accesses 157511754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.017971 # mshr miss rate for overall accesses 157611754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.329066 # mshr miss rate for overall accesses 157711754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.002975 # mshr miss rate for overall accesses 157811754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.042638 # mshr miss rate for overall accesses 157911754Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.173209 # mshr miss rate for overall accesses 158011606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 50000 # average UpgradeReq mshr miss latency 158111680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average UpgradeReq mshr miss latency 158211680SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 44750 # average UpgradeReq mshr miss latency 158311754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80939.978256 # average ReadExReq mshr miss latency 158411754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92736.563328 # average ReadExReq mshr miss latency 158511754Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 81554.432588 # average ReadExReq mshr miss latency 158611754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 92934.096386 # average ReadCleanReq mshr miss latency 158711754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 92258.992806 # average ReadCleanReq mshr miss latency 158811754Sandreas.hansson@arm.comsystem.l2c.ReadCleanReq_avg_mshr_miss_latency::total 92885.159800 # average ReadCleanReq mshr miss latency 158911754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 70825.841476 # average ReadSharedReq mshr miss latency 159011754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 113205.014749 # average ReadSharedReq mshr miss latency 159111754Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 70878.687614 # average ReadSharedReq mshr miss latency 159211754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 92934.096386 # average overall mshr miss latency 159311754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 73868.315338 # average overall mshr miss latency 159411754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 92258.992806 # average overall mshr miss latency 159511754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 93763.317550 # average overall mshr miss latency 159611754Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 74822.293728 # average overall mshr miss latency 159711754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 92934.096386 # average overall mshr miss latency 159811754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 73868.315338 # average overall mshr miss latency 159911754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 92258.992806 # average overall mshr miss latency 160011754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 93763.317550 # average overall mshr miss latency 160111754Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 74822.293728 # average overall mshr miss latency 160211680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209766.859890 # average ReadReq mshr uncacheable latency 160311680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 197824 # average ReadReq mshr uncacheable latency 160411680SCurtis.Dunham@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209559.460961 # average ReadReq mshr uncacheable latency 160511680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83235.960729 # average overall mshr uncacheable latency 160611680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 7073.226545 # average overall mshr uncacheable latency 160711680SCurtis.Dunham@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total 70747.572816 # average overall mshr uncacheable latency 160811754Sandreas.hansson@arm.comsystem.membus.snoop_filter.tot_requests 856478 # Total number of requests made to the snoop filter. 160911754Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_single_requests 407046 # Number of requests hitting in the snoop filter with a single holder of the requested data. 161011754Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_multi_requests 512 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 161111502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 161211502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 161311502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 161411754Sandreas.hansson@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 161511680SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadReq 7198 # Transaction distribution 161611754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 292655 # Transaction distribution 161711680SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteReq 14123 # Transaction distribution 161811680SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteResp 14123 # Transaction distribution 161911754Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 121475 # Transaction distribution 162011754Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 262336 # Transaction distribution 162111754Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 11690 # Transaction distribution 162211754Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 9942 # Transaction distribution 162311336Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 3 # Transaction distribution 162411754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 123955 # Transaction distribution 162511754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 123087 # Transaction distribution 162611754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 285457 # Transaction distribution 162710892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 41552 # Transaction distribution 162811754Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 148 # Transaction distribution 162911680SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42642 # Packet count per connected master and slave (bytes) 163011754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1181082 # Packet count per connected master and slave (bytes) 163111754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 1223724 # Packet count per connected master and slave (bytes) 163211680SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83443 # Packet count per connected master and slave (bytes) 163311680SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 83443 # Packet count per connected master and slave (bytes) 163411754Sandreas.hansson@arm.comsystem.membus.pkt_count::total 1307167 # Packet count per connected master and slave (bytes) 163511680SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82394 # Cumulative packet size per connected master and slave (bytes) 163611754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31235712 # Cumulative packet size per connected master and slave (bytes) 163711754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 31318106 # Cumulative packet size per connected master and slave (bytes) 163811245Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes) 163911245Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes) 164011754Sandreas.hansson@arm.comsystem.membus.pkt_size::total 33976346 # Cumulative packet size per connected master and slave (bytes) 164111754Sandreas.hansson@arm.comsystem.membus.snoops 22923 # Total snoops (count) 164211680SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 27264 # Total snoop traffic (bytes) 164311754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 493917 # Request fanout histogram 164411754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0.001373 # Request fanout histogram 164511754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0.037025 # Request fanout histogram 164610585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 164711754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 493239 99.86% 99.86% # Request fanout histogram 164811754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 678 0.14% 100.00% # Request fanout histogram 164910585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 165010585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 165111502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 165210585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 165311754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 493917 # Request fanout histogram 165411754Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 40493500 # Layer occupancy (ticks) 165510585Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 165611754Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 1322925099 # Layer occupancy (ticks) 165710585Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 165811754Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 2182236750 # Layer occupancy (ticks) 165910726Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 0.1 # Layer utilization (%) 166011754Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 1074598 # Layer occupancy (ticks) 166110585Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 166211754Sandreas.hansson@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 166311754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_requests 4789722 # Total number of requests made to the snoop filter. 166411754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 2388089 # Number of requests hitting in the snoop filter with a single holder of the requested data. 166511754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 374620 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 166611754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 991 # Total number of snoops made to the snoop filter. 166711754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 930 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 166811680SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 61 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 166911754Sandreas.hansson@arm.comsystem.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 167011680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadReq 7198 # Transaction distribution 167111754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 2107102 # Transaction distribution 167211680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WriteReq 14123 # Transaction distribution 167311680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WriteResp 14123 # Transaction distribution 167411754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 872860 # Transaction distribution 167511754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WritebackClean 1018728 # Transaction distribution 167611754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::CleanEvict 815346 # Transaction distribution 167711754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 17080 # Transaction distribution 167811754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 11845 # Transaction distribution 167911754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 28925 # Transaction distribution 168011754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 297046 # Transaction distribution 168111754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 297046 # Transaction distribution 168211754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadCleanReq 1019917 # Transaction distribution 168311754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 1079990 # Transaction distribution 168411680SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 246 # Transaction distribution 168511754Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::InvalidateResp 4 # Transaction distribution 168611754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2077759 # Packet count per connected master and slave (bytes) 168711754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3616208 # Packet count per connected master and slave (bytes) 168811754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 980781 # Packet count per connected master and slave (bytes) 168911754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 523727 # Packet count per connected master and slave (bytes) 169011754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 7198475 # Packet count per connected master and slave (bytes) 169111754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 88636992 # Cumulative packet size per connected master and slave (bytes) 169211754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119193988 # Cumulative packet size per connected master and slave (bytes) 169311754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41834880 # Cumulative packet size per connected master and slave (bytes) 169411754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17315286 # Cumulative packet size per connected master and slave (bytes) 169511754Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 266981146 # Cumulative packet size per connected master and slave (bytes) 169611754Sandreas.hansson@arm.comsystem.toL2Bus.snoops 403271 # Total snoops (count) 169711754Sandreas.hansson@arm.comsystem.toL2Bus.snoopTraffic 7578112 # Total snoop traffic (bytes) 169811754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 2790369 # Request fanout histogram 169911754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 0.143087 # Request fanout histogram 170011754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.350419 # Request fanout histogram 170110585Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 170211754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 2391353 85.70% 85.70% # Request fanout histogram 170311754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 398767 14.29% 99.99% # Request fanout histogram 170411754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 248 0.01% 100.00% # Request fanout histogram 170511606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram 170611138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 170710585Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 170811138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 170911138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram 171011754Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 2790369 # Request fanout histogram 171111754Sandreas.hansson@arm.comsystem.toL2Bus.reqLayer0.occupancy 4224217497 # Layer occupancy (ticks) 171210892Sandreas.hansson@arm.comsystem.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 171311754Sandreas.hansson@arm.comsystem.toL2Bus.snoopLayer0.occupancy 304383 # Layer occupancy (ticks) 171410585Sandreas.hansson@arm.comsystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 171511754Sandreas.hansson@arm.comsystem.toL2Bus.respLayer0.occupancy 1039374668 # Layer occupancy (ticks) 171611245Sandreas.sandberg@arm.comsystem.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 171711754Sandreas.hansson@arm.comsystem.toL2Bus.respLayer1.occupancy 1817986111 # Layer occupancy (ticks) 171810726Sandreas.hansson@arm.comsystem.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 171911754Sandreas.hansson@arm.comsystem.toL2Bus.respLayer2.occupancy 491891046 # Layer occupancy (ticks) 172010726Sandreas.hansson@arm.comsystem.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 172111754Sandreas.hansson@arm.comsystem.toL2Bus.respLayer3.occupancy 276353266 # Layer occupancy (ticks) 172210585Sandreas.hansson@arm.comsystem.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 172311754Sandreas.hansson@arm.comsystem.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 172411754Sandreas.hansson@arm.comsystem.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 172511754Sandreas.hansson@arm.comsystem.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 172611754Sandreas.hansson@arm.comsystem.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 17278721SN/Asystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 17288721SN/Asystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 17298721SN/Asystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 17308721SN/Asystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 17318721SN/Asystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 17328983Snate@binkert.orgsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 17338721SN/Asystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 17348721SN/Asystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 17358983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 17368721SN/Asystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 17378721SN/Asystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 17388983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 17398721SN/Asystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 17408721SN/Asystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 17418983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 17428721SN/Asystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 17438721SN/Asystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 17448983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 17458721SN/Asystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 17468721SN/Asystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 17478983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 17488721SN/Asystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 17498721SN/Asystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 17508983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 17518721SN/Asystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 17528721SN/Asystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 17538983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 17548721SN/Asystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 17558983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 17568721SN/Asystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 17578721SN/Asystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 175811754Sandreas.hansson@arm.comsystem.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 175911754Sandreas.hansson@arm.comsystem.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 176011754Sandreas.hansson@arm.comsystem.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 176111754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 176211754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 176311754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 176411754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 176511754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 176611754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 176711754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 176811754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 176911754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 177011754Sandreas.hansson@arm.comsystem.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 177111754Sandreas.hansson@arm.comsystem.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 177211754Sandreas.hansson@arm.comsystem.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 177311754Sandreas.hansson@arm.comsystem.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 177411754Sandreas.hansson@arm.comsystem.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 177511754Sandreas.hansson@arm.comsystem.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 177611754Sandreas.hansson@arm.comsystem.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 177711754Sandreas.hansson@arm.comsystem.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 177811754Sandreas.hansson@arm.comsystem.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 177911754Sandreas.hansson@arm.comsystem.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 178011754Sandreas.hansson@arm.comsystem.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1966742176000 # Cumulative time (in ticks) in various power states 17812968SN/A 17822968SN/A---------- End Simulation Statistics ---------- 1783