Searched hist:2010 (Results 451 - 475 of 929) sorted by relevance

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/gem5/src/mem/ruby/system/
H A DSequencer.ccdiff 7805:f249937228b5 Thu Dec 23 00:15:00 EST 2010 Nilay Vaish<nilay@cs.wisc.edu> This patch removes the WARN_* and ERROR_* from src/mem/ruby/common/Debug.hh file. These statements have been replaced with warn(), panic() and fatal() defined in src/base/misc.hh
diff 7632:acf43d6bbc18 Tue Aug 24 03:07:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> testers: move testers to a new directory

This patch moves the testers to a new subdirectory under src/cpu and includes
the necessary fixes to work with latest m5 initialization patches.
diff 7565:9fc3475e8175 Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> MOESI_hammer: break down miss latency stalled cycles

This patch tracks the number of cycles a transaction is delayed at different
points of the request-forward-response loop.
diff 7560:29d5891a96d6 Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Added SC fail indication to trace profiling
diff 7550:7d97cec15818 Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: fix ruby llsc support to sync sc outcomes

Added support so that ruby can determine the outcome of store conditional
operations and reflect that outcome to M5 physical memory and cpus.
diff 7546:84e8f914b3b8 Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Reincarnated the responding machine profiling

This patch adds back to ruby the capability to understand the response time
for messages that hit in different levels of the cache heirarchy.
Specifically add support for the MI_example, MOESI_hammer, and MOESI_CMP_token
protocols.
diff 7537:8178df9c17c4 Fri Aug 20 14:41:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Fixed printout when Sequencer detects a deadlock
diff 7455:586f99bf0dc4 Fri Jun 11 02:17:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get rid of the Map class
diff 7454:3a3e8e8cce1b Fri Jun 11 02:17:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get rid of Vector and use STL
add a couple of helper functions to base for deleteing all pointers in
a container and outputting containers to a stream
diff 7453:1a5db3dd0f62 Fri Jun 11 02:17:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get rid of RefCnt and Allocator stuff use base/refcnt.hh

This was somewhat tricky because the RefCnt API was somewhat odd. The
biggest confusion was that the the RefCnt object's constructor that
took a TYPE& cloned the object. I created an explicit virtual clone()
function for things that took advantage of this version of the
constructor. I was conservative and used clone() when I was in doubt
of whether or not it was necessary. I still think that there are
probably too many instances of clone(), but hopefully not too many.

I converted several instances of const MsgPtr & to a simple MsgPtr.
If the function wants to avoid the overhead of creating another
reference, then it should just use a regular pointer instead of a ref
counting ptr.

There were a couple of instances where refcounted objects were created
on the stack. This seems pretty dangerous since if you ever
accidentally make a reference to that object with a ref counting
pointer, bad things are bound to happen.
/gem5/src/arch/arm/
H A Dfaults.ccdiff 7720:65d338a8dba4 Sun Oct 31 03:07:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.



This change is a low level and pervasive reorganization of how PCs are managed
in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about,
the PC and the NPC, and the lsb of the PC signaled whether or not you were in
PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next
micropc, x86 and ARM introduced variable length instruction sets, and ARM
started to keep track of mode bits in the PC. Each CPU model handled PCs in
its own custom way that needed to be updated individually to handle the new
dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack,
the complexity could be hidden in the ISA at the ISA implementation's expense.
Areas like the branch predictor hadn't been updated to handle branch delay
slots or micropcs, and it turns out that had introduced a significant (10s of
percent) performance bug in SPARC and to a lesser extend MIPS. Rather than
perpetuate the problem by reworking O3 again to handle the PC features needed
by x86, this change was introduced to rework PC handling in a more modular,
transparent, and hopefully efficient way.


PC type:

Rather than having the superset of all possible elements of PC state declared
in each of the CPU models, each ISA defines its own PCState type which has
exactly the elements it needs. A cross product of canned PCState classes are
defined in the new "generic" ISA directory for ISAs with/without delay slots
and microcode. These are either typedef-ed or subclassed by each ISA. To read
or write this structure through a *Context, you use the new pcState() accessor
which reads or writes depending on whether it has an argument. If you just
want the address of the current or next instruction or the current micro PC,
you can get those through read-only accessors on either the PCState type or
the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the
move away from readPC. That name is ambiguous since it's not clear whether or
not it should be the actual address to fetch from, or if it should have extra
bits in it like the PAL mode bit. Each class is free to define its own
functions to get at whatever values it needs however it needs to to be used in
ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the
PC and into a separate field like ARM.

These types can be reset to a particular pc (where npc = pc +
sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as
appropriate), printed, serialized, and compared. There is a branching()
function which encapsulates code in the CPU models that checked if an
instruction branched or not. Exactly what that means in the context of branch
delay slots which can skip an instruction when not taken is ambiguous, and
ideally this function and its uses can be eliminated. PCStates also generally
know how to advance themselves in various ways depending on if they point at
an instruction, a microop, or the last microop of a macroop. More on that
later.

Ideally, accessing all the PCs at once when setting them will improve
performance of M5 even though more data needs to be moved around. This is
because often all the PCs need to be manipulated together, and by getting them
all at once you avoid multiple function calls. Also, the PCs of a particular
thread will have spatial locality in the cache. Previously they were grouped
by element in arrays which spread out accesses.


Advancing the PC:

The PCs were previously managed entirely by the CPU which had to know about PC
semantics, try to figure out which dimension to increment the PC in, what to
set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction
with the PC type itself. Because most of the information about how to
increment the PC (mainly what type of instruction it refers to) is contained
in the instruction object, a new advancePC virtual function was added to the
StaticInst class. Subclasses provide an implementation that moves around the
right element of the PC with a minimal amount of decision making. In ISAs like
Alpha, the instructions always simply assign NPC to PC without having to worry
about micropcs, nnpcs, etc. The added cost of a virtual function call should
be outweighed by not having to figure out as much about what to do with the
PCs and mucking around with the extra elements.

One drawback of making the StaticInsts advance the PC is that you have to
actually have one to advance the PC. This would, superficially, seem to
require decoding an instruction before fetch could advance. This is, as far as
I can tell, realistic. fetch would advance through memory addresses, not PCs,
perhaps predicting new memory addresses using existing ones. More
sophisticated decisions about control flow would be made later on, after the
instruction was decoded, and handed back to fetch. If branching needs to
happen, some amount of decoding needs to happen to see that it's a branch,
what the target is, etc. This could get a little more complicated if that gets
done by the predecoder, but I'm choosing to ignore that for now.


Variable length instructions:

To handle variable length instructions in x86 and ARM, the predecoder now
takes in the current PC by reference to the getExtMachInst function. It can
modify the PC however it needs to (by setting NPC to be the PC + instruction
length, for instance). This could be improved since the CPU doesn't know if
the PC was modified and always has to write it back.


ISA parser:

To support the new API, all PC related operand types were removed from the
parser and replaced with a PCState type. There are two warts on this
implementation. First, as with all the other operand types, the PCState still
has to have a valid operand type even though it doesn't use it. Second, using
syntax like PCS.npc(target) doesn't work for two reasons, this looks like the
syntax for operand type overriding, and the parser can't figure out if you're
reading or writing. Instructions that use the PCS operand (which I've
consistently called it) need to first read it into a local variable,
manipulate it, and then write it back out.


Return address stack:

The return address stack needed a little extra help because, in the presence
of branch delay slots, it has to merge together elements of the return PC and
the call PC. To handle that, a buildRetPC utility function was added. There
are basically only two versions in all the ISAs, but it didn't seem short
enough to put into the generic ISA directory. Also, the branch predictor code
in O3 and InOrder were adjusted so that they always store the PC of the actual
call instruction in the RAS, not the next PC. If the call instruction is a
microop, the next PC refers to the next microop in the same macroop which is
probably not desirable. The buildRetPC function advances the PC intelligently
to the next macroop (in an ISA specific way) so that that case works.


Change in stats:

There were no change in stats except in MIPS and SPARC in the O3 model. MIPS
runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could
likely be improved further by setting call/return instruction flags and taking
advantage of the RAS.


TODO:

Add != operators to the PCState classes, defined trivially to be !(a==b).
Smooth out places where PCs are split apart, passed around, and put back
together later. I think this might happen in SPARC's fault code. Add ISA
specific constructors that allow setting PC elements without calling a bunch
of accessors. Try to eliminate the need for the branching() function. Factor
out Alpha's PAL mode pc bit into a separate flag field, and eliminate places
where it's blindly masked out or tested in the PC.
diff 7692:8173327c9c65 Fri Oct 01 17:02:00 EDT 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Clean up use of TBit and JBit.

Rather tha constantly using ULL(1) << PcXBitShift define those directly.
Additionally, add some helper functions to further clean up the code.
diff 7678:f19b6a3a8cec Mon Sep 13 22:26:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.

Also move the "Fault" reference counted pointer type into a separate file,
sim/fault.hh. It would be better to name this less similarly to sim/faults.hh
to reduce confusion, but fault.hh matches the name of the type. We could change
Fault to FaultPtr to match other pointer types, and then changing the name of
the file would make more sense.
diff 7652:f2621206b062 Wed Aug 25 20:10:00 EDT 2010 Min Kyu Jeong <minkyu.jeong@arm.com> ARM: Adding a bogus fault that does nothing.
This fault can used to flush the pipe, not including the faulting instruction.

The particular case I needed this was for a self-modifying code. It needed to
drain the store queue and force the following instruction to refetch from
icache. DCCMVAC cp15 mcr instruction is modified to raise this fault.
diff 7640:5286a8a469c5 Wed Aug 25 20:10:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement CPACR register and return Undefined Instruction when FP access is disabled.
diff 7585:afbc40280b56 Mon Aug 23 12:18:00 EDT 2010 Ali Saidi <Ali.Saidi@arm.com> ARM: Add system for ARM/Linux and bootstrapping
diff 7426:5da64155a605 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Get rid of the binary dumping function in utility.hh.
diff 7412:b62d0343ad8f Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Make sure the upc is zeroed when vectoring to a fault.
diff 7400:f6c9b27c4dbe Wed Jun 02 01:58:00 EDT 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Implement ARM CPU interrupts
diff 7362:9ea92e0eb4a9 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement and update the DFSR and IFSR registers on faults.
H A Dvtophys.ccdiff 7694:de057cccee82 Fri Oct 01 17:03:00 EDT 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Implement functional virtual to physical address translation
for debugging and program introspection.
diff 7651:84a44eb3ccb8 Wed Aug 25 20:10:00 EDT 2010 William Wang <William.Wang@ARM.com> ARM: Remove ALPHA KSeg functions.

These were erronously copied years ago into the ARM directory.
/gem5/src/cpu/pred/
H A Dras.hhdiff 9480:d059f8a95a42 Thu Jan 24 01:28:00 EST 2013 Nilay Vaish <nilay@cs.wisc.edu>, Timothy Jones <timothy.jones@cl.cam.ac.uk> branch predictor: move out of o3 and inorder cpus
This patch moves the branch predictor files in the o3 and inorder directories
to src/cpu/pred. This allows sharing the branch predictor across different
cpu models.

This patch was originally posted by Timothy Jones in July 2010
but never made it to the repository.
diff 7720:65d338a8dba4 Sun Oct 31 03:07:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.



This change is a low level and pervasive reorganization of how PCs are managed
in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about,
the PC and the NPC, and the lsb of the PC signaled whether or not you were in
PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next
micropc, x86 and ARM introduced variable length instruction sets, and ARM
started to keep track of mode bits in the PC. Each CPU model handled PCs in
its own custom way that needed to be updated individually to handle the new
dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack,
the complexity could be hidden in the ISA at the ISA implementation's expense.
Areas like the branch predictor hadn't been updated to handle branch delay
slots or micropcs, and it turns out that had introduced a significant (10s of
percent) performance bug in SPARC and to a lesser extend MIPS. Rather than
perpetuate the problem by reworking O3 again to handle the PC features needed
by x86, this change was introduced to rework PC handling in a more modular,
transparent, and hopefully efficient way.


PC type:

Rather than having the superset of all possible elements of PC state declared
in each of the CPU models, each ISA defines its own PCState type which has
exactly the elements it needs. A cross product of canned PCState classes are
defined in the new "generic" ISA directory for ISAs with/without delay slots
and microcode. These are either typedef-ed or subclassed by each ISA. To read
or write this structure through a *Context, you use the new pcState() accessor
which reads or writes depending on whether it has an argument. If you just
want the address of the current or next instruction or the current micro PC,
you can get those through read-only accessors on either the PCState type or
the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the
move away from readPC. That name is ambiguous since it's not clear whether or
not it should be the actual address to fetch from, or if it should have extra
bits in it like the PAL mode bit. Each class is free to define its own
functions to get at whatever values it needs however it needs to to be used in
ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the
PC and into a separate field like ARM.

These types can be reset to a particular pc (where npc = pc +
sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as
appropriate), printed, serialized, and compared. There is a branching()
function which encapsulates code in the CPU models that checked if an
instruction branched or not. Exactly what that means in the context of branch
delay slots which can skip an instruction when not taken is ambiguous, and
ideally this function and its uses can be eliminated. PCStates also generally
know how to advance themselves in various ways depending on if they point at
an instruction, a microop, or the last microop of a macroop. More on that
later.

Ideally, accessing all the PCs at once when setting them will improve
performance of M5 even though more data needs to be moved around. This is
because often all the PCs need to be manipulated together, and by getting them
all at once you avoid multiple function calls. Also, the PCs of a particular
thread will have spatial locality in the cache. Previously they were grouped
by element in arrays which spread out accesses.


Advancing the PC:

The PCs were previously managed entirely by the CPU which had to know about PC
semantics, try to figure out which dimension to increment the PC in, what to
set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction
with the PC type itself. Because most of the information about how to
increment the PC (mainly what type of instruction it refers to) is contained
in the instruction object, a new advancePC virtual function was added to the
StaticInst class. Subclasses provide an implementation that moves around the
right element of the PC with a minimal amount of decision making. In ISAs like
Alpha, the instructions always simply assign NPC to PC without having to worry
about micropcs, nnpcs, etc. The added cost of a virtual function call should
be outweighed by not having to figure out as much about what to do with the
PCs and mucking around with the extra elements.

One drawback of making the StaticInsts advance the PC is that you have to
actually have one to advance the PC. This would, superficially, seem to
require decoding an instruction before fetch could advance. This is, as far as
I can tell, realistic. fetch would advance through memory addresses, not PCs,
perhaps predicting new memory addresses using existing ones. More
sophisticated decisions about control flow would be made later on, after the
instruction was decoded, and handed back to fetch. If branching needs to
happen, some amount of decoding needs to happen to see that it's a branch,
what the target is, etc. This could get a little more complicated if that gets
done by the predecoder, but I'm choosing to ignore that for now.


Variable length instructions:

To handle variable length instructions in x86 and ARM, the predecoder now
takes in the current PC by reference to the getExtMachInst function. It can
modify the PC however it needs to (by setting NPC to be the PC + instruction
length, for instance). This could be improved since the CPU doesn't know if
the PC was modified and always has to write it back.


ISA parser:

To support the new API, all PC related operand types were removed from the
parser and replaced with a PCState type. There are two warts on this
implementation. First, as with all the other operand types, the PCState still
has to have a valid operand type even though it doesn't use it. Second, using
syntax like PCS.npc(target) doesn't work for two reasons, this looks like the
syntax for operand type overriding, and the parser can't figure out if you're
reading or writing. Instructions that use the PCS operand (which I've
consistently called it) need to first read it into a local variable,
manipulate it, and then write it back out.


Return address stack:

The return address stack needed a little extra help because, in the presence
of branch delay slots, it has to merge together elements of the return PC and
the call PC. To handle that, a buildRetPC utility function was added. There
are basically only two versions in all the ISAs, but it didn't seem short
enough to put into the generic ISA directory. Also, the branch predictor code
in O3 and InOrder were adjusted so that they always store the PC of the actual
call instruction in the RAS, not the next PC. If the call instruction is a
microop, the next PC refers to the next microop in the same macroop which is
probably not desirable. The buildRetPC function advances the PC intelligently
to the next macroop (in an ISA specific way) so that that case works.


Change in stats:

There were no change in stats except in MIPS and SPARC in the O3 model. MIPS
runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could
likely be improved further by setting call/return instruction flags and taking
advantage of the RAS.


TODO:

Add != operators to the PCState classes, defined trivially to be !(a==b).
Smooth out places where PCs are split apart, passed around, and put back
together later. I think this might happen in SPARC's fault code. Add ISA
specific constructors that allow setting PC elements without calling a bunch
of accessors. Try to eliminate the need for the branching() function. Factor
out Alpha's PAL mode pc bit into a separate flag field, and eliminate places
where it's blindly masked out or tested in the PC.
/gem5/src/dev/
H A Dintel_8254_timer.hhdiff 7683:f81f5f27592b Thu Sep 16 23:24:00 EDT 2010 Steve Reinhardt <steve.reinhardt@amd.com> devices: undo cset 017baf09599f that added timer drain functions.
It's not the right fix for the checkpoint deadlock problem
Brad was having, and creates another bug where the system can
deadlock on restore. Brad can't reproduce the original bug
right now, so we'll wait until it arises again and then try
to fix it the right way then.
diff 7559:017baf09599f Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> devices: Fixed periodic interrupts to work with draining

Added drain functions to the RTC and 8254 timer so that periodic interrupts
stop when the system is draining. This patch is needed to checkpoint in
timing mode. Otherwise under certain situations, the event queue will never
be completely empty.
/gem5/src/mem/ruby/common/
H A DAddress.ccdiff 7055:4e24742201d7 Fri Apr 02 14:20:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get "using namespace" out of headers
In addition to obvious changes, this required a slight change to the slicc
grammar to allow types with :: in them. Otherwise slicc barfs on std::string
which we need for the headers that slicc generates.
diff 7039:bc0b6ea676b5 Mon Mar 22 21:43:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: style pass
H A DSet.hhdiff 7089:9ea24d102d66 Tue Jun 01 14:38:00 EDT 2010 Nathan Binkert <nate@binkert.org> style: clean up ruby's Set class

Further cleanup should probably be done to make this class be non-Ruby
specific and put it in src/base.

There are probably several cases where this class is used, std::bitset
could be used instead.
diff 7055:4e24742201d7 Fri Apr 02 14:20:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get "using namespace" out of headers
In addition to obvious changes, this required a slight change to the slicc
grammar to allow types with :: in them. Otherwise slicc barfs on std::string
which we need for the headers that slicc generates.
H A DSConscriptdiff 7039:bc0b6ea676b5 Mon Mar 22 21:43:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: style pass
diff 6876:a658c315512c Fri Jan 29 23:29:00 EST 2010 Steve Reinhardt <steve.reinhardt@amd.com> ruby: Convert most Ruby objects to M5 SimObjects.
The necessary companion conversion of Ruby objects generated by SLICC
are converted to M5 SimObjects in the following patch, so this patch
alone does not compile.
Conversion of Garnet network models is also handled in a separate
patch; that code is temporarily disabled from compiling to allow
testing of interim code.
/gem5/src/mem/slicc/ast/
H A DMethodCallExprAST.pydiff 6999:f226c098c393 Wed Mar 10 19:22:00 EST 2010 Nathan Binkert <nate@binkert.org> slicc: have a central mechanism for creating a code_formatter.
This makes it easier to add global variables like protocol
diff 6882:898047a3672c Fri Jan 29 23:29:00 EST 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Ruby changes required to use the python config system
This patch includes the necessary changes to connect ruby objects using
the python configuration system. Mainly it consists of removing
unnecessary ruby object pointers and connecting the necessary object
pointers using the generated param objects. This patch includes the
slicc changes necessary to connect generated ruby objects together using
the python configuraiton system.
H A DInPortDeclAST.pydiff 7567:238f99c9f441 Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Stall and wait input messages instead of recycling

This patch allows messages to be stalled in their input buffers and wait
until a corresponding address changes state. In order to make this work,
all in_ports must be ranked in order of dependence and those in_ports that
may unblock an address, must wake up the stalled messages. Alot of this
complexity is handled in slicc and the specification files simply
annotate the in_ports.
diff 6999:f226c098c393 Wed Mar 10 19:22:00 EST 2010 Nathan Binkert <nate@binkert.org> slicc: have a central mechanism for creating a code_formatter.
This makes it easier to add global variables like protocol
H A DFormalParamAST.pydiff 6882:898047a3672c Fri Jan 29 23:29:00 EST 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Ruby changes required to use the python config system
This patch includes the necessary changes to connect ruby objects using
the python configuration system. Mainly it consists of removing
unnecessary ruby object pointers and connecting the necessary object
pointers using the generated param objects. This patch includes the
slicc changes necessary to connect generated ruby objects together using
the python configuraiton system.
diff 6877:2a1a3d916ca8 Fri Jan 29 23:29:00 EST 2010 Steve Reinhardt <steve.reinhardt@amd.com> ruby: Make SLICC-generated objects SimObjects.
Also add SLICC support for state-machine parameter defaults
(passed through to Python as SimObject Param defaults).
/gem5/src/base/
H A Dinet.hhdiff 7778:6a7207241112 Tue Nov 23 17:08:00 EST 2010 Gabe Black <gblack@eecs.umich.edu> Copyright: Add AMD copyright to the param changes I just made.
diff 7777:369f90d32e2e Tue Nov 23 15:54:00 EST 2010 Gabe Black <gblack@eecs.umich.edu> Params: Add parameter types for IP addresses in various forms.

New parameter forms are:
IP address in the format "a.b.c.d" where a-d are from decimal 0 to 255.
IP address with netmask which is an IP followed by "/n" where n is a netmask
length in bits from decimal 0 to 32 or by "/e.f.g.h" where e-h are from
decimal 0 to 255 and which is all 1 bits followed by all 0 bits when
represented in binary. These can also be specified as an integral IP and
netmask passed in separately.
IP address with port which is an IP followed by ":p" where p is a port index
from decimal 0 to 65535. These can also be specified as an integral IP and
port value passed in separately.
H A Dinet.ccdiff 7778:6a7207241112 Tue Nov 23 17:08:00 EST 2010 Gabe Black <gblack@eecs.umich.edu> Copyright: Add AMD copyright to the param changes I just made.
diff 7777:369f90d32e2e Tue Nov 23 15:54:00 EST 2010 Gabe Black <gblack@eecs.umich.edu> Params: Add parameter types for IP addresses in various forms.

New parameter forms are:
IP address in the format "a.b.c.d" where a-d are from decimal 0 to 255.
IP address with netmask which is an IP followed by "/n" where n is a netmask
length in bits from decimal 0 to 32 or by "/e.f.g.h" where e-h are from
decimal 0 to 255 and which is all 1 bits followed by all 0 bits when
represented in binary. These can also be specified as an integral IP and
netmask passed in separately.
IP address with port which is an IP followed by ":p" where p is a port index
from decimal 0 to 65535. These can also be specified as an integral IP and
port value passed in separately.
/gem5/src/sim/
H A DRoot.pydiff 7534:c76a14014c27 Tue Aug 17 08:49:00 EDT 2010 Steve Reinhardt <steve.reinhardt@amd.com> misc: add some AMD copyright notices
Meant to add these with the previous batch of csets.
diff 7525:722f2ad014a7 Tue Aug 17 08:06:00 EDT 2010 Steve Reinhardt <steve.reinhardt@amd.com> sim: make Python Root object a singleton
Enforce that the Python Root SimObject is instantiated only
once. The C++ Root object already panics if more than one is
created. This change avoids the need to track what the root
object is, since it's available from Root.getInstance() (if it
exists). It's now redundant to have the user pass the root
object to functions like instantiate(), checkpoint(), and
restoreCheckpoint(), so that arg is gone. Users who use
configs/common/Simulate.py should not notice.
/gem5/src/mem/ruby/network/simple/
H A DPerfectSwitch.ccdiff 7780:42da07116e12 Wed Dec 01 14:30:00 EST 2010 Nilay Vaish <nilay@cs.wisc.edu> ruby: Converted old ruby debug calls to M5 debug calls

This patch developed by Nilay Vaish converts all the old GEMS-style ruby
debug calls to the appropriate M5 debug calls.
diff 7454:3a3e8e8cce1b Fri Jun 11 02:17:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get rid of Vector and use STL
add a couple of helper functions to base for deleteing all pointers in
a container and outputting containers to a stream
diff 7453:1a5db3dd0f62 Fri Jun 11 02:17:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get rid of RefCnt and Allocator stuff use base/refcnt.hh

This was somewhat tricky because the RefCnt API was somewhat odd. The
biggest confusion was that the the RefCnt object's constructor that
took a TYPE& cloned the object. I created an explicit virtual clone()
function for things that took advantage of this version of the
constructor. I was conservative and used clone() when I was in doubt
of whether or not it was necessary. I still think that there are
probably too many instances of clone(), but hopefully not too many.

I converted several instances of const MsgPtr & to a simple MsgPtr.
If the function wants to avoid the overhead of creating another
reference, then it should just use a regular pointer instead of a ref
counting ptr.

There were a couple of instances where refcounted objects were created
on the stack. This seems pretty dangerous since if you ever
accidentally make a reference to that object with a ref counting
pointer, bad things are bound to happen.
diff 7056:b66b558578bd Fri Apr 02 14:20:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get rid of gems_common/util.hh and .cc and use stuff in src/base
diff 7055:4e24742201d7 Fri Apr 02 14:20:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get "using namespace" out of headers
In addition to obvious changes, this required a slight change to the slicc
grammar to allow types with :: in them. Otherwise slicc barfs on std::string
which we need for the headers that slicc generates.
diff 7054:7d6862b80049 Wed Mar 31 19:56:00 EDT 2010 Nathan Binkert <nate@binkert.org> style: another ruby style pass
diff 7002:48a19d52d939 Wed Mar 10 21:33:00 EST 2010 Nathan Binkert <nate@binkert.org> ruby: get rid of std-includes.hh
Do not use "using namespace std;" in headers
Include header files as needed
diff 6891:77451885bb00 Fri Jan 29 23:29:00 EST 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Removed out_link_vec from Consumer
Removed the out_line_vec data structure from the Consumer. I'm not sure
what this did before, but currently it has no usefulness.
H A DSimpleNetwork.pydiff 7019:a49fd5febdce Mon Mar 22 00:22:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Added copyright to many Ruby *.py files
6876:a658c315512c Fri Jan 29 23:29:00 EST 2010 Steve Reinhardt <steve.reinhardt@amd.com> ruby: Convert most Ruby objects to M5 SimObjects.
The necessary companion conversion of Ruby objects generated by SLICC
are converted to M5 SimObjects in the following patch, so this patch
alone does not compile.
Conversion of Garnet network models is also handled in a separate
patch; that code is temporarily disabled from compiling to allow
testing of interim code.
/gem5/src/dev/arm/
H A Dtimer_sp804.hhdiff 7733:08d6a773d1b6 Mon Nov 08 14:58:00 EST 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add checkpointing support
7584:28ddf6d9e982 Mon Aug 23 12:18:00 EDT 2010 Ali Saidi <Ali.Saidi@arm.com> ARM: Add I/O devices for booting linux
/gem5/src/arch/arm/linux/
H A Dsystem.hhdiff 7733:08d6a773d1b6 Mon Nov 08 14:58:00 EST 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add checkpointing support
7585:afbc40280b56 Mon Aug 23 12:18:00 EDT 2010 Ali Saidi <Ali.Saidi@arm.com> ARM: Add system for ARM/Linux and bootstrapping
/gem5/src/arch/x86/insts/
H A Dstatic_inst.ccdiff 7629:0f0c231e3e97 Mon Aug 23 19:14:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> X86: Create a directory for files that define register indexes.

This is to help tidy up arch/x86. These files should not be used external to
the ISA.
diff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
/gem5/src/arch/x86/
H A Dsystem.hhdiff 7532:3f6413fc37a2 Tue Aug 17 08:17:00 EDT 2010 Steve Reinhardt <steve.reinhardt@amd.com> sim: revamp unserialization procedure

Replace direct call to unserialize() on each SimObject with a pair of
calls for better control over initialization in both ckpt and non-ckpt
cases.

If restoring from a checkpoint, loadState(ckpt) is called on each
SimObject. The default implementation simply calls unserialize() if
there is a corresponding checkpoint section, so we get backward
compatibility for existing objects. However, objects can override
loadState() to get other behaviors, e.g., doing other programmed
initializations after unserialize(), or complaining if no checkpoint
section is found. (Note that the default warning for a missing
checkpoint section is now gone.)

If not restoring from a checkpoint, we call the new initState() method
on each SimObject instead. This provides a hook for state
initializations that are only required when *not* restoring from a
checkpoint.

Given this new framework, do some cleanup of LiveProcess subclasses
and X86System, which were (in some cases) emulating initState()
behavior in startup via a local flag or (in other cases) erroneously
doing initializations in startup() that clobbered state loaded earlier
by unserialize().
diff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
/gem5/configs/ruby/
H A DMI_example.pydiff 7544:90c5eb6a5e66 Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> memtest: Memtester support for DMA

This patch adds DMA testing to the Memtester and is inherits many changes from
Polina's old tester_dma_extension patch. Since Ruby does not work in atomic
mode, the atomic mode options are removed.
diff 7541:1e1f63dfd130 Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> config: Improve ruby simobject names

This patch attaches ruby objects to the system before the topology is
created so that their simobject names read their meaningful variable
names instead of their topology name.
diff 7538:5691b9dd51f4 Fri Aug 20 14:44:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> config: reorganized how ruby specifies command-line options
diff 7535:7f8213cb2337 Fri Aug 20 14:41:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> config: moved python protocol config files

Moved the python protocol config files back to their original location to avoid
addToPath calls.
diff 7032:9f938aea1942 Mon Mar 22 00:22:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Reorganized Ruby topology and protocol files
diff 7025:9adf5b0ccc79 Mon Mar 22 00:22:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Ruby support for sparse memory

The patch includes direct support for the MI example protocol.
diff 7015:6c91d41dfc12 Mon Mar 22 00:22:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Python config files now sets a unique id for each sequencer
6906:35da51c349e2 Fri Jan 29 23:29:00 EST 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: MI_example updates to use the new config system
H A DMOESI_CMP_directory.pydiff 7633:d8112aa18a1b Tue Aug 24 16:20:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> config: fixed ruby dma device connections
diff 7544:90c5eb6a5e66 Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> memtest: Memtester support for DMA

This patch adds DMA testing to the Memtester and is inherits many changes from
Polina's old tester_dma_extension patch. Since Ruby does not work in atomic
mode, the atomic mode options are removed.
diff 7541:1e1f63dfd130 Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> config: Improve ruby simobject names

This patch attaches ruby objects to the system before the topology is
created so that their simobject names read their meaningful variable
names instead of their topology name.
diff 7538:5691b9dd51f4 Fri Aug 20 14:44:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> config: reorganized how ruby specifies command-line options
diff 7535:7f8213cb2337 Fri Aug 20 14:41:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> config: moved python protocol config files

Moved the python protocol config files back to their original location to avoid
addToPath calls.
diff 7032:9f938aea1942 Mon Mar 22 00:22:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Reorganized Ruby topology and protocol files
diff 7015:6c91d41dfc12 Mon Mar 22 00:22:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Python config files now sets a unique id for each sequencer
6911:1fdbff869ff4 Fri Jan 29 23:29:00 EST 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: MOESI_CMP_directory updated to the new config system
/gem5/src/arch/alpha/
H A Disa.ccdiff 7680:f4eda002333b Tue Sep 14 03:29:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> CPU: Trim unnecessary includes from some common files.

This reduces the scope of those includes and makes it less likely for there to
be a dependency loop. This also moves the hashing functions associated with
ExtMachInst objects to be with the ExtMachInst definitions and out of
utility.hh.
diff 7678:f19b6a3a8cec Mon Sep 13 22:26:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.

Also move the "Fault" reference counted pointer type into a separate file,
sim/fault.hh. It would be better to name this less similarly to sim/faults.hh
to reduce confusion, but fault.hh matches the name of the type. We could change
Fault to FaultPtr to match other pointer types, and then changing the name of
the file would make more sense.
/gem5/src/python/m5/util/
H A D__init__.pydiff 7503:37da2c208f5f Wed Jul 21 18:53:00 EDT 2010 Nathan Binkert <nate@binkert.org> python: add a sorted dictionary class
It would be nice if python had a tree class that would do this for real,
but since we don't, we'll just keep a sorted list of keys and update
it on demand.
diff 7459:da32c2b05648 Tue Jun 15 02:24:00 EDT 2010 Nathan Binkert <nate@binkert.org> util: clean up attrdict and import multiattrdict into m5.util
H A Dconvert.pydiff 7778:6a7207241112 Tue Nov 23 17:08:00 EST 2010 Gabe Black <gblack@eecs.umich.edu> Copyright: Add AMD copyright to the param changes I just made.
diff 7777:369f90d32e2e Tue Nov 23 15:54:00 EST 2010 Gabe Black <gblack@eecs.umich.edu> Params: Add parameter types for IP addresses in various forms.

New parameter forms are:
IP address in the format "a.b.c.d" where a-d are from decimal 0 to 255.
IP address with netmask which is an IP followed by "/n" where n is a netmask
length in bits from decimal 0 to 32 or by "/e.f.g.h" where e-h are from
decimal 0 to 255 and which is all 1 bits followed by all 0 bits when
represented in binary. These can also be specified as an integral IP and
netmask passed in separately.
IP address with port which is an IP followed by ":p" where p is a port index
from decimal 0 to 65535. These can also be specified as an integral IP and
port value passed in separately.

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