11689SN/A/*
21689SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan
31689SN/A * All rights reserved.
41689SN/A *
51689SN/A * Redistribution and use in source and binary forms, with or without
61689SN/A * modification, are permitted provided that the following conditions are
71689SN/A * met: redistributions of source code must retain the above copyright
81689SN/A * notice, this list of conditions and the following disclaimer;
91689SN/A * redistributions in binary form must reproduce the above copyright
101689SN/A * notice, this list of conditions and the following disclaimer in the
111689SN/A * documentation and/or other materials provided with the distribution;
121689SN/A * neither the name of the copyright holders nor the names of its
131689SN/A * contributors may be used to endorse or promote products derived from
141689SN/A * this software without specific prior written permission.
151689SN/A *
161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665SN/A *
282665SN/A * Authors: Kevin Lim
291689SN/A */
301689SN/A
319480Snilay@cs.wisc.edu#ifndef __CPU_PRED_RAS_HH__
329480Snilay@cs.wisc.edu#define __CPU_PRED_RAS_HH__
331062SN/A
346216SN/A#include <vector>
356216SN/A
367720Sgblack@eecs.umich.edu#include "arch/types.hh"
376214SN/A#include "base/types.hh"
387720Sgblack@eecs.umich.edu#include "config/the_isa.hh"
391062SN/A
402292SN/A/** Return address stack class, implements a simple RAS. */
411062SN/Aclass ReturnAddrStack
421062SN/A{
431062SN/A  public:
442292SN/A    /** Creates a return address stack, but init() must be called prior to
452292SN/A     *  use.
462292SN/A     */
472292SN/A    ReturnAddrStack() {}
481062SN/A
492292SN/A    /** Initializes RAS with a specified number of entries.
502292SN/A     *  @param numEntries Number of entries in the RAS.
512292SN/A     */
522292SN/A    void init(unsigned numEntries);
532292SN/A
542307SN/A    void reset();
552307SN/A
562292SN/A    /** Returns the top address on the RAS. */
577720Sgblack@eecs.umich.edu    TheISA::PCState top()
581062SN/A    { return addrStack[tos]; }
591062SN/A
602292SN/A    /** Returns the index of the top of the RAS. */
611062SN/A    unsigned topIdx()
621062SN/A    { return tos; }
631062SN/A
642292SN/A    /** Pushes an address onto the RAS. */
657720Sgblack@eecs.umich.edu    void push(const TheISA::PCState &return_addr);
661062SN/A
672292SN/A    /** Pops the top address from the RAS. */
681062SN/A    void pop();
691062SN/A
702292SN/A    /** Changes index to the top of the RAS, and replaces the top address with
712292SN/A     *  a new target.
722292SN/A     *  @param top_entry_idx The index of the RAS that will now be the top.
737720Sgblack@eecs.umich.edu     *  @param restored The new target address of the new top of the RAS.
742292SN/A     */
757720Sgblack@eecs.umich.edu    void restore(unsigned top_entry_idx, const TheISA::PCState &restored);
761062SN/A
775865SN/A     bool empty() { return usedEntries == 0; }
785865SN/A
795865SN/A     bool full() { return usedEntries == numEntries; }
801062SN/A  private:
812292SN/A    /** Increments the top of stack index. */
821062SN/A    inline void incrTos()
831684SN/A    { if (++tos == numEntries) tos = 0; }
841062SN/A
852292SN/A    /** Decrements the top of stack index. */
861062SN/A    inline void decrTos()
871062SN/A    { tos = (tos == 0 ? numEntries - 1 : tos - 1); }
881062SN/A
892292SN/A    /** The RAS itself. */
907720Sgblack@eecs.umich.edu    std::vector<TheISA::PCState> addrStack;
911062SN/A
922292SN/A    /** The number of entries in the RAS. */
931062SN/A    unsigned numEntries;
941062SN/A
952292SN/A    /** The number of used entries in the RAS. */
961062SN/A    unsigned usedEntries;
971062SN/A
982292SN/A    /** The top of stack index. */
991062SN/A    unsigned tos;
1001062SN/A};
1011062SN/A
1029480Snilay@cs.wisc.edu#endif // __CPU_PRED_RAS_HH__
103