16145Snate@binkert.org/* 26145Snate@binkert.org * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 36145Snate@binkert.org * All rights reserved. 46145Snate@binkert.org * 56145Snate@binkert.org * Redistribution and use in source and binary forms, with or without 66145Snate@binkert.org * modification, are permitted provided that the following conditions are 76145Snate@binkert.org * met: redistributions of source code must retain the above copyright 86145Snate@binkert.org * notice, this list of conditions and the following disclaimer; 96145Snate@binkert.org * redistributions in binary form must reproduce the above copyright 106145Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 116145Snate@binkert.org * documentation and/or other materials provided with the distribution; 126145Snate@binkert.org * neither the name of the copyright holders nor the names of its 136145Snate@binkert.org * contributors may be used to endorse or promote products derived from 146145Snate@binkert.org * this software without specific prior written permission. 156145Snate@binkert.org * 166145Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176145Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186145Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196145Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206145Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216145Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226145Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236145Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246145Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256145Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266145Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276145Snate@binkert.org */ 286145Snate@binkert.org 2911793Sbrandon.potter@amd.com#include "mem/ruby/system/Sequencer.hh" 3011793Sbrandon.potter@amd.com 3110467Sandreas.hansson@arm.com#include "arch/x86/ldstflags.hh" 3212334Sgabeblack@google.com#include "base/logging.hh" 337056Snate@binkert.org#include "base/str.hh" 347632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/RubyTester.hh" 358232Snate@binkert.org#include "debug/MemoryAccess.hh" 368232Snate@binkert.org#include "debug/ProtocolTrace.hh" 378615Snilay@cs.wisc.edu#include "debug/RubySequencer.hh" 389104Shestness@cs.utexas.edu#include "debug/RubyStats.hh" 3911793Sbrandon.potter@amd.com#include "mem/packet.hh" 407039Snate@binkert.org#include "mem/ruby/profiler/Profiler.hh" 4114184Sgabeblack@google.com#include "mem/ruby/protocol/PrefetchBit.hh" 4214184Sgabeblack@google.com#include "mem/ruby/protocol/RubyAccessMode.hh" 438229Snate@binkert.org#include "mem/ruby/slicc_interface/RubyRequest.hh" 4411108Sdavid.hashe@amd.com#include "mem/ruby/system/RubySystem.hh" 4510467Sandreas.hansson@arm.com#include "sim/system.hh" 466876Ssteve.reinhardt@amd.com 477055Snate@binkert.orgusing namespace std; 487055Snate@binkert.org 496876Ssteve.reinhardt@amd.comSequencer * 506876Ssteve.reinhardt@amd.comRubySequencerParams::create() 516285Snate@binkert.org{ 526876Ssteve.reinhardt@amd.com return new Sequencer(this); 536285Snate@binkert.org} 547039Snate@binkert.org 556876Ssteve.reinhardt@amd.comSequencer::Sequencer(const Params *p) 5612133Sspwilson2@wisc.edu : RubyPort(p), m_IncompleteTimes(MachineType_NUM), 5712133Sspwilson2@wisc.edu deadlockCheckEvent([this]{ wakeup(); }, "Sequencer deadlock check") 586876Ssteve.reinhardt@amd.com{ 596876Ssteve.reinhardt@amd.com m_outstanding_count = 0; 606285Snate@binkert.org 616876Ssteve.reinhardt@amd.com m_instCache_ptr = p->icache; 626876Ssteve.reinhardt@amd.com m_dataCache_ptr = p->dcache; 636876Ssteve.reinhardt@amd.com m_max_outstanding_requests = p->max_outstanding_requests; 646876Ssteve.reinhardt@amd.com m_deadlock_threshold = p->deadlock_threshold; 656899SBrad.Beckmann@amd.com 6611308Santhony.gutierrez@amd.com m_coreId = p->coreid; // for tracking the two CorePair sequencers 676876Ssteve.reinhardt@amd.com assert(m_max_outstanding_requests > 0); 686876Ssteve.reinhardt@amd.com assert(m_deadlock_threshold > 0); 696876Ssteve.reinhardt@amd.com assert(m_instCache_ptr != NULL); 706876Ssteve.reinhardt@amd.com assert(m_dataCache_ptr != NULL); 718171Stushar@csail.mit.edu 7211660Stushar@ece.gatech.edu m_runningGarnetStandalone = p->garnet_standalone; 736145Snate@binkert.org} 746145Snate@binkert.org 757039Snate@binkert.orgSequencer::~Sequencer() 767039Snate@binkert.org{ 776145Snate@binkert.org} 786145Snate@binkert.org 797039Snate@binkert.orgvoid 807039Snate@binkert.orgSequencer::wakeup() 817039Snate@binkert.org{ 8210913Sandreas.sandberg@arm.com assert(drainState() != DrainState::Draining); 839245Shestness@cs.wisc.edu 847039Snate@binkert.org // Check for deadlock of any of the requests 859501Snilay@cs.wisc.edu Cycles current_time = curCycle(); 866145Snate@binkert.org 877039Snate@binkert.org // Check across all outstanding requests 887039Snate@binkert.org int total_outstanding = 0; 896285Snate@binkert.org 907455Snate@binkert.org RequestTable::iterator read = m_readRequestTable.begin(); 917455Snate@binkert.org RequestTable::iterator read_end = m_readRequestTable.end(); 927455Snate@binkert.org for (; read != read_end; ++read) { 937455Snate@binkert.org SequencerRequest* request = read->second; 947455Snate@binkert.org if (current_time - request->issue_time < m_deadlock_threshold) 957455Snate@binkert.org continue; 967455Snate@binkert.org 977805Snilay@cs.wisc.edu panic("Possible Deadlock detected. Aborting!\n" 9811025Snilay@cs.wisc.edu "version: %d request.paddr: 0x%x m_readRequestTable: %d " 9911025Snilay@cs.wisc.edu "current time: %u issue_time: %d difference: %d\n", m_version, 10011025Snilay@cs.wisc.edu request->pkt->getAddr(), m_readRequestTable.size(), 1019467Smalek.musleh@gmail.com current_time * clockPeriod(), request->issue_time * clockPeriod(), 1029467Smalek.musleh@gmail.com (current_time * clockPeriod()) - (request->issue_time * clockPeriod())); 1036145Snate@binkert.org } 1046145Snate@binkert.org 1057455Snate@binkert.org RequestTable::iterator write = m_writeRequestTable.begin(); 1067455Snate@binkert.org RequestTable::iterator write_end = m_writeRequestTable.end(); 1077455Snate@binkert.org for (; write != write_end; ++write) { 1087455Snate@binkert.org SequencerRequest* request = write->second; 1097455Snate@binkert.org if (current_time - request->issue_time < m_deadlock_threshold) 1107455Snate@binkert.org continue; 1117455Snate@binkert.org 1127805Snilay@cs.wisc.edu panic("Possible Deadlock detected. Aborting!\n" 11311025Snilay@cs.wisc.edu "version: %d request.paddr: 0x%x m_writeRequestTable: %d " 11411025Snilay@cs.wisc.edu "current time: %u issue_time: %d difference: %d\n", m_version, 11511025Snilay@cs.wisc.edu request->pkt->getAddr(), m_writeRequestTable.size(), 1169467Smalek.musleh@gmail.com current_time * clockPeriod(), request->issue_time * clockPeriod(), 1179467Smalek.musleh@gmail.com (current_time * clockPeriod()) - (request->issue_time * clockPeriod())); 1186145Snate@binkert.org } 1196285Snate@binkert.org 1207039Snate@binkert.org total_outstanding += m_writeRequestTable.size(); 1217039Snate@binkert.org total_outstanding += m_readRequestTable.size(); 1226145Snate@binkert.org 1237039Snate@binkert.org assert(m_outstanding_count == total_outstanding); 1247039Snate@binkert.org 1257039Snate@binkert.org if (m_outstanding_count > 0) { 1267039Snate@binkert.org // If there are still outstanding requests, keep checking 1279465Snilay@cs.wisc.edu schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold)); 1287039Snate@binkert.org } 1296145Snate@binkert.org} 1306145Snate@binkert.org 13110012Snilay@cs.wisc.eduvoid Sequencer::resetStats() 1329598Snilay@cs.wisc.edu{ 13310012Snilay@cs.wisc.edu m_latencyHist.reset(); 13410012Snilay@cs.wisc.edu m_hitLatencyHist.reset(); 13510012Snilay@cs.wisc.edu m_missLatencyHist.reset(); 1369773Snilay@cs.wisc.edu for (int i = 0; i < RubyRequestType_NUM; i++) { 13710012Snilay@cs.wisc.edu m_typeLatencyHist[i]->reset(); 13810012Snilay@cs.wisc.edu m_hitTypeLatencyHist[i]->reset(); 13910012Snilay@cs.wisc.edu m_missTypeLatencyHist[i]->reset(); 1409773Snilay@cs.wisc.edu for (int j = 0; j < MachineType_NUM; j++) { 14110012Snilay@cs.wisc.edu m_hitTypeMachLatencyHist[i][j]->reset(); 14210012Snilay@cs.wisc.edu m_missTypeMachLatencyHist[i][j]->reset(); 1439773Snilay@cs.wisc.edu } 1449773Snilay@cs.wisc.edu } 1459773Snilay@cs.wisc.edu 14610012Snilay@cs.wisc.edu for (int i = 0; i < MachineType_NUM; i++) { 14710012Snilay@cs.wisc.edu m_missMachLatencyHist[i]->reset(); 14810012Snilay@cs.wisc.edu m_hitMachLatencyHist[i]->reset(); 1499773Snilay@cs.wisc.edu 15010012Snilay@cs.wisc.edu m_IssueToInitialDelayHist[i]->reset(); 15110012Snilay@cs.wisc.edu m_InitialToForwardDelayHist[i]->reset(); 15210012Snilay@cs.wisc.edu m_ForwardToFirstResponseDelayHist[i]->reset(); 15310012Snilay@cs.wisc.edu m_FirstResponseToCompletionDelayHist[i]->reset(); 1549773Snilay@cs.wisc.edu 1559773Snilay@cs.wisc.edu m_IncompleteTimes[i] = 0; 1569773Snilay@cs.wisc.edu } 1579598Snilay@cs.wisc.edu} 1589598Snilay@cs.wisc.edu 1596145Snate@binkert.org// Insert the request on the correct request table. Return true if 1606145Snate@binkert.org// the entry was already present. 1618615Snilay@cs.wisc.eduRequestStatus 1628615Snilay@cs.wisc.eduSequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type) 1637039Snate@binkert.org{ 1648641Snate@binkert.org assert(m_outstanding_count == 1658641Snate@binkert.org (m_writeRequestTable.size() + m_readRequestTable.size())); 1666145Snate@binkert.org 1677039Snate@binkert.org // See if we should schedule a deadlock check 1689342SAndreas.Sandberg@arm.com if (!deadlockCheckEvent.scheduled() && 16910913Sandreas.sandberg@arm.com drainState() != DrainState::Draining) { 1709465Snilay@cs.wisc.edu schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold)); 1717039Snate@binkert.org } 1726145Snate@binkert.org 17311025Snilay@cs.wisc.edu Addr line_addr = makeLineAddress(pkt->getAddr()); 17411448Sjthestness@gmail.com 17511448Sjthestness@gmail.com // Check if the line is blocked for a Locked_RMW 17611448Sjthestness@gmail.com if (m_controller->isBlocked(line_addr) && 17711448Sjthestness@gmail.com (request_type != RubyRequestType_Locked_RMW_Write)) { 17811448Sjthestness@gmail.com // Return that this request's cache line address aliases with 17911448Sjthestness@gmail.com // a prior request that locked the cache line. The request cannot 18011448Sjthestness@gmail.com // proceed until the cache line is unlocked by a Locked_RMW_Write 18111448Sjthestness@gmail.com return RequestStatus_Aliased; 18211448Sjthestness@gmail.com } 18311448Sjthestness@gmail.com 1849224Sandreas.hansson@arm.com // Create a default entry, mapping the address to NULL, the cast is 1859224Sandreas.hansson@arm.com // there to make gcc 4.4 happy 1869224Sandreas.hansson@arm.com RequestTable::value_type default_entry(line_addr, 1879224Sandreas.hansson@arm.com (SequencerRequest*) NULL); 1889224Sandreas.hansson@arm.com 1898615Snilay@cs.wisc.edu if ((request_type == RubyRequestType_ST) || 1908615Snilay@cs.wisc.edu (request_type == RubyRequestType_RMW_Read) || 1918615Snilay@cs.wisc.edu (request_type == RubyRequestType_RMW_Write) || 1928615Snilay@cs.wisc.edu (request_type == RubyRequestType_Load_Linked) || 1938615Snilay@cs.wisc.edu (request_type == RubyRequestType_Store_Conditional) || 1948615Snilay@cs.wisc.edu (request_type == RubyRequestType_Locked_RMW_Read) || 1958615Snilay@cs.wisc.edu (request_type == RubyRequestType_Locked_RMW_Write) || 1968615Snilay@cs.wisc.edu (request_type == RubyRequestType_FLUSH)) { 1978615Snilay@cs.wisc.edu 1988615Snilay@cs.wisc.edu // Check if there is any outstanding read request for the same 1998615Snilay@cs.wisc.edu // cache line. 2008615Snilay@cs.wisc.edu if (m_readRequestTable.count(line_addr) > 0) { 20110012Snilay@cs.wisc.edu m_store_waiting_on_load++; 2028615Snilay@cs.wisc.edu return RequestStatus_Aliased; 2038615Snilay@cs.wisc.edu } 2048615Snilay@cs.wisc.edu 2057455Snate@binkert.org pair<RequestTable::iterator, bool> r = 2069224Sandreas.hansson@arm.com m_writeRequestTable.insert(default_entry); 2078615Snilay@cs.wisc.edu if (r.second) { 2088615Snilay@cs.wisc.edu RequestTable::iterator i = r.first; 2099465Snilay@cs.wisc.edu i->second = new SequencerRequest(pkt, request_type, curCycle()); 2108615Snilay@cs.wisc.edu m_outstanding_count++; 2118615Snilay@cs.wisc.edu } else { 2128615Snilay@cs.wisc.edu // There is an outstanding write request for the cache line 21310012Snilay@cs.wisc.edu m_store_waiting_on_store++; 2148615Snilay@cs.wisc.edu return RequestStatus_Aliased; 2158615Snilay@cs.wisc.edu } 2168615Snilay@cs.wisc.edu } else { 2178615Snilay@cs.wisc.edu // Check if there is any outstanding write request for the same 2188615Snilay@cs.wisc.edu // cache line. 2198615Snilay@cs.wisc.edu if (m_writeRequestTable.count(line_addr) > 0) { 22010012Snilay@cs.wisc.edu m_load_waiting_on_store++; 2218615Snilay@cs.wisc.edu return RequestStatus_Aliased; 2228615Snilay@cs.wisc.edu } 2237039Snate@binkert.org 2247455Snate@binkert.org pair<RequestTable::iterator, bool> r = 2259224Sandreas.hansson@arm.com m_readRequestTable.insert(default_entry); 2267039Snate@binkert.org 2278615Snilay@cs.wisc.edu if (r.second) { 2288615Snilay@cs.wisc.edu RequestTable::iterator i = r.first; 2299465Snilay@cs.wisc.edu i->second = new SequencerRequest(pkt, request_type, curCycle()); 2308615Snilay@cs.wisc.edu m_outstanding_count++; 2318615Snilay@cs.wisc.edu } else { 2328615Snilay@cs.wisc.edu // There is an outstanding read request for the cache line 23310012Snilay@cs.wisc.edu m_load_waiting_on_load++; 2348615Snilay@cs.wisc.edu return RequestStatus_Aliased; 2357039Snate@binkert.org } 2366145Snate@binkert.org } 2376145Snate@binkert.org 23810012Snilay@cs.wisc.edu m_outstandReqHist.sample(m_outstanding_count); 2398641Snate@binkert.org assert(m_outstanding_count == 2408641Snate@binkert.org (m_writeRequestTable.size() + m_readRequestTable.size())); 2416145Snate@binkert.org 2428615Snilay@cs.wisc.edu return RequestStatus_Ready; 2436145Snate@binkert.org} 2446145Snate@binkert.org 2457039Snate@binkert.orgvoid 2467455Snate@binkert.orgSequencer::markRemoved() 2477455Snate@binkert.org{ 2487455Snate@binkert.org m_outstanding_count--; 2497455Snate@binkert.org assert(m_outstanding_count == 2507455Snate@binkert.org m_writeRequestTable.size() + m_readRequestTable.size()); 2517455Snate@binkert.org} 2527455Snate@binkert.org 2537455Snate@binkert.orgvoid 25411025Snilay@cs.wisc.eduSequencer::invalidateSC(Addr address) 2559563Sgope@wisc.edu{ 25611059Snilay@cs.wisc.edu AbstractCacheEntry *e = m_dataCache_ptr->lookup(address); 25711059Snilay@cs.wisc.edu // The controller has lost the coherence permissions, hence the lock 25811059Snilay@cs.wisc.edu // on the cache line maintained by the cache should be cleared. 25911059Snilay@cs.wisc.edu if (e && e->isLocked(m_version)) { 26011059Snilay@cs.wisc.edu e->clearLocked(); 2619563Sgope@wisc.edu } 2629563Sgope@wisc.edu} 2639563Sgope@wisc.edu 2647560SBrad.Beckmann@amd.combool 26511025Snilay@cs.wisc.eduSequencer::handleLlsc(Addr address, SequencerRequest* request) 2667550SBrad.Beckmann@amd.com{ 26711059Snilay@cs.wisc.edu AbstractCacheEntry *e = m_dataCache_ptr->lookup(address); 26811059Snilay@cs.wisc.edu if (!e) 26911059Snilay@cs.wisc.edu return true; 27011059Snilay@cs.wisc.edu 2717560SBrad.Beckmann@amd.com // The success flag indicates whether the LLSC operation was successful. 2727560SBrad.Beckmann@amd.com // LL ops will always succeed, but SC may fail if the cache line is no 2737560SBrad.Beckmann@amd.com // longer locked. 2747560SBrad.Beckmann@amd.com bool success = true; 2758615Snilay@cs.wisc.edu if (request->m_type == RubyRequestType_Store_Conditional) { 27611059Snilay@cs.wisc.edu if (!e->isLocked(m_version)) { 2777550SBrad.Beckmann@amd.com // 2787550SBrad.Beckmann@amd.com // For failed SC requests, indicate the failure to the cpu by 2797550SBrad.Beckmann@amd.com // setting the extra data to zero. 2807550SBrad.Beckmann@amd.com // 2818615Snilay@cs.wisc.edu request->pkt->req->setExtraData(0); 2827560SBrad.Beckmann@amd.com success = false; 2837550SBrad.Beckmann@amd.com } else { 2847550SBrad.Beckmann@amd.com // 2857550SBrad.Beckmann@amd.com // For successful SC requests, indicate the success to the cpu by 28610917Sbrandon.potter@amd.com // setting the extra data to one. 2877550SBrad.Beckmann@amd.com // 2888615Snilay@cs.wisc.edu request->pkt->req->setExtraData(1); 2897550SBrad.Beckmann@amd.com } 2907560SBrad.Beckmann@amd.com // 2917560SBrad.Beckmann@amd.com // Independent of success, all SC operations must clear the lock 2927560SBrad.Beckmann@amd.com // 29311059Snilay@cs.wisc.edu e->clearLocked(); 2948615Snilay@cs.wisc.edu } else if (request->m_type == RubyRequestType_Load_Linked) { 2957550SBrad.Beckmann@amd.com // 2967550SBrad.Beckmann@amd.com // Note: To fully follow Alpha LLSC semantics, should the LL clear any 2977550SBrad.Beckmann@amd.com // previously locked cache lines? 2987550SBrad.Beckmann@amd.com // 29911059Snilay@cs.wisc.edu e->setLocked(m_version); 30011059Snilay@cs.wisc.edu } else if (e->isLocked(m_version)) { 3017550SBrad.Beckmann@amd.com // 3027550SBrad.Beckmann@amd.com // Normal writes should clear the locked address 3037550SBrad.Beckmann@amd.com // 30411059Snilay@cs.wisc.edu e->clearLocked(); 3057550SBrad.Beckmann@amd.com } 3067560SBrad.Beckmann@amd.com return success; 3077550SBrad.Beckmann@amd.com} 3087550SBrad.Beckmann@amd.com 3097550SBrad.Beckmann@amd.comvoid 3109773Snilay@cs.wisc.eduSequencer::recordMissLatency(const Cycles cycles, const RubyRequestType type, 3119773Snilay@cs.wisc.edu const MachineType respondingMach, 3129773Snilay@cs.wisc.edu bool isExternalHit, Cycles issuedTime, 3139773Snilay@cs.wisc.edu Cycles initialRequestTime, 3149773Snilay@cs.wisc.edu Cycles forwardRequestTime, 3159773Snilay@cs.wisc.edu Cycles firstResponseTime, Cycles completionTime) 3167039Snate@binkert.org{ 31710012Snilay@cs.wisc.edu m_latencyHist.sample(cycles); 31810012Snilay@cs.wisc.edu m_typeLatencyHist[type]->sample(cycles); 3199773Snilay@cs.wisc.edu 3209773Snilay@cs.wisc.edu if (isExternalHit) { 32110012Snilay@cs.wisc.edu m_missLatencyHist.sample(cycles); 32210012Snilay@cs.wisc.edu m_missTypeLatencyHist[type]->sample(cycles); 3239773Snilay@cs.wisc.edu 3249773Snilay@cs.wisc.edu if (respondingMach != MachineType_NUM) { 32510012Snilay@cs.wisc.edu m_missMachLatencyHist[respondingMach]->sample(cycles); 32610012Snilay@cs.wisc.edu m_missTypeMachLatencyHist[type][respondingMach]->sample(cycles); 3279773Snilay@cs.wisc.edu 3289773Snilay@cs.wisc.edu if ((issuedTime <= initialRequestTime) && 3299773Snilay@cs.wisc.edu (initialRequestTime <= forwardRequestTime) && 3309773Snilay@cs.wisc.edu (forwardRequestTime <= firstResponseTime) && 3319773Snilay@cs.wisc.edu (firstResponseTime <= completionTime)) { 3329773Snilay@cs.wisc.edu 33310012Snilay@cs.wisc.edu m_IssueToInitialDelayHist[respondingMach]->sample( 3349773Snilay@cs.wisc.edu initialRequestTime - issuedTime); 33510012Snilay@cs.wisc.edu m_InitialToForwardDelayHist[respondingMach]->sample( 3369773Snilay@cs.wisc.edu forwardRequestTime - initialRequestTime); 33710012Snilay@cs.wisc.edu m_ForwardToFirstResponseDelayHist[respondingMach]->sample( 3389773Snilay@cs.wisc.edu firstResponseTime - forwardRequestTime); 33910012Snilay@cs.wisc.edu m_FirstResponseToCompletionDelayHist[respondingMach]->sample( 3409773Snilay@cs.wisc.edu completionTime - firstResponseTime); 3419773Snilay@cs.wisc.edu } else { 3429773Snilay@cs.wisc.edu m_IncompleteTimes[respondingMach]++; 3439773Snilay@cs.wisc.edu } 3449773Snilay@cs.wisc.edu } 3459773Snilay@cs.wisc.edu } else { 34610012Snilay@cs.wisc.edu m_hitLatencyHist.sample(cycles); 34710012Snilay@cs.wisc.edu m_hitTypeLatencyHist[type]->sample(cycles); 3489773Snilay@cs.wisc.edu 3499773Snilay@cs.wisc.edu if (respondingMach != MachineType_NUM) { 35010012Snilay@cs.wisc.edu m_hitMachLatencyHist[respondingMach]->sample(cycles); 35110012Snilay@cs.wisc.edu m_hitTypeMachLatencyHist[type][respondingMach]->sample(cycles); 3529773Snilay@cs.wisc.edu } 3539773Snilay@cs.wisc.edu } 3547546SBrad.Beckmann@amd.com} 3557546SBrad.Beckmann@amd.com 3567546SBrad.Beckmann@amd.comvoid 35711025Snilay@cs.wisc.eduSequencer::writeCallback(Addr address, DataBlock& data, 3589773Snilay@cs.wisc.edu const bool externalHit, const MachineType mach, 3599773Snilay@cs.wisc.edu const Cycles initialRequestTime, 3609773Snilay@cs.wisc.edu const Cycles forwardRequestTime, 3619773Snilay@cs.wisc.edu const Cycles firstResponseTime) 3627565SBrad.Beckmann@amd.com{ 36311025Snilay@cs.wisc.edu assert(address == makeLineAddress(address)); 36411025Snilay@cs.wisc.edu assert(m_writeRequestTable.count(makeLineAddress(address))); 3656145Snate@binkert.org 3667455Snate@binkert.org RequestTable::iterator i = m_writeRequestTable.find(address); 3677455Snate@binkert.org assert(i != m_writeRequestTable.end()); 3687455Snate@binkert.org SequencerRequest* request = i->second; 3696145Snate@binkert.org 3707455Snate@binkert.org m_writeRequestTable.erase(i); 3717455Snate@binkert.org markRemoved(); 3726846Spdudnik@cs.wisc.edu 3738615Snilay@cs.wisc.edu assert((request->m_type == RubyRequestType_ST) || 3748615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_ATOMIC) || 3758615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_RMW_Read) || 3768615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_RMW_Write) || 3778615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_Load_Linked) || 3788615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_Store_Conditional) || 3798615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_Locked_RMW_Read) || 3808615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_Locked_RMW_Write) || 3818615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_FLUSH)); 3828184Ssomayeh@cs.wisc.edu 3837550SBrad.Beckmann@amd.com // 3847550SBrad.Beckmann@amd.com // For Alpha, properly handle LL, SC, and write requests with respect to 3857550SBrad.Beckmann@amd.com // locked cache blocks. 3867550SBrad.Beckmann@amd.com // 38711660Stushar@ece.gatech.edu // Not valid for Garnet_standalone protocl 3888171Stushar@csail.mit.edu // 3898171Stushar@csail.mit.edu bool success = true; 39011660Stushar@ece.gatech.edu if (!m_runningGarnetStandalone) 3918171Stushar@csail.mit.edu success = handleLlsc(address, request); 3927550SBrad.Beckmann@amd.com 39311448Sjthestness@gmail.com // Handle SLICC block_on behavior for Locked_RMW accesses. NOTE: the 39411448Sjthestness@gmail.com // address variable here is assumed to be a line address, so when 39511448Sjthestness@gmail.com // blocking buffers, must check line addresses. 3968615Snilay@cs.wisc.edu if (request->m_type == RubyRequestType_Locked_RMW_Read) { 39711448Sjthestness@gmail.com // blockOnQueue blocks all first-level cache controller queues 39811448Sjthestness@gmail.com // waiting on memory accesses for the specified address that go to 39911448Sjthestness@gmail.com // the specified queue. In this case, a Locked_RMW_Write must go to 40011448Sjthestness@gmail.com // the mandatory_q before unblocking the first-level controller. 40111448Sjthestness@gmail.com // This will block standard loads, stores, ifetches, etc. 4027039Snate@binkert.org m_controller->blockOnQueue(address, m_mandatory_q_ptr); 4038615Snilay@cs.wisc.edu } else if (request->m_type == RubyRequestType_Locked_RMW_Write) { 4047039Snate@binkert.org m_controller->unblock(address); 4057039Snate@binkert.org } 4066863Sdrh5@cs.wisc.edu 4079773Snilay@cs.wisc.edu hitCallback(request, data, success, mach, externalHit, 4087565SBrad.Beckmann@amd.com initialRequestTime, forwardRequestTime, firstResponseTime); 4096145Snate@binkert.org} 4106145Snate@binkert.org 4117039Snate@binkert.orgvoid 41211025Snilay@cs.wisc.eduSequencer::readCallback(Addr address, DataBlock& data, 4139773Snilay@cs.wisc.edu bool externalHit, const MachineType mach, 4149507Snilay@cs.wisc.edu Cycles initialRequestTime, 4159507Snilay@cs.wisc.edu Cycles forwardRequestTime, 4169507Snilay@cs.wisc.edu Cycles firstResponseTime) 4177565SBrad.Beckmann@amd.com{ 41811025Snilay@cs.wisc.edu assert(address == makeLineAddress(address)); 41911025Snilay@cs.wisc.edu assert(m_readRequestTable.count(makeLineAddress(address))); 4206145Snate@binkert.org 4217455Snate@binkert.org RequestTable::iterator i = m_readRequestTable.find(address); 4227455Snate@binkert.org assert(i != m_readRequestTable.end()); 4237455Snate@binkert.org SequencerRequest* request = i->second; 4247455Snate@binkert.org 4257455Snate@binkert.org m_readRequestTable.erase(i); 4267455Snate@binkert.org markRemoved(); 4276145Snate@binkert.org 4288615Snilay@cs.wisc.edu assert((request->m_type == RubyRequestType_LD) || 4298615Snilay@cs.wisc.edu (request->m_type == RubyRequestType_IFETCH)); 4306285Snate@binkert.org 4319773Snilay@cs.wisc.edu hitCallback(request, data, true, mach, externalHit, 4327565SBrad.Beckmann@amd.com initialRequestTime, forwardRequestTime, firstResponseTime); 4336145Snate@binkert.org} 4346145Snate@binkert.org 4357039Snate@binkert.orgvoid 4369773Snilay@cs.wisc.eduSequencer::hitCallback(SequencerRequest* srequest, DataBlock& data, 4379773Snilay@cs.wisc.edu bool llscSuccess, 4389773Snilay@cs.wisc.edu const MachineType mach, const bool externalHit, 4399773Snilay@cs.wisc.edu const Cycles initialRequestTime, 4409773Snilay@cs.wisc.edu const Cycles forwardRequestTime, 4419773Snilay@cs.wisc.edu const Cycles firstResponseTime) 4427039Snate@binkert.org{ 44311087Snilay@cs.wisc.edu warn_once("Replacement policy updates recently became the responsibility " 44411087Snilay@cs.wisc.edu "of SLICC state machines. Make sure to setMRU() near callbacks " 44511087Snilay@cs.wisc.edu "in .sm files!"); 44611087Snilay@cs.wisc.edu 4478615Snilay@cs.wisc.edu PacketPtr pkt = srequest->pkt; 44811025Snilay@cs.wisc.edu Addr request_address(pkt->getAddr()); 4498615Snilay@cs.wisc.edu RubyRequestType type = srequest->m_type; 4509507Snilay@cs.wisc.edu Cycles issued_time = srequest->issue_time; 4516145Snate@binkert.org 4529465Snilay@cs.wisc.edu assert(curCycle() >= issued_time); 4539773Snilay@cs.wisc.edu Cycles total_latency = curCycle() - issued_time; 4546145Snate@binkert.org 4559773Snilay@cs.wisc.edu // Profile the latency for all demand accesses. 4569773Snilay@cs.wisc.edu recordMissLatency(total_latency, type, mach, externalHit, issued_time, 4579773Snilay@cs.wisc.edu initialRequestTime, forwardRequestTime, 4589773Snilay@cs.wisc.edu firstResponseTime, curCycle()); 4596285Snate@binkert.org 46011025Snilay@cs.wisc.edu DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %d cycles\n", 4619773Snilay@cs.wisc.edu curTick(), m_version, "Seq", 4629773Snilay@cs.wisc.edu llscSuccess ? "Done" : "SC_Failed", "", "", 46311118Snilay@cs.wisc.edu printAddress(request_address), total_latency); 4646285Snate@binkert.org 46510562Sandreas.hansson@arm.com // update the data unless it is a non-data-carrying flush 46610837Sjthestness@gmail.com if (RubySystem::getWarmupEnabled()) { 46710563Sandreas.hansson@arm.com data.setData(pkt->getConstPtr<uint8_t>(), 46811025Snilay@cs.wisc.edu getOffset(request_address), pkt->getSize()); 46910562Sandreas.hansson@arm.com } else if (!pkt->isFlush()) { 4707039Snate@binkert.org if ((type == RubyRequestType_LD) || 4717039Snate@binkert.org (type == RubyRequestType_IFETCH) || 4727039Snate@binkert.org (type == RubyRequestType_RMW_Read) || 4737908Shestness@cs.utexas.edu (type == RubyRequestType_Locked_RMW_Read) || 4747907Shestness@cs.utexas.edu (type == RubyRequestType_Load_Linked)) { 47513399Sodanrc@yahoo.com.br pkt->setData( 47613399Sodanrc@yahoo.com.br data.getData(getOffset(request_address), pkt->getSize())); 47710954SBrad.Beckmann@amd.com DPRINTF(RubySequencer, "read data %s\n", data); 47811519Smarco.elver@ed.ac.uk } else if (pkt->req->isSwap()) { 47911519Smarco.elver@ed.ac.uk std::vector<uint8_t> overwrite_val(pkt->getSize()); 48013399Sodanrc@yahoo.com.br pkt->writeData(&overwrite_val[0]); 48113399Sodanrc@yahoo.com.br pkt->setData( 48213399Sodanrc@yahoo.com.br data.getData(getOffset(request_address), pkt->getSize())); 48311519Smarco.elver@ed.ac.uk data.setData(&overwrite_val[0], 48411519Smarco.elver@ed.ac.uk getOffset(request_address), pkt->getSize()); 48511519Smarco.elver@ed.ac.uk DPRINTF(RubySequencer, "swap data %s\n", data); 48612051Snikos.nikoleris@arm.com } else if (type != RubyRequestType_Store_Conditional || llscSuccess) { 48712051Snikos.nikoleris@arm.com // Types of stores set the actual data here, apart from 48812051Snikos.nikoleris@arm.com // failed Store Conditional requests 48910563Sandreas.hansson@arm.com data.setData(pkt->getConstPtr<uint8_t>(), 49011025Snilay@cs.wisc.edu getOffset(request_address), pkt->getSize()); 49110954SBrad.Beckmann@amd.com DPRINTF(RubySequencer, "set data %s\n", data); 4927039Snate@binkert.org } 4937039Snate@binkert.org } 4947023SBrad.Beckmann@amd.com 4957039Snate@binkert.org // If using the RubyTester, update the RubyTester sender state's 4967039Snate@binkert.org // subBlock with the recieved data. The tester will later access 4977039Snate@binkert.org // this state. 4987039Snate@binkert.org if (m_usingRubyTester) { 49910657Sandreas.hansson@arm.com DPRINTF(RubySequencer, "hitCallback %s 0x%x using RubyTester\n", 50010657Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr()); 5017039Snate@binkert.org RubyTester::SenderState* testerSenderState = 50210089Sandreas.hansson@arm.com pkt->findNextSenderState<RubyTester::SenderState>(); 50310089Sandreas.hansson@arm.com assert(testerSenderState); 5049542Sandreas.hansson@arm.com testerSenderState->subBlock.mergeFrom(data); 5057039Snate@binkert.org } 5067023SBrad.Beckmann@amd.com 5077039Snate@binkert.org delete srequest; 5088688Snilay@cs.wisc.edu 50910919Sbrandon.potter@amd.com RubySystem *rs = m_ruby_system; 51010837Sjthestness@gmail.com if (RubySystem::getWarmupEnabled()) { 5119632Sjthestness@gmail.com assert(pkt->req); 5128688Snilay@cs.wisc.edu delete pkt; 51310919Sbrandon.potter@amd.com rs->m_cache_recorder->enqueueNextFetchRequest(); 51410837Sjthestness@gmail.com } else if (RubySystem::getCooldownEnabled()) { 5158688Snilay@cs.wisc.edu delete pkt; 51610919Sbrandon.potter@amd.com rs->m_cache_recorder->enqueueNextFlushRequest(); 5178688Snilay@cs.wisc.edu } else { 5188688Snilay@cs.wisc.edu ruby_hit_callback(pkt); 51911266SBrad.Beckmann@amd.com testDrainComplete(); 5208688Snilay@cs.wisc.edu } 5216285Snate@binkert.org} 5226285Snate@binkert.org 5237039Snate@binkert.orgbool 5247039Snate@binkert.orgSequencer::empty() const 5257039Snate@binkert.org{ 5267455Snate@binkert.org return m_writeRequestTable.empty() && m_readRequestTable.empty(); 5276145Snate@binkert.org} 5286145Snate@binkert.org 5297039Snate@binkert.orgRequestStatus 5308615Snilay@cs.wisc.eduSequencer::makeRequest(PacketPtr pkt) 5317039Snate@binkert.org{ 5328615Snilay@cs.wisc.edu if (m_outstanding_count >= m_max_outstanding_requests) { 5338615Snilay@cs.wisc.edu return RequestStatus_BufferFull; 5348615Snilay@cs.wisc.edu } 5358615Snilay@cs.wisc.edu 5368615Snilay@cs.wisc.edu RubyRequestType primary_type = RubyRequestType_NULL; 5378615Snilay@cs.wisc.edu RubyRequestType secondary_type = RubyRequestType_NULL; 5388615Snilay@cs.wisc.edu 5398615Snilay@cs.wisc.edu if (pkt->isLLSC()) { 5408615Snilay@cs.wisc.edu // 5418615Snilay@cs.wisc.edu // Alpha LL/SC instructions need to be handled carefully by the cache 5428615Snilay@cs.wisc.edu // coherence protocol to ensure they follow the proper semantics. In 5438615Snilay@cs.wisc.edu // particular, by identifying the operations as atomic, the protocol 5448615Snilay@cs.wisc.edu // should understand that migratory sharing optimizations should not 5458615Snilay@cs.wisc.edu // be performed (i.e. a load between the LL and SC should not steal 5468615Snilay@cs.wisc.edu // away exclusive permission). 5478615Snilay@cs.wisc.edu // 5488615Snilay@cs.wisc.edu if (pkt->isWrite()) { 5498615Snilay@cs.wisc.edu DPRINTF(RubySequencer, "Issuing SC\n"); 5508615Snilay@cs.wisc.edu primary_type = RubyRequestType_Store_Conditional; 5518615Snilay@cs.wisc.edu } else { 5528615Snilay@cs.wisc.edu DPRINTF(RubySequencer, "Issuing LL\n"); 5538615Snilay@cs.wisc.edu assert(pkt->isRead()); 5548615Snilay@cs.wisc.edu primary_type = RubyRequestType_Load_Linked; 5558615Snilay@cs.wisc.edu } 5568615Snilay@cs.wisc.edu secondary_type = RubyRequestType_ATOMIC; 55710760Ssteve.reinhardt@amd.com } else if (pkt->req->isLockedRMW()) { 5588615Snilay@cs.wisc.edu // 5598615Snilay@cs.wisc.edu // x86 locked instructions are translated to store cache coherence 5608615Snilay@cs.wisc.edu // requests because these requests should always be treated as read 5618615Snilay@cs.wisc.edu // exclusive operations and should leverage any migratory sharing 5628615Snilay@cs.wisc.edu // optimization built into the protocol. 5638615Snilay@cs.wisc.edu // 5648615Snilay@cs.wisc.edu if (pkt->isWrite()) { 5658615Snilay@cs.wisc.edu DPRINTF(RubySequencer, "Issuing Locked RMW Write\n"); 5668615Snilay@cs.wisc.edu primary_type = RubyRequestType_Locked_RMW_Write; 5678615Snilay@cs.wisc.edu } else { 5688615Snilay@cs.wisc.edu DPRINTF(RubySequencer, "Issuing Locked RMW Read\n"); 5698615Snilay@cs.wisc.edu assert(pkt->isRead()); 5708615Snilay@cs.wisc.edu primary_type = RubyRequestType_Locked_RMW_Read; 5718615Snilay@cs.wisc.edu } 5728615Snilay@cs.wisc.edu secondary_type = RubyRequestType_ST; 5738615Snilay@cs.wisc.edu } else { 57411519Smarco.elver@ed.ac.uk // 57511519Smarco.elver@ed.ac.uk // To support SwapReq, we need to check isWrite() first: a SwapReq 57611519Smarco.elver@ed.ac.uk // should always be treated like a write, but since a SwapReq implies 57711519Smarco.elver@ed.ac.uk // both isWrite() and isRead() are true, check isWrite() first here. 57811519Smarco.elver@ed.ac.uk // 57911519Smarco.elver@ed.ac.uk if (pkt->isWrite()) { 58011519Smarco.elver@ed.ac.uk // 58111519Smarco.elver@ed.ac.uk // Note: M5 packets do not differentiate ST from RMW_Write 58211519Smarco.elver@ed.ac.uk // 58311519Smarco.elver@ed.ac.uk primary_type = secondary_type = RubyRequestType_ST; 58411519Smarco.elver@ed.ac.uk } else if (pkt->isRead()) { 5858615Snilay@cs.wisc.edu if (pkt->req->isInstFetch()) { 5868615Snilay@cs.wisc.edu primary_type = secondary_type = RubyRequestType_IFETCH; 5878615Snilay@cs.wisc.edu } else { 5888615Snilay@cs.wisc.edu bool storeCheck = false; 58910467Sandreas.hansson@arm.com // only X86 need the store check 59010467Sandreas.hansson@arm.com if (system->getArch() == Arch::X86ISA) { 59110467Sandreas.hansson@arm.com uint32_t flags = pkt->req->getFlags(); 59210467Sandreas.hansson@arm.com storeCheck = flags & 59310467Sandreas.hansson@arm.com (X86ISA::StoreCheck << X86ISA::FlagShift); 59410467Sandreas.hansson@arm.com } 5958615Snilay@cs.wisc.edu if (storeCheck) { 5968615Snilay@cs.wisc.edu primary_type = RubyRequestType_RMW_Read; 5978615Snilay@cs.wisc.edu secondary_type = RubyRequestType_ST; 5988615Snilay@cs.wisc.edu } else { 5998615Snilay@cs.wisc.edu primary_type = secondary_type = RubyRequestType_LD; 6008615Snilay@cs.wisc.edu } 6018615Snilay@cs.wisc.edu } 6028615Snilay@cs.wisc.edu } else if (pkt->isFlush()) { 6038615Snilay@cs.wisc.edu primary_type = secondary_type = RubyRequestType_FLUSH; 6048615Snilay@cs.wisc.edu } else { 6058615Snilay@cs.wisc.edu panic("Unsupported ruby packet type\n"); 6068615Snilay@cs.wisc.edu } 6078615Snilay@cs.wisc.edu } 6088615Snilay@cs.wisc.edu 6098615Snilay@cs.wisc.edu RequestStatus status = insertRequest(pkt, primary_type); 6107039Snate@binkert.org if (status != RequestStatus_Ready) 6117039Snate@binkert.org return status; 6126349Spdudnik@gmail.com 6138615Snilay@cs.wisc.edu issueRequest(pkt, secondary_type); 6146145Snate@binkert.org 6157039Snate@binkert.org // TODO: issue hardware prefetches here 6167039Snate@binkert.org return RequestStatus_Issued; 6176145Snate@binkert.org} 6186145Snate@binkert.org 6197039Snate@binkert.orgvoid 6208615Snilay@cs.wisc.eduSequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type) 6217039Snate@binkert.org{ 6229216Sandreas.hansson@arm.com assert(pkt != NULL); 62311005Sandreas.sandberg@arm.com ContextID proc_id = pkt->req->hasContextId() ? 62411005Sandreas.sandberg@arm.com pkt->req->contextId() : InvalidContextID; 6256285Snate@binkert.org 62611308Santhony.gutierrez@amd.com ContextID core_id = coreId(); 62711308Santhony.gutierrez@amd.com 6288615Snilay@cs.wisc.edu // If valid, copy the pc to the ruby request 6298615Snilay@cs.wisc.edu Addr pc = 0; 6308615Snilay@cs.wisc.edu if (pkt->req->hasPC()) { 6318615Snilay@cs.wisc.edu pc = pkt->req->getPC(); 6327039Snate@binkert.org } 6336285Snate@binkert.org 63410562Sandreas.hansson@arm.com // check if the packet has data as for example prefetch and flush 63510562Sandreas.hansson@arm.com // requests do not 63610472Sandreas.hansson@arm.com std::shared_ptr<RubyRequest> msg = 63710472Sandreas.hansson@arm.com std::make_shared<RubyRequest>(clockEdge(), pkt->getAddr(), 63810562Sandreas.hansson@arm.com pkt->isFlush() ? 63910562Sandreas.hansson@arm.com nullptr : pkt->getPtr<uint8_t>(), 64010472Sandreas.hansson@arm.com pkt->getSize(), pc, secondary_type, 64110472Sandreas.hansson@arm.com RubyAccessMode_Supervisor, pkt, 64211308Santhony.gutierrez@amd.com PrefetchBit_No, proc_id, core_id); 6436285Snate@binkert.org 64411025Snilay@cs.wisc.edu DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %s\n", 6458266Sksewell@umich.edu curTick(), m_version, "Seq", "Begin", "", "", 64611118Snilay@cs.wisc.edu printAddress(msg->getPhysicalAddress()), 6478615Snilay@cs.wisc.edu RubyRequestType_to_string(secondary_type)); 6486285Snate@binkert.org 64913974Stiago.muck@arm.com Tick latency = cyclesToTicks( 65013974Stiago.muck@arm.com m_controller->mandatoryQueueLatency(secondary_type)); 6517039Snate@binkert.org assert(latency > 0); 6526145Snate@binkert.org 6537039Snate@binkert.org assert(m_mandatory_q_ptr != NULL); 65413974Stiago.muck@arm.com m_mandatory_q_ptr->enqueue(msg, clockEdge(), latency); 6556145Snate@binkert.org} 6566145Snate@binkert.org 6577455Snate@binkert.orgtemplate <class KEY, class VALUE> 6587455Snate@binkert.orgstd::ostream & 65911168Sandreas.hansson@arm.comoperator<<(ostream &out, const std::unordered_map<KEY, VALUE> &map) 6607455Snate@binkert.org{ 66111168Sandreas.hansson@arm.com auto i = map.begin(); 66211168Sandreas.hansson@arm.com auto end = map.end(); 6637455Snate@binkert.org 6647455Snate@binkert.org out << "["; 6657455Snate@binkert.org for (; i != end; ++i) 6667455Snate@binkert.org out << " " << i->first << "=" << i->second; 6677455Snate@binkert.org out << " ]"; 6687455Snate@binkert.org 6697455Snate@binkert.org return out; 6707455Snate@binkert.org} 6717455Snate@binkert.org 6727039Snate@binkert.orgvoid 6737039Snate@binkert.orgSequencer::print(ostream& out) const 6747039Snate@binkert.org{ 6757039Snate@binkert.org out << "[Sequencer: " << m_version 6767039Snate@binkert.org << ", outstanding requests: " << m_outstanding_count 6777039Snate@binkert.org << ", read request table: " << m_readRequestTable 6787039Snate@binkert.org << ", write request table: " << m_writeRequestTable 6797039Snate@binkert.org << "]"; 6807039Snate@binkert.org} 6817039Snate@binkert.org 6827039Snate@binkert.org// this can be called from setState whenever coherence permissions are 6837039Snate@binkert.org// upgraded when invoked, coherence violations will be checked for the 6847039Snate@binkert.org// given block 6857039Snate@binkert.orgvoid 68611025Snilay@cs.wisc.eduSequencer::checkCoherence(Addr addr) 6877039Snate@binkert.org{ 6886145Snate@binkert.org} 6898717Snilay@cs.wisc.edu 6908717Snilay@cs.wisc.eduvoid 6919104Shestness@cs.utexas.eduSequencer::recordRequestType(SequencerRequestType requestType) { 6929104Shestness@cs.utexas.edu DPRINTF(RubyStats, "Recorded statistic: %s\n", 6939104Shestness@cs.utexas.edu SequencerRequestType_to_string(requestType)); 6949104Shestness@cs.utexas.edu} 6959104Shestness@cs.utexas.edu 6969104Shestness@cs.utexas.edu 6979104Shestness@cs.utexas.eduvoid 69811025Snilay@cs.wisc.eduSequencer::evictionCallback(Addr address) 6998717Snilay@cs.wisc.edu{ 7008717Snilay@cs.wisc.edu ruby_eviction_callback(address); 7018717Snilay@cs.wisc.edu} 70210012Snilay@cs.wisc.edu 70310012Snilay@cs.wisc.eduvoid 70410012Snilay@cs.wisc.eduSequencer::regStats() 70510012Snilay@cs.wisc.edu{ 70611523Sdavid.guillen@arm.com RubyPort::regStats(); 70711523Sdavid.guillen@arm.com 70810012Snilay@cs.wisc.edu m_store_waiting_on_load 70910012Snilay@cs.wisc.edu .name(name() + ".store_waiting_on_load") 71010012Snilay@cs.wisc.edu .desc("Number of times a store aliased with a pending load") 71110012Snilay@cs.wisc.edu .flags(Stats::nozero); 71210012Snilay@cs.wisc.edu m_store_waiting_on_store 71310012Snilay@cs.wisc.edu .name(name() + ".store_waiting_on_store") 71410012Snilay@cs.wisc.edu .desc("Number of times a store aliased with a pending store") 71510012Snilay@cs.wisc.edu .flags(Stats::nozero); 71610012Snilay@cs.wisc.edu m_load_waiting_on_load 71710012Snilay@cs.wisc.edu .name(name() + ".load_waiting_on_load") 71810012Snilay@cs.wisc.edu .desc("Number of times a load aliased with a pending load") 71910012Snilay@cs.wisc.edu .flags(Stats::nozero); 72010012Snilay@cs.wisc.edu m_load_waiting_on_store 72110012Snilay@cs.wisc.edu .name(name() + ".load_waiting_on_store") 72210012Snilay@cs.wisc.edu .desc("Number of times a load aliased with a pending store") 72310012Snilay@cs.wisc.edu .flags(Stats::nozero); 72410012Snilay@cs.wisc.edu 72510012Snilay@cs.wisc.edu // These statistical variables are not for display. 72610012Snilay@cs.wisc.edu // The profiler will collate these across different 72710012Snilay@cs.wisc.edu // sequencers and display those collated statistics. 72810012Snilay@cs.wisc.edu m_outstandReqHist.init(10); 72910012Snilay@cs.wisc.edu m_latencyHist.init(10); 73010012Snilay@cs.wisc.edu m_hitLatencyHist.init(10); 73110012Snilay@cs.wisc.edu m_missLatencyHist.init(10); 73210012Snilay@cs.wisc.edu 73310012Snilay@cs.wisc.edu for (int i = 0; i < RubyRequestType_NUM; i++) { 73410012Snilay@cs.wisc.edu m_typeLatencyHist.push_back(new Stats::Histogram()); 73510012Snilay@cs.wisc.edu m_typeLatencyHist[i]->init(10); 73610012Snilay@cs.wisc.edu 73710012Snilay@cs.wisc.edu m_hitTypeLatencyHist.push_back(new Stats::Histogram()); 73810012Snilay@cs.wisc.edu m_hitTypeLatencyHist[i]->init(10); 73910012Snilay@cs.wisc.edu 74010012Snilay@cs.wisc.edu m_missTypeLatencyHist.push_back(new Stats::Histogram()); 74110012Snilay@cs.wisc.edu m_missTypeLatencyHist[i]->init(10); 74210012Snilay@cs.wisc.edu } 74310012Snilay@cs.wisc.edu 74410012Snilay@cs.wisc.edu for (int i = 0; i < MachineType_NUM; i++) { 74510012Snilay@cs.wisc.edu m_hitMachLatencyHist.push_back(new Stats::Histogram()); 74610012Snilay@cs.wisc.edu m_hitMachLatencyHist[i]->init(10); 74710012Snilay@cs.wisc.edu 74810012Snilay@cs.wisc.edu m_missMachLatencyHist.push_back(new Stats::Histogram()); 74910012Snilay@cs.wisc.edu m_missMachLatencyHist[i]->init(10); 75010012Snilay@cs.wisc.edu 75110012Snilay@cs.wisc.edu m_IssueToInitialDelayHist.push_back(new Stats::Histogram()); 75210012Snilay@cs.wisc.edu m_IssueToInitialDelayHist[i]->init(10); 75310012Snilay@cs.wisc.edu 75410012Snilay@cs.wisc.edu m_InitialToForwardDelayHist.push_back(new Stats::Histogram()); 75510012Snilay@cs.wisc.edu m_InitialToForwardDelayHist[i]->init(10); 75610012Snilay@cs.wisc.edu 75710012Snilay@cs.wisc.edu m_ForwardToFirstResponseDelayHist.push_back(new Stats::Histogram()); 75810012Snilay@cs.wisc.edu m_ForwardToFirstResponseDelayHist[i]->init(10); 75910012Snilay@cs.wisc.edu 76010012Snilay@cs.wisc.edu m_FirstResponseToCompletionDelayHist.push_back(new Stats::Histogram()); 76110012Snilay@cs.wisc.edu m_FirstResponseToCompletionDelayHist[i]->init(10); 76210012Snilay@cs.wisc.edu } 76310012Snilay@cs.wisc.edu 76410012Snilay@cs.wisc.edu for (int i = 0; i < RubyRequestType_NUM; i++) { 76510012Snilay@cs.wisc.edu m_hitTypeMachLatencyHist.push_back(std::vector<Stats::Histogram *>()); 76610012Snilay@cs.wisc.edu m_missTypeMachLatencyHist.push_back(std::vector<Stats::Histogram *>()); 76710012Snilay@cs.wisc.edu 76810012Snilay@cs.wisc.edu for (int j = 0; j < MachineType_NUM; j++) { 76910012Snilay@cs.wisc.edu m_hitTypeMachLatencyHist[i].push_back(new Stats::Histogram()); 77010012Snilay@cs.wisc.edu m_hitTypeMachLatencyHist[i][j]->init(10); 77110012Snilay@cs.wisc.edu 77210012Snilay@cs.wisc.edu m_missTypeMachLatencyHist[i].push_back(new Stats::Histogram()); 77310012Snilay@cs.wisc.edu m_missTypeMachLatencyHist[i][j]->init(10); 77410012Snilay@cs.wisc.edu } 77510012Snilay@cs.wisc.edu } 77610012Snilay@cs.wisc.edu} 777