Searched hist:2010 (Results 376 - 400 of 929) sorted by relevance

<<11121314151617181920>>

/gem5/src/arch/x86/
H A Dvtophys.hhdiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
/gem5/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/
H A Dsave_and_restore_state.pydiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/
H A Djump.pydiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
/gem5/src/mem/slicc/ast/
H A DEnumDeclAST.pydiff 7055:4e24742201d7 Fri Apr 02 14:20:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get "using namespace" out of headers
In addition to obvious changes, this required a slight change to the slicc
grammar to allow types with :: in them. Otherwise slicc barfs on std::string
which we need for the headers that slicc generates.
/gem5/src/arch/x86/isa/insts/general_purpose/
H A Dsystem_calls.pydiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
/gem5/src/arch/x86/regs/
H A Dint.hh7629:0f0c231e3e97 Mon Aug 23 19:14:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> X86: Create a directory for files that define register indexes.

This is to help tidy up arch/x86. These files should not be used external to
the ISA.
/gem5/src/python/m5/util/
H A Dattrdict.pydiff 7459:da32c2b05648 Tue Jun 15 02:24:00 EDT 2010 Nathan Binkert <nate@binkert.org> util: clean up attrdict and import multiattrdict into m5.util
/gem5/src/arch/arm/isa/templates/
H A Dmult.isa7159:2d7f1528f2d0 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Add templates for multiply instructions.
/gem5/src/cpu/testers/directedtest/
H A DDirectedGenerator.cc7632:acf43d6bbc18 Tue Aug 24 03:07:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> testers: move testers to a new directory

This patch moves the testers to a new subdirectory under src/cpu and includes
the necessary fixes to work with latest m5 initialization patches.
H A DSeriesRequestGenerator.hh7632:acf43d6bbc18 Tue Aug 24 03:07:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> testers: move testers to a new directory

This patch moves the testers to a new subdirectory under src/cpu and includes
the necessary fixes to work with latest m5 initialization patches.
H A DInvalidateGenerator.hh7632:acf43d6bbc18 Tue Aug 24 03:07:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> testers: move testers to a new directory

This patch moves the testers to a new subdirectory under src/cpu and includes
the necessary fixes to work with latest m5 initialization patches.
/gem5/src/python/m5/
H A Dcore.pydiff 7527:fe90827a663f Tue Aug 17 08:08:00 EDT 2010 Steve Reinhardt <steve.reinhardt@amd.com> sim: move iterating over SimObjects into Python.
/gem5/src/arch/x86/bios/
H A De820.ccdiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
/gem5/src/mem/ruby/slicc_interface/
H A DRubySlicc_ComponentMapping.hhdiff 7805:f249937228b5 Thu Dec 23 00:15:00 EST 2010 Nilay Vaish<nilay@cs.wisc.edu> This patch removes the WARN_* and ERROR_* from src/mem/ruby/common/Debug.hh file. These statements have been replaced with warn(), panic() and fatal() defined in src/base/misc.hh
diff 7039:bc0b6ea676b5 Mon Mar 22 21:43:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: style pass
diff 6926:775342cda4db Fri Jan 29 23:29:00 EST 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: removed last level cache support

Removed the last level cache support and MOESI_hammer's dependency on it.
Replaces the LLC support with the more generic MachineType count.
diff 6862:3d308cbd1657 Tue Jan 19 16:48:00 EST 2010 Derek Hower <drh5@cs.wisc.edu> merge
/gem5/src/arch/x86/isa/insts/simd64/integer/data_transfer/
H A Dmove_non_temporal.pydiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
/gem5/src/arch/x86/isa/insts/simd128/integer/data_transfer/
H A Dmove_non_temporal.pydiff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
/gem5/src/arch/arm/
H A Dintregs.hhdiff 7643:775ccd204013 Wed Aug 25 20:10:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Seperate out the renamable bits in the FPSCR.
diff 7310:239ab4e0c7d4 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Allow flattening into any mode.
diff 7171:75996fe47db8 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Eliminate the unused rhi and rlo operands.
/gem5/src/mem/slicc/symbols/
H A DFunc.pydiff 7055:4e24742201d7 Fri Apr 02 14:20:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get "using namespace" out of headers
In addition to obvious changes, this required a slight change to the slicc
grammar to allow types with :: in them. Otherwise slicc barfs on std::string
which we need for the headers that slicc generates.
diff 7007:79413d1ec307 Fri Mar 12 21:42:00 EST 2010 Nathan Binkert <nate@binkert.org> slicc: Change the code generation so that the generated code is easier to read
diff 6999:f226c098c393 Wed Mar 10 19:22:00 EST 2010 Nathan Binkert <nate@binkert.org> slicc: have a central mechanism for creating a code_formatter.
This makes it easier to add global variables like protocol
H A DStateMachine.pydiff 7805:f249937228b5 Thu Dec 23 00:15:00 EST 2010 Nilay Vaish<nilay@cs.wisc.edu> This patch removes the WARN_* and ERROR_* from src/mem/ruby/common/Debug.hh file. These statements have been replaced with warn(), panic() and fatal() defined in src/base/misc.hh
diff 7780:42da07116e12 Wed Dec 01 14:30:00 EST 2010 Nilay Vaish <nilay@cs.wisc.edu> ruby: Converted old ruby debug calls to M5 debug calls

This patch developed by Nilay Vaish converts all the old GEMS-style ruby
debug calls to the appropriate M5 debug calls.
diff 7672:d609cd948ca0 Thu Sep 09 17:15:00 EDT 2010 Nathan Binkert <nate@binkert.org> code_formatter: make it easier to insert whitespace
a newline by just doing "code()". indent() and dedent() now take a
"count" parameter to indent/dedent multiple levels.
diff 7567:238f99c9f441 Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Stall and wait input messages instead of recycling

This patch allows messages to be stalled in their input buffers and wait
until a corresponding address changes state. In order to make this work,
all in_ports must be ranked in order of dependence and those in_ports that
may unblock an address, must wake up the stalled messages. Alot of this
complexity is handled in slicc and the specification files simply
annotate the in_ports.
diff 7566:6919df046bba Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Recycle latency fix for hammer

Patch allows each individual message buffer to have different recycle latencies
and allows the overall recycle latency to be specified at the cmd line. The
patch also adds profiling info to make sure no one processor's requests are
recycled too much.
diff 7542:49327b849c7f Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> slicc: Consolidated the protocol stats printing

Created a separate ProfileDumper that consolidates the generated stats for
each controller of a certain type.
diff 7454:3a3e8e8cce1b Fri Jun 11 02:17:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get rid of Vector and use STL
add a couple of helper functions to base for deleteing all pointers in
a container and outputting containers to a stream
diff 7056:b66b558578bd Fri Apr 02 14:20:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get rid of gems_common/util.hh and .cc and use stuff in src/base
diff 7055:4e24742201d7 Fri Apr 02 14:20:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get "using namespace" out of headers
In addition to obvious changes, this required a slight change to the slicc
grammar to allow types with :: in them. Otherwise slicc barfs on std::string
which we need for the headers that slicc generates.
diff 7025:9adf5b0ccc79 Mon Mar 22 00:22:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Ruby support for sparse memory

The patch includes direct support for the MI example protocol.
/gem5/src/arch/x86/insts/
H A Dmicroregop.ccdiff 7676:92274350b953 Fri Sep 10 17:58:00 EDT 2010 Nathan Binkert <nate@binkert.org> style: fix sorting of includes and whitespace in some files
diff 7629:0f0c231e3e97 Mon Aug 23 19:14:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> X86: Create a directory for files that define register indexes.

This is to help tidy up arch/x86. These files should not be used external to
the ISA.
diff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
H A Dmicroldstop.hhdiff 7678:f19b6a3a8cec Mon Sep 13 22:26:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.

Also move the "Fault" reference counted pointer type into a separate file,
sim/fault.hh. It would be better to name this less similarly to sim/faults.hh
to reduce confusion, but fault.hh matches the name of the type. We could change
Fault to FaultPtr to match other pointer types, and then changing the name of
the file would make more sense.
diff 7620:3d8a23caa1ef Mon Aug 23 12:44:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> X86: Consolidate extra microop flags into one parameter.

This single parameter replaces the collection of bools that set up various
flavors of microops. A flag parameter also allows other flags to be set like
the serialize before/after flags, etc., without having to change the
constructor.
diff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly
/gem5/src/dev/
H A Dintel_8254_timer.ccdiff 7683:f81f5f27592b Thu Sep 16 23:24:00 EDT 2010 Steve Reinhardt <steve.reinhardt@amd.com> devices: undo cset 017baf09599f that added timer drain functions.
It's not the right fix for the checkpoint deadlock problem
Brad was having, and creates another bug where the system can
deadlock on restore. Brad can't reproduce the original bug
right now, so we'll wait until it arises again and then try
to fix it the right way then.
diff 7559:017baf09599f Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> devices: Fixed periodic interrupts to work with draining

Added drain functions to the RTC and 8254 timer so that periodic interrupts
stop when the system is draining. This patch is needed to checkpoint in
timing mode. Otherwise under certain situations, the event queue will never
be completely empty.
diff 7064:586b0e3a12b3 Thu Apr 15 19:24:00 EDT 2010 Nathan Binkert <nate@binkert.org> tick: rename Clock namespace to SimClock
H A Dmc146818.hhdiff 7683:f81f5f27592b Thu Sep 16 23:24:00 EDT 2010 Steve Reinhardt <steve.reinhardt@amd.com> devices: undo cset 017baf09599f that added timer drain functions.
It's not the right fix for the checkpoint deadlock problem
Brad was having, and creates another bug where the system can
deadlock on restore. Brad can't reproduce the original bug
right now, so we'll wait until it arises again and then try
to fix it the right way then.
diff 7559:017baf09599f Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> devices: Fixed periodic interrupts to work with draining

Added drain functions to the RTC and 8254 timer so that periodic interrupts
stop when the system is draining. This patch is needed to checkpoint in
timing mode. Otherwise under certain situations, the event queue will never
be completely empty.
diff 7064:586b0e3a12b3 Thu Apr 15 19:24:00 EDT 2010 Nathan Binkert <nate@binkert.org> tick: rename Clock namespace to SimClock
/gem5/src/cpu/
H A Dtranslation.hhdiff 7678:f19b6a3a8cec Mon Sep 13 22:26:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.

Also move the "Fault" reference counted pointer type into a separate file,
sim/fault.hh. It would be better to name this less similarly to sim/faults.hh
to reduce confusion, but fault.hh matches the name of the type. We could change
Fault to FaultPtr to match other pointer types, and then changing the name of
the file would make more sense.
diff 7049:a06e95c99294 Wed Mar 24 20:43:00 EDT 2010 Timothy M. Jones <tjones1@inf.ed.ac.uk> CPU: Added comments to address translation classes.
6973:a123bd350935 Fri Feb 12 14:53:00 EST 2010 Timothy M. Jones <tjones1@inf.ed.ac.uk> BaseDynInst: Make the TLB translation timing instead of atomic.

This initiates a timing translation and passes the read or write on to the
processor before waiting for it to finish. Once the translation is finished,
the instruction's state is updated via the 'finish' function. A new
DataTranslation class is created to handle this.

The idea is taken from the implementation of timing translations in
TimingSimpleCPU by Gabe Black. This patch also separates out the timing
translations from this CPU and uses the new DataTranslation class.
/gem5/configs/ruby/
H A DMOESI_CMP_token.pydiff 7633:d8112aa18a1b Tue Aug 24 16:20:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> config: fixed ruby dma device connections
diff 7564:3559d47839a1 Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: added probe filter support to hammer
diff 7561:02a9a597fce4 Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Disable migratory sharing for token and hammer

This patch allows one to disable migratory sharing for those cache blocks that
are accessed by atomic requests. While the implementations are different
between the token and hammer protocols, the motivation is the same. For
Alpha, LLSC semantics expect that normal loads do not unlock cache blocks that
have been locked by LL accesses. Therefore, locked blocks should not transfer
write permissions when responding to these load requests. Instead, only they
only transfer read permissions so that the subsequent SC access can possibly
succeed.
diff 7551:b10ee98aea91 Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Reduced ruby latencies

The previous slower ruby latencies created a mismatch between the faster M5
cpu models and the much slower ruby memory system. Specifically smp
interrupts were much slower and infrequent, as well as cpus moving in and out
of spin locks. The result was many cpus were idle for large periods of time.

These changes fix the latency mismatch.
diff 7544:90c5eb6a5e66 Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> memtest: Memtester support for DMA

This patch adds DMA testing to the Memtester and is inherits many changes from
Polina's old tester_dma_extension patch. Since Ruby does not work in atomic
mode, the atomic mode options are removed.
diff 7541:1e1f63dfd130 Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> config: Improve ruby simobject names

This patch attaches ruby objects to the system before the topology is
created so that their simobject names read their meaningful variable
names instead of their topology name.
diff 7539:9ca6602c5345 Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: added token broadcast config params to cmd options
diff 7538:5691b9dd51f4 Fri Aug 20 14:44:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> config: reorganized how ruby specifies command-line options
diff 7535:7f8213cb2337 Fri Aug 20 14:41:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> config: moved python protocol config files

Moved the python protocol config files back to their original location to avoid
addToPath calls.
diff 7032:9f938aea1942 Mon Mar 22 00:22:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Reorganized Ruby topology and protocol files

Completed in 118 milliseconds

<<11121314151617181920>>