style: [patch 1/22] use /r/3648/ to reorganize includes

style: fix missing spaces in control statements

Result of running 'hg m5style --skip-all --fix-control -a'.

trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help

X86: Put the result used for flags in an intermediate variable.

Using the destination register directly causes the ISA parser to treat it as a
source even if none of the original bits are used.

style: fix sorting of includes and whitespace in some files

X86: Create a directory for files that define register indexes.

This is to help tidy up arch/x86. These files should not be used external to
the ISA.

copyright: Change HP copyright on x86 code to be more friendly

X86: Fix how the parity flag is computed.
It's only for the lowest order byte, and I had the polarity wrong.

X86: Set up a named constant for the "fold bit" for int register indices.

X86: Calculate flags based on the actual result.

X86: Get rid of stray Sparc DPRINTF

X86: Move the fp microops to their own file with their own base classes in C++ and python.

X86: Fix how ECF is computed in genFlags, and get rid of some duplicate code.

X86: Added some missing parenthesis in the condition code calculation function.

X86: Implemented and hooked in SCAS (scan string)
Fixed the asz assembler symbol.
Adjusted the condion checks to have appropriate options.
Implemented the SCAS microcode.
Attached SCAS into the decoder.

X86: Make disassembly use the final register index. Add bits to indicate whether or not register indexes should be "folded".

Fixed width parameter and provided a parameter to flip the carry bit on subtract.

Make disassembled x86 register indices reflect their size.
This doesn't handle high byte register accesses. It also highlights the fact that address size isn't actually being calculated, and that the size a microop uses needs to be overridable from the microassembly.

Add in support for condition code flags.
Some microops can set the condition codes, and some of them can be predicated on them. Some of the codes aren't implemented because it was unclear from the AMD patent what they actually did. They are used with string instructions, but they use variables IP, DTF, and SSTF which don't appear to be documented.

Pull some hard coded base classes out of the isa description.