Searched hist:2010 (Results 326 - 350 of 929) sorted by relevance
/gem5/src/cpu/testers/rubytest/ | ||
H A D | CheckTable.hh | 7632:acf43d6bbc18 Tue Aug 24 03:07:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> testers: move testers to a new directory This patch moves the testers to a new subdirectory under src/cpu and includes the necessary fixes to work with latest m5 initialization patches. |
/gem5/src/dev/mips/ | ||
H A D | SConscript | diff 7709:fc12f4d657f0 Mon Oct 18 02:15:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> MIPS: Get rid of the backdoor device copy/pasted from and only used in Alpha. |
/gem5/src/mem/ruby/common/ | ||
H A D | NetDest.hh | diff 7780:42da07116e12 Wed Dec 01 14:30:00 EST 2010 Nilay Vaish <nilay@cs.wisc.edu> ruby: Converted old ruby debug calls to M5 debug calls This patch developed by Nilay Vaish converts all the old GEMS-style ruby debug calls to the appropriate M5 debug calls. diff 7454:3a3e8e8cce1b Fri Jun 11 02:17:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get rid of Vector and use STL add a couple of helper functions to base for deleteing all pointers in a container and outputting containers to a stream diff 7055:4e24742201d7 Fri Apr 02 14:20:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get "using namespace" out of headers In addition to obvious changes, this required a slight change to the slicc grammar to allow types with :: in them. Otherwise slicc barfs on std::string which we need for the headers that slicc generates. diff 7039:bc0b6ea676b5 Mon Mar 22 21:43:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: style pass |
H A D | DataBlock.hh | diff 7454:3a3e8e8cce1b Fri Jun 11 02:17:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get rid of Vector and use STL add a couple of helper functions to base for deleteing all pointers in a container and outputting containers to a stream diff 7039:bc0b6ea676b5 Mon Mar 22 21:43:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: style pass diff 7002:48a19d52d939 Wed Mar 10 21:33:00 EST 2010 Nathan Binkert <nate@binkert.org> ruby: get rid of std-includes.hh Do not use "using namespace std;" in headers Include header files as needed diff 6971:12cfde8f819b Wed Feb 10 19:40:00 EST 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: fixed data block assignment fix Fixed data block assignment to not delete if not internally allocated. |
H A D | Consumer.hh | diff 7039:bc0b6ea676b5 Mon Mar 22 21:43:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: style pass diff 7021:0b3c02da71b3 Mon Mar 22 00:22:00 EDT 2010 Tushar Krishna <tushar@csail.mit.edu> ruby: Fix multiple wakeups in Ruby Eventqueue Fix bug in Ruby Event queue to avoid multiple wakeups of same consumer in same cycle diff 7002:48a19d52d939 Wed Mar 10 21:33:00 EST 2010 Nathan Binkert <nate@binkert.org> ruby: get rid of std-includes.hh Do not use "using namespace std;" in headers Include header files as needed diff 6891:77451885bb00 Fri Jan 29 23:29:00 EST 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Removed out_link_vec from Consumer Removed the out_line_vec data structure from the Consumer. I'm not sure what this did before, but currently it has no usefulness. |
/gem5/src/arch/arm/isa/formats/ | ||
H A D | pred.isa | diff 7422:feddb9077def Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Decode to specialized conditional/unconditional versions of instructions. This is to avoid condition code based dependences from effectively serializing instructions when the instruction doesn't actually use them. diff 7143:c81f34f9e075 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Get rid of obsoleted predicated inst formats, etc. diff 7133:4a1af4580b7d Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Move the templates for predicated instructions into a separate file. This allows the templates to all be available at the same time before any of the formats, etc. This breaks an artificial circular dependence. diff 7110:7d27bd3e7ffb Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Add a base class for 32 bit thumb data processing immediate instructions. |
/gem5/src/cpu/testers/directedtest/ | ||
H A D | DirectedGenerator.hh | 7632:acf43d6bbc18 Tue Aug 24 03:07:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> testers: move testers to a new directory This patch moves the testers to a new subdirectory under src/cpu and includes the necessary fixes to work with latest m5 initialization patches. |
/gem5/src/arch/sparc/isa/formats/ | ||
H A D | formats.isa | diff 7741:340b6f01d69b Thu Nov 11 05:03:00 EST 2010 Gabe Black <gblack@eecs.umich.edu> SPARC: Clean up some historical style issues. |
/gem5/src/arch/x86/isa/insts/x87/control/ | ||
H A D | save_and_restore_x87_environment.py | diff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly |
/gem5/src/arch/x86/isa/insts/general_purpose/ | ||
H A D | cache_and_memory_management.py | diff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly |
/gem5/src/arch/arm/isa/templates/ | ||
H A D | vfp.isa | diff 7644:62873d5c2bfc Wed Aug 25 20:10:00 EDT 2010 Ali Saidi <ali.saidi@arm.com> ARM: Fix VFP enabled checks for mem instructions diff 7640:5286a8a469c5 Wed Aug 25 20:10:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Implement CPACR register and return Undefined Instruction when FP access is disabled. diff 7396:53454ef35b46 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Clean up the implementation of the VFP instructions. 7375:7095d84ffb36 Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Introduce new VFP base classes that are optionally microops. |
/gem5/src/cpu/o3/ | ||
H A D | deriv.cc | diff 9480:d059f8a95a42 Thu Jan 24 01:28:00 EST 2013 Nilay Vaish <nilay@cs.wisc.edu>, Timothy Jones <timothy.jones@cl.cam.ac.uk> branch predictor: move out of o3 and inorder cpus This patch moves the branch predictor files in the o3 and inorder directories to src/cpu/pred. This allows sharing the branch predictor across different cpu models. This patch was originally posted by Timothy Jones in July 2010 but never made it to the repository. |
/gem5/util/ | ||
H A D | checkpoint-tester.py | 7489:26cd0ad262d0 Tue Jul 06 00:39:00 EDT 2010 Steve Reinhardt <steve.reinhardt@amd.com> util: add a script for testing checkpointing See comments in util/checkpoint-tester.py for details. |
/gem5/src/arch/x86/linux/ | ||
H A D | system.cc | diff 7737:f4362ffd810f Mon Nov 08 03:43:00 EST 2010 Gabe Black <gblack@eecs.umich.edu> X86: Fix X86_FS compilation. diff 7629:0f0c231e3e97 Mon Aug 23 19:14:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> X86: Create a directory for files that define register indexes. This is to help tidy up arch/x86. These files should not be used external to the ISA. diff 7532:3f6413fc37a2 Tue Aug 17 08:17:00 EDT 2010 Steve Reinhardt <steve.reinhardt@amd.com> sim: revamp unserialization procedure Replace direct call to unserialize() on each SimObject with a pair of calls for better control over initialization in both ckpt and non-ckpt cases. If restoring from a checkpoint, loadState(ckpt) is called on each SimObject. The default implementation simply calls unserialize() if there is a corresponding checkpoint section, so we get backward compatibility for existing objects. However, objects can override loadState() to get other behaviors, e.g., doing other programmed initializations after unserialize(), or complaining if no checkpoint section is found. (Note that the default warning for a missing checkpoint section is now gone.) If not restoring from a checkpoint, we call the new initState() method on each SimObject instead. This provides a hook for state initializations that are only required when *not* restoring from a checkpoint. Given this new framework, do some cleanup of LiveProcess subclasses and X86System, which were (in some cases) emulating initState() behavior in startup via a local flag or (in other cases) erroneously doing initializations in startup() that clobbered state loaded earlier by unserialize(). diff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly |
/gem5/src/mem/protocol/ | ||
H A D | SConscript | diff 6999:f226c098c393 Wed Mar 10 19:22:00 EST 2010 Nathan Binkert <nate@binkert.org> slicc: have a central mechanism for creating a code_formatter. This makes it easier to add global variables like protocol diff 6925:a27441e3d106 Fri Jan 29 23:29:00 EST 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Added a Scons option to prevent HTML file creation diff 6878:c3a3c09af8be Fri Jan 29 23:29:00 EST 2010 Steve Reinhardt <steve.reinhardt@amd.com> scons: ignore blank lines in .slicc files diff 6877:2a1a3d916ca8 Fri Jan 29 23:29:00 EST 2010 Steve Reinhardt <steve.reinhardt@amd.com> ruby: Make SLICC-generated objects SimObjects. Also add SLICC support for state-machine parameter defaults (passed through to Python as SimObject Param defaults). |
/gem5/src/mem/ruby/profiler/ | ||
H A D | AddressProfiler.hh | diff 7455:586f99bf0dc4 Fri Jun 11 02:17:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get rid of the Map class diff 7055:4e24742201d7 Fri Apr 02 14:20:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get "using namespace" out of headers In addition to obvious changes, this required a slight change to the slicc grammar to allow types with :: in them. Otherwise slicc barfs on std::string which we need for the headers that slicc generates. diff 7048:2ab58c54de63 Wed Mar 24 01:49:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: continue style pass diff 6896:649e40aad897 Fri Jan 29 23:29:00 EST 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Removed RubySystem::getNumberOfSequencers removed the static function RubySystem::getNumberOfSequencers and replaced it with a python config variable |
H A D | AccessTraceForAddress.hh | diff 7456:8b9be6e12c9b Fri Jun 11 02:17:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get rid of PrioHeap and use STL One big difference is that PrioHeap puts the smallest element at the top of the heap, whereas stl puts the largest element on top, so I changed all comparisons so they did the right thing. Some usage of PrioHeap was simply changed to a std::vector, using sort at the right time, other usage had me just use the various heap functions in the stl. diff 7455:586f99bf0dc4 Fri Jun 11 02:17:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get rid of the Map class diff 7055:4e24742201d7 Fri Apr 02 14:20:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get "using namespace" out of headers In addition to obvious changes, this required a slight change to the slicc grammar to allow types with :: in them. Otherwise slicc barfs on std::string which we need for the headers that slicc generates. diff 7048:2ab58c54de63 Wed Mar 24 01:49:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: continue style pass |
H A D | Profiler.cc | diff 7565:9fc3475e8175 Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> MOESI_hammer: break down miss latency stalled cycles This patch tracks the number of cycles a transaction is delayed at different points of the request-forward-response loop. diff 7546:84e8f914b3b8 Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Reincarnated the responding machine profiling This patch adds back to ruby the capability to understand the response time for messages that hit in different levels of the cache heirarchy. Specifically add support for the MI_example, MOESI_hammer, and MOESI_CMP_token protocols. diff 7456:8b9be6e12c9b Fri Jun 11 02:17:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get rid of PrioHeap and use STL One big difference is that PrioHeap puts the smallest element at the top of the heap, whereas stl puts the largest element on top, so I changed all comparisons so they did the right thing. Some usage of PrioHeap was simply changed to a std::vector, using sort at the right time, other usage had me just use the various heap functions in the stl. diff 7455:586f99bf0dc4 Fri Jun 11 02:17:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get rid of the Map class diff 7454:3a3e8e8cce1b Fri Jun 11 02:17:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get rid of Vector and use STL add a couple of helper functions to base for deleteing all pointers in a container and outputting containers to a stream diff 7056:b66b558578bd Fri Apr 02 14:20:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get rid of gems_common/util.hh and .cc and use stuff in src/base diff 7055:4e24742201d7 Fri Apr 02 14:20:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get "using namespace" out of headers In addition to obvious changes, this required a slight change to the slicc grammar to allow types with :: in them. Otherwise slicc barfs on std::string which we need for the headers that slicc generates. diff 7054:7d6862b80049 Wed Mar 31 19:56:00 EDT 2010 Nathan Binkert <nate@binkert.org> style: another ruby style pass diff 7048:2ab58c54de63 Wed Mar 24 01:49:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: continue style pass diff 7010:c769c45253c9 Mon Mar 22 00:22:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Removed deprecated stats from the main profiler |
/gem5/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/ | ||
H A D | move_non_temporal.py | diff 7087:fb8d5786ff30 Mon May 24 01:44:00 EDT 2010 Nathan Binkert <nate@binkert.org> copyright: Change HP copyright on x86 code to be more friendly |
/gem5/src/arch/arm/ | ||
H A D | isa_traits.hh | diff 7799:5d0f62927d75 Mon Dec 20 16:24:00 EST 2010 Gabe Black <gblack@eecs.umich.edu> Style: Replace some tabs with spaces. diff 7720:65d338a8dba4 Sun Oct 31 03:07:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC. diff 7692:8173327c9c65 Fri Oct 01 17:02:00 EDT 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Clean up use of TBit and JBit. Rather tha constantly using ULL(1) << PcXBitShift define those directly. Additionally, add some helper functions to further clean up the code. diff 7654:7447a92d1ad5 Wed Aug 25 20:10:00 EDT 2010 Min Kyu Jeong <minkyu.jeong@arm.com> ARM: Support unaligned memory access. Without this flag set, page-crossing requests were not split into two mem request. Depending on the alignment bit in the SCTLR, misaligned access could raise a fault. However it seems unnecessary to implement that. diff 7651:84a44eb3ccb8 Wed Aug 25 20:10:00 EDT 2010 William Wang <William.Wang@ARM.com> ARM: Remove ALPHA KSeg functions. These were erronously copied years ago into the ARM directory. diff 7580:6f77f379a594 Mon Aug 23 12:18:00 EDT 2010 Ali Saidi <Ali.Saidi@arm.com> Loader: Make the load address mask be a parameter of the system rather than a constant. This allows one two different OS requirements for the same ISA to be handled. Some OSes are compiled for a virtual address and need to be loaded into physical memory that starts at address 0, while other bare metal tools generate images that start at address 0. diff 7400:f6c9b27c4dbe Wed Jun 02 01:58:00 EDT 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Implement ARM CPU interrupts diff 7349:8b4564729c81 Wed Jun 02 01:58:00 EDT 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Move PC mode bits around so they can be used for exectrace diff 7158:195780d97b1b Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Add base classes for multiply instructions. diff 6974:4d4903a3e7c5 Fri Feb 12 14:53:00 EST 2010 Timothy M. Jones <tjones1@inf.ed.ac.uk> O3PCU: Split loads and stores that cross cache line boundaries. When each load or store is sent to the LSQ, we check whether it will cross a cache line boundary and, if so, split it in two. This creates two TLB translations and two memory requests. Care has to be taken if the first packet of a split load is sent but the second blocks the cache. Similarly, for a store, if the first packet cannot be sent, we must store the second one somewhere to retry later. This modifies the LSQSenderState class to record both packets in a split load or store. Finally, a new const variable, HasUnalignedMemAcc, is added to each ISA to indicate whether unaligned memory accesses are allowed. This is used throughout the changed code so that compiler can optimise away code dealing with split requests for ISAs that don't need them. |
H A D | table_walker.hh | diff 7748:7bf78d12b359 Mon Nov 15 15:04:00 EST 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add support for switching CPUs diff 7733:08d6a773d1b6 Mon Nov 08 14:58:00 EST 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add checkpointing support diff 7728:cf9db1c47a77 Mon Nov 08 14:58:00 EST 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Don't return the result of a table walk the same cycle it's completed. The L1 cache may have been accessed to provide this data, which confuses it, if it ends up being accesses twice in one cycle. Instead wait 1 tick which will force the timing simple CPU to forward to its next clock cycle when the translation completes. Also prevent multiple outstanding table walks from occuring at once. diff 7694:de057cccee82 Fri Oct 01 17:03:00 EDT 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Implement functional virtual to physical address translation for debugging and program introspection. diff 7678:f19b6a3a8cec Mon Sep 13 22:26:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> Faults: Pass the StaticInst involved, if any, to a Fault's invoke method. Also move the "Fault" reference counted pointer type into a separate file, sim/fault.hh. It would be better to name this less similarly to sim/faults.hh to reduce confusion, but fault.hh matches the name of the type. We could change Fault to FaultPtr to match other pointer types, and then changing the name of the file would make more sense. diff 7653:968302e54850 Wed Aug 25 20:10:00 EDT 2010 Gene WU <gene.wu@arm.com> ARM: Seperate the queues of L1 and L2 walker states. diff 7608:17aabeaa1a8f Mon Aug 23 12:18:00 EDT 2010 Gene Wu <Gene.Wu@arm.com> ARM: Fix Uncachable TLB requests and decoding of xn bit diff 7578:7ea651f34ae6 Mon Aug 23 12:18:00 EDT 2010 Dam Sunwoo <dam.sunwoo@arm.com> ARM: Use a stl queue for the table walker state diff 7439:b4c6b2532bbf Wed Jun 02 01:58:00 EDT 2010 Dam Sunwoo <dam.sunwoo@arm.com> ARM: Allow multiple outstanding TLB walks to queue. diff 7438:8e4b37136330 Wed Jun 02 01:58:00 EDT 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM TLB: Fix bug in memAttrs getting a bogus thread context |
H A D | utility.hh | diff 7752:08e1e28a062a Mon Nov 15 15:04:00 EST 2010 William Wang <William.Wang@arm.com> ARM: Add support for GDB on ARM diff 7751:b12a5700f1fa Mon Nov 15 15:04:00 EST 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Make utility.hh meet style guidelines diff 7748:7bf78d12b359 Mon Nov 15 15:04:00 EST 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add support for switching CPUs diff 7720:65d338a8dba4 Sun Oct 31 03:07:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC. diff 7707:e5b6f1157be3 Sat Oct 16 02:57:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> GetArgument: Rework getArgument so that X86_FS compiles again. When no size is specified for an argument, push the decision about what size to use into the ISA by passing a size of -1. diff 7693:f1db1000d957 Fri Oct 01 17:02:00 EDT 2010 Ali Saidi <Ali.Saidi@ARM.com> Debug: Implement getArgument() and function skipping for ARM. In the process make add skipFuction() to handle isa specific function skipping instead of ifdefs and other ugliness. For almost all ABIs, 64 bit arguments can only start in even registers. Size is now passed to getArgument() so that 32 bit systems can make decisions about register selection for 64 bit arguments. The number argument is now passed by reference because getArgument() will need to change it based on the size of the argument and the current argument number. For ARM, if the argument number is odd and a 64-bit register is requested the number must first be incremented to because all 64 bit arguments are passed in an even argument register. Then the number will be incremented again to access both halves of the argument. diff 7692:8173327c9c65 Fri Oct 01 17:02:00 EDT 2010 Ali Saidi <Ali.Saidi@ARM.com> ARM: Clean up use of TBit and JBit. Rather tha constantly using ULL(1) << PcXBitShift define those directly. Additionally, add some helper functions to further clean up the code. diff 7680:f4eda002333b Tue Sep 14 03:29:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> CPU: Trim unnecessary includes from some common files. This reduces the scope of those includes and makes it less likely for there to be a dependency loop. This also moves the hashing functions associated with ExtMachInst objects to be with the ExtMachInst definitions and out of utility.hh. diff 7678:f19b6a3a8cec Mon Sep 13 22:26:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> Faults: Pass the StaticInst involved, if any, to a Fault's invoke method. Also move the "Fault" reference counted pointer type into a separate file, sim/fault.hh. It would be better to name this less similarly to sim/faults.hh to reduce confusion, but fault.hh matches the name of the type. We could change Fault to FaultPtr to match other pointer types, and then changing the name of the file would make more sense. diff 7666:c1b66fc648e2 Tue Aug 31 12:50:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Get rid of the checkFpEnableFault function in ARM. |
/gem5/src/mem/ruby/system/ | ||
H A D | SConscript | diff 7780:42da07116e12 Wed Dec 01 14:30:00 EST 2010 Nilay Vaish <nilay@cs.wisc.edu> ruby: Converted old ruby debug calls to M5 debug calls This patch developed by Nilay Vaish converts all the old GEMS-style ruby debug calls to the appropriate M5 debug calls. diff 7544:90c5eb6a5e66 Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> memtest: Memtester support for DMA This patch adds DMA testing to the Memtester and is inherits many changes from Polina's old tester_dma_extension patch. Since Ruby does not work in atomic mode, the atomic mode options are removed. diff 7025:9adf5b0ccc79 Mon Mar 22 00:22:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Ruby support for sparse memory The patch includes direct support for the MI example protocol. diff 7023:185ad61a4117 Mon Mar 22 00:22:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Ruby support for LLSC diff 6876:a658c315512c Fri Jan 29 23:29:00 EST 2010 Steve Reinhardt <steve.reinhardt@amd.com> ruby: Convert most Ruby objects to M5 SimObjects. The necessary companion conversion of Ruby objects generated by SLICC are converted to M5 SimObjects in the following patch, so this patch alone does not compile. Conversion of Garnet network models is also handled in a separate patch; that code is temporarily disabled from compiling to allow testing of interim code. |
H A D | Sequencer.hh | diff 7565:9fc3475e8175 Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> MOESI_hammer: break down miss latency stalled cycles This patch tracks the number of cycles a transaction is delayed at different points of the request-forward-response loop. diff 7560:29d5891a96d6 Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Added SC fail indication to trace profiling diff 7550:7d97cec15818 Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: fix ruby llsc support to sync sc outcomes Added support so that ruby can determine the outcome of store conditional operations and reflect that outcome to M5 physical memory and cpus. diff 7546:84e8f914b3b8 Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Reincarnated the responding machine profiling This patch adds back to ruby the capability to understand the response time for messages that hit in different levels of the cache heirarchy. Specifically add support for the MI_example, MOESI_hammer, and MOESI_CMP_token protocols. diff 7455:586f99bf0dc4 Fri Jun 11 02:17:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get rid of the Map class diff 7055:4e24742201d7 Fri Apr 02 14:20:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: get "using namespace" out of headers In addition to obvious changes, this required a slight change to the slicc grammar to allow types with :: in them. Otherwise slicc barfs on std::string which we need for the headers that slicc generates. diff 7039:bc0b6ea676b5 Mon Mar 22 21:43:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: style pass diff 6922:1620cffaa3b6 Fri Jan 29 23:29:00 EST 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Removed static members in RubyPort including hitcallback Removed static members in RubyPort and removed the ruby request unique id. diff 6899:f8057af86bf7 Fri Jan 29 23:29:00 EST 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: added the GEMS ruby tester diff 6886:3137c3d41107 Fri Jan 29 23:29:00 EST 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Converted the sequencer deadlock event to m5 eventq |
/gem5/configs/ruby/ | ||
H A D | Ruby.py | diff 7663:abb78217021f Mon Aug 30 18:26:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> config: fixed numa high bit setting bug diff 7661:b03534522b91 Sun Aug 29 10:02:00 EDT 2010 Nathan Binkert <nate@binkert.org> ruby: None, not none diff 7566:6919df046bba Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Recycle latency fix for hammer Patch allows each individual message buffer to have different recycle latencies and allows the overall recycle latency to be specified at the cmd line. The patch also adds profiling info to make sure no one processor's requests are recycled too much. diff 7563:406e98960def Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: fixed DirectoryMemory's numa_high_bit configuration This fix includes the off-by-one bit selection bug for numa mapping. diff 7557:bd48f4547e77 Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Improved try except blocks in ruby creation Replaced the sys.exit in the try-except blocks with raise so that the python call stack will be printed diff 7555:ccd55d73c75d Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> config: added cmd options to control ruby debug diff 7541:1e1f63dfd130 Fri Aug 20 14:46:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> config: Improve ruby simobject names This patch attaches ruby objects to the system before the topology is created so that their simobject names read their meaningful variable names instead of their topology name. diff 7538:5691b9dd51f4 Fri Aug 20 14:44:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> config: reorganized how ruby specifies command-line options diff 7535:7f8213cb2337 Fri Aug 20 14:41:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> config: moved python protocol config files Moved the python protocol config files back to their original location to avoid addToPath calls. diff 7032:9f938aea1942 Mon Mar 22 00:22:00 EDT 2010 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Reorganized Ruby topology and protocol files |
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