style: remove trailing whitespace

Result of running 'hg m5style --skip-all --fix-white -a'.

ARM: Construct the predicate test register for more instruction programatically.

If one of the condition codes isn't being used in the execution we should only
read it if the instruction might be dependent on it. With the preeceding changes
there are several more cases where we should dynamically pick instead of assuming
as we did before.

ARM: Further break up condition code into NZ, C, V bits.

Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.

ARM: Break up condition codes into normal flags, saturation, and simd.

This change splits out the condcodes from being one monolithic register
into three blocks that are updated independently. This allows CPUs
to not have to do RMW operations on the flags registers for instructions
that don't write all flags.

ARM: Decode to specialized conditional/unconditional versions of instructions.

This is to avoid condition code based dependences from effectively serializing
instructions when the instruction doesn't actually use them.

ARM: Get rid of obsoleted predicated inst formats, etc.

ARM: Move the templates for predicated instructions into a separate file.
This allows the templates to all be available at the same time before any of
the formats, etc. This breaks an artificial circular dependence.

ARM: Add a base class for 32 bit thumb data processing immediate instructions.

ARM: Fix some bugs in the ISA desc and fill out some instructions.

ARM: Split the condition codes out of the CPSR.

This allows those bits to be renamed while allowing the other fields to
control the behavior of the processor.

ARM: Mul and mla ignore the c and v flags, but we were setting them to 1.

ARM: Make DataOps select from a set of ways to set the c and v flags.

ARM: Add defaults for DataOp flag code.

ARM: Get rid of the val2 variable.

ARM: Centralize the declaration of resTemp.

ARM: Add a DataImmOp format similar to DataOp.

ARM: Add a DataOp format so data op definitions can be aggregated.

ARM: Simplify the ISA desc by pulling some classes out of it.

ARM: Make inst bitfields accessible outside of the isa desc.

ARM: Get rid of unnecessary fp_enable_checks.

ARM: Adjust simplify rotate_imm slightly.

ARM: Make the isa parser aware that CPSR is being used.

ARM: Pull some static code out of the isa desc and create miscregs.hh.

arm: add ARM support to M5