Searched hist:2009 (Results 251 - 275 of 951) sorted by relevance

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/gem5/src/arch/x86/isa/
H A Dmicroasm.isadiff 6801:353726c415f4 Sat Dec 19 04:48:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add a common named flag for signed media operations.
diff 6800:335f8b406bb9 Sat Dec 19 04:48:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Create a common flag with a name to indicate high multiplies.
diff 6799:36131e4dfb6e Sat Dec 19 04:47:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Create a common flag with a name to indicate scalar media instructions.
diff 6618:2cd3ce4fa03f Thu Aug 20 03:41:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add microassembler symbols for floating point stack register operands.
diff 6517:584314d07394 Mon Aug 17 21:15:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add microcode assembler symbols for mmx registers.
diff 6457:f964c623723c Wed Aug 05 06:03:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Let microops force folding an index into the high byte of a register.
diff 6345:f9ae7c3a036c Thu Jul 16 12:29:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Take limitted advantage of the compilers type checking for microop operands.
diff 5936:c30088a243ad Wed Feb 25 13:21:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add segmentation checks for ldt related descriptors and selectors.
diff 5930:ec124ac0984b Wed Feb 25 13:20:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Rename oszForPseudoDesc maxOsz to reflect its more general use.
diff 5906:fe94a5f1f229 Wed Feb 25 13:17:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make the microcode assembler recognize r8-r15.
H A Dincludes.isadiff 6570:d7907eaf7419 Mon Aug 17 23:04:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement an integer media addition microop with optional saturation.
diff 6516:b5b420d15a20 Mon Aug 17 21:15:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Set up a media microop framework and create mov2int and mov2fp microops.
diff 6345:f9ae7c3a036c Thu Jul 16 12:29:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Take limitted advantage of the compilers type checking for microop operands.
diff 6336:25635830e33c Thu Jul 09 23:29:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Fold the MiscRegFile all the way into the ISA object.
diff 6329:5d8b91875859 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Add a registers.hh file as an ISA switched header.
This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.
diff 5920:5a9c976270d6 Wed Feb 25 13:19:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement a basic prefetch instruction.
diff 5912:d113f6def227 Wed Feb 25 13:18:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add a flag to force memory accesses to happen at CPL 0.
diff 5789:46c548dbe620 Wed Jan 07 02:55:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Hook in the M5 pseudo insts.
diff 5786:07f635cab026 Wed Jan 07 01:44:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Move the macroop class out of the isa description into C++.
/gem5/src/dev/
H A Dmc146818.ccdiff 6772:788cdecedf9f Wed Nov 18 16:55:00 EST 2009 Brad Beckmann <Brad.Beckmann@amd.com> m5: fixed destructor to deschedule the tickEvent and event
diff 6677:b741b3e7164b Thu Oct 15 18:15:00 EDT 2009 Brad Beckmann <Brad.Beckmann@amd.com> fixed MC146818 checkpointing bug and added isa serialization calls to simple_thread
diff 6621:835a99bdab10 Fri Aug 21 02:09:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> RTC: Make calls to writeData update the RTCs internal representation of time.
diff 6620:ade9a088bb14 Thu Aug 20 03:42:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make the real time clock actually keep track of time.
diff 6617:6d3645f68654 Thu Aug 20 03:40:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Don't insist on binary encoding for the RTC since we implement BCD.
diff 5949:04ed7a1d9904 Wed Feb 25 13:22:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> Devices: Make the RTC device reflect the use of BCD in its status registers.
diff 5813:624566640d7c Sun Jan 25 23:32:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> Dev: Make the RTC device ignore writes to a read only bit.
/gem5/src/arch/arm/linux/
H A Dlinux.hhdiff 6689:67d980fcbc7a Sat Oct 24 13:53:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> syscall: Addition of an ioctl command code for Power.
diff 6640:30d92d2b66a1 Wed Sep 16 01:36:00 EDT 2009 Vince Weaver <vince@csl.cornell.edu> Syscalls: Implement sysinfo() syscall.
diff 6415:d6f1c81980e2 Wed Jul 29 03:09:00 EDT 2009 Ali Saidi <saidi@eecs.umich.edu> ARM: Fix an ioctl constant.
diff 6413:424ac9b1079a Mon Jul 27 03:54:00 EDT 2009 Ali Saidi <saidi@eecs.umich.edu> ARM: Update some syscall constants and delete others that are Alpha only.
diff 6395:05f1d2cd7e9e Mon Jul 27 03:51:00 EDT 2009 Ali Saidi <saidi@eecs.umich.edu> ARM: Fix fstat/fstat64 structs to match EABI definitions.
diff 6341:46819ffe2778 Wed Jul 15 00:03:00 EDT 2009 Jack Whitham <jack-m5ml2@cs.york.ac.uk> ARM: Fix the "open" flag constants.
6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5
/gem5/src/arch/mips/
H A Disa.ccdiff 6806:45879b0e3240 Thu Dec 31 15:30:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Extract CPU pointer from the thread context in scheduleCP0 setMiscReg.

The MIPS ISA object expects to be constructed with a CPU pointer it uses to
look at other thread contexts and allow them to be manipulated with control
registers. Unfortunately, that differs from all the other ISA classes and
would complicate their implementation.

This change makes the event constructor use a CPU pointer pulled out of the
thread context passed to setMiscReg instead.
diff 6383:31c067ae3331 Wed Jul 22 02:38:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Format the register index constants like the other ISAs.
Also a few more style fixes.
diff 6378:4a2ff62c3b4f Tue Jul 21 04:08:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Many style fixes.
White space, commented out code, some other minor fixes.
diff 6376:eaf61ef6a8f2 Mon Jul 20 23:14:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Use BitUnions instead of bits() functions and constants.
Also fix style issues in regions around these changes.
diff 6334:285b9886fee2 Thu Jul 09 23:28:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Fold the MiscRegFile all the way into the ISA object.
diff 6328:67dbc192f692 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Collapse ARM and MIPS regfile directories.
6313:95f69a436c82 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Add an ISA object which replaces the MiscRegFile.
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.
H A Dinterrupts.ccdiff 6383:31c067ae3331 Wed Jul 22 02:38:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Format the register index constants like the other ISAs.
Also a few more style fixes.
diff 6379:75d4aaf7dd54 Tue Jul 21 04:09:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Get MIPS_FS to compile, more style fixes.
Some breakage was from my BitUnion change, some was much older.
diff 6378:4a2ff62c3b4f Tue Jul 21 04:08:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Many style fixes.
White space, commented out code, some other minor fixes.
/gem5/src/dev/x86/
H A DSouthBridge.pydiff 6432:550f76603d41 Sun Aug 02 21:01:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Set up the IDE device correctly, ie. with and using legacy ports.
diff 5843:a2c317cefcf8 Sun Feb 01 03:26:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Configure the first PCI interrupt.
diff 5842:1349786dd9a7 Sun Feb 01 03:25:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Hook up the IDE controller interrupt line.
diff 5833:5a07c4e3249b Sun Feb 01 03:00:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Plug in an IDE controller.
diff 5831:ee307cca6d31 Sun Feb 01 02:59:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add a keyboard controller device.
diff 5827:ac2c268bf4f1 Sun Feb 01 02:33:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Rework interrupt pins to allow one to many connections.
diff 5818:b47de42ec8b2 Sun Jan 25 23:35:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add a dummy minimal DMA controller that doesn't do anything.
H A DSConscriptdiff 6045:214461cb8abe Sun Apr 19 05:42:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make code that sends an interrupt from the IO APIC available for IPIs.
diff 5831:ee307cca6d31 Sun Feb 01 02:59:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add a keyboard controller device.
diff 5818:b47de42ec8b2 Sun Jan 25 23:35:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add a dummy minimal DMA controller that doesn't do anything.
/gem5/src/arch/arm/
H A Dintregs.hhdiff 6734:4ac7bc30c482 Tue Nov 10 23:19:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Fix the integer register indexes.

The PC indexes in the various register sets was defined in the section for
unaliased registers which was throwing off the indexing. This moves those
where they belong. Also, to make detecting accesses to the PC easier and
because it's in the same place in all modes, the intRegForceUser function
now passes it through as index 15.
diff 6726:a5322e816a2a Sun Nov 08 18:49:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Support forcing load/store multiple to use user registers.
diff 6724:70129fdded75 Sun Nov 08 05:08:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Split the condition codes out of the CPSR.

This allows those bits to be renamed while allowing the other fields to
control the behavior of the processor.
diff 6721:77318ac91316 Sun Nov 08 04:59:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Add back in spots for Rhi and Rlo, and use a named constant for LR.
6717:07546255fb03 Sun Nov 08 03:07:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Set up an intregs.hh for ARM.

Add constants for all the modes and registers, maps for aliasing, functions
that use the maps and range check, and use a named constant instead of a magic
number for the microcode register.
/gem5/src/arch/mips/linux/
H A Dlinux.hhdiff 6689:67d980fcbc7a Sat Oct 24 13:53:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> syscall: Addition of an ioctl command code for Power.
diff 6640:30d92d2b66a1 Wed Sep 16 01:36:00 EDT 2009 Vince Weaver <vince@csl.cornell.edu> Syscalls: Implement sysinfo() syscall.
diff 6378:4a2ff62c3b4f Tue Jul 21 04:08:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Many style fixes.
White space, commented out code, some other minor fixes.
diff 5991:3ca926101a5c Thu Mar 05 20:15:00 EST 2009 Steve Reinhardt <steve.reinhardt@amd.com> Get rid of 'using namespace' declarations in headers.
diff 5867:c3e4371d37a8 Tue Feb 10 18:49:00 EST 2009 Korey Sewell <ksewell@umich.edu> syscall: Expose ioctl for MIPS
/gem5/src/mem/ruby/common/
H A DNetDest.ccdiff 6797:7bf0a839c237 Wed Nov 18 19:34:00 EST 2009 Brad Beckmann <Brad.Beckmann@amd.com> Resurrection of the CMP token protocol to GEM5
diff 6372:f1a41ea3bbab Sat Jul 18 19:20:00 EDT 2009 Derek Hower <drh5@cs.wisc.edu> ruby: removed all refs to old RubyConfig
diff 6284:a63d1dc4c820 Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: replace strings that were missed in original ruby import.
diff 6154:6bb54dcb940e Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Make ruby #includes use full paths to the files they're including.
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths. Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.
6145:15cca6ab723a Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import ruby and slicc from GEMS

We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.
H A DSet.hhdiff 6372:f1a41ea3bbab Sat Jul 18 19:20:00 EDT 2009 Derek Hower <drh5@cs.wisc.edu> ruby: removed all refs to old RubyConfig
diff 6284:a63d1dc4c820 Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: replace strings that were missed in original ruby import.
diff 6163:92318648212f Mon May 11 13:38:00 EDT 2009 Polina Dudnik <pdudnik@gmail.com> ruby: decommission code

1. Set.* and BigSet.* are replaced with OptBigSet.* which was renamed Set.*
2. Decomissioned all bloom filters
3. Decomissioned ruby/simics directory
diff 6154:6bb54dcb940e Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Make ruby #includes use full paths to the files they're including.
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths. Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.
6145:15cca6ab723a Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import ruby and slicc from GEMS

We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.
H A DAddress.hhdiff 6712:b95abe00dd9d Wed Nov 04 19:57:00 EST 2009 Nathan Binkert <nate@binkert.org> build: fix compile problems pointed out by gcc 4.4
diff 6372:f1a41ea3bbab Sat Jul 18 19:20:00 EDT 2009 Derek Hower <drh5@cs.wisc.edu> ruby: removed all refs to old RubyConfig
diff 6285:ce086eca1ede Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import the latest ruby changes from gems.
This was done with an automated process, so there could be things that were
done in this tree in the past that didn't make it. One known regression
is that atomic memory operations do not seem to work properly anymore.
diff 6239:0c808c6d4481 Wed Jun 10 03:41:00 EDT 2009 Nathan Binkert <nate@binkert.org> copyright: I missed some copyrights during ruby integration
diff 6154:6bb54dcb940e Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Make ruby #includes use full paths to the files they're including.
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths. Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.
6145:15cca6ab723a Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import ruby and slicc from GEMS

We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.
/gem5/src/arch/x86/insts/
H A Dmicroldstop.hhdiff 6622:aff9a522956a Fri Aug 21 12:10:00 EDT 2009 Nathan Binkert <nate@binkert.org> X86: fix some simple compile issues
static should not be used for constants that are not inside a class definition.
diff 6345:f9ae7c3a036c Thu Jul 16 12:29:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Take limitted advantage of the compilers type checking for microop operands.
diff 6132:916f10213bea Thu Apr 23 04:43:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Put the StoreCheck flag with the others, and don't collide with other flags.
diff 5965:71f8d7c12619 Fri Feb 27 12:23:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Fix segment limit checks.
diff 5912:d113f6def227 Wed Feb 25 13:18:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add a flag to force memory accesses to happen at CPL 0.
/gem5/src/mem/ruby/profiler/
H A DAddressProfiler.ccdiff 6433:0f0f0fbef977 Mon Jul 27 22:43:00 EDT 2009 Derek Hower <drh5@cs.wisc.edu> ruby: removed unused/incorrect profiler state
diff 6285:ce086eca1ede Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import the latest ruby changes from gems.
This was done with an automated process, so there could be things that were
done in this tree in the past that didn't make it. One known regression
is that atomic memory operations do not seem to work properly anymore.
diff 6284:a63d1dc4c820 Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: replace strings that were missed in original ruby import.
diff 6154:6bb54dcb940e Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Make ruby #includes use full paths to the files they're including.
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths. Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.
6145:15cca6ab723a Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import ruby and slicc from GEMS

We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.
H A DAddressProfiler.hhdiff 6433:0f0f0fbef977 Mon Jul 27 22:43:00 EDT 2009 Derek Hower <drh5@cs.wisc.edu> ruby: removed unused/incorrect profiler state
diff 6285:ce086eca1ede Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import the latest ruby changes from gems.
This was done with an automated process, so there could be things that were
done in this tree in the past that didn't make it. One known regression
is that atomic memory operations do not seem to work properly anymore.
diff 6284:a63d1dc4c820 Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: replace strings that were missed in original ruby import.
diff 6154:6bb54dcb940e Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Make ruby #includes use full paths to the files they're including.
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths. Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.
6145:15cca6ab723a Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import ruby and slicc from GEMS

We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.
/gem5/src/cpu/
H A Dnativetrace.ccdiff 6409:6eaa041d043e Mon Jul 27 03:54:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Make native trace print out what instruction caused an error.
diff 6365:a3037fa327a0 Mon Jul 20 02:54:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> CPU: Separate out native trace into ISA (in)dependent code and SimObjects.
diff 6329:5d8b91875859 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Add a registers.hh file as an ISA switched header.
This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.
/gem5/src/arch/x86/
H A DSConscriptdiff 6515:a785733109e7 Mon Aug 17 21:15:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Create base classes for use with media/SIMD microops.
diff 6365:a3037fa327a0 Mon Jul 20 02:54:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> CPU: Separate out native trace into ISA (in)dependent code and SimObjects.
diff 6336:25635830e33c Thu Jul 09 23:29:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Fold the MiscRegFile all the way into the ISA object.
diff 6329:5d8b91875859 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Add a registers.hh file as an ISA switched header.
This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.
diff 6316:51f3026d4cbb Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Eliminate the ISA defined integer register file.
diff 6315:c7295a4826d5 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Eliminate the ISA defined floating point register file.
diff 6313:95f69a436c82 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Add an ISA object which replaces the MiscRegFile.
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.
diff 5933:8b9bc09b149c Wed Feb 25 13:21:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement CLTS.
diff 5909:ecbd27e5d1f8 Wed Feb 25 13:17:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add a trace flag for tracing faults.
diff 5904:5c61233cbd53 Wed Feb 25 13:17:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add a trace flag for the page table walker.
H A Demulenv.ccdiff 6437:ecebd7cccb06 Mon Aug 03 14:01:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Fix segment override prefixes on instructions that use rbp/rsp and a displacement.
diff 6071:551b62d68f43 Sun Apr 19 07:14:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Actually handle 16 bit mode modrm.
diff 5966:833e487aa8f7 Fri Feb 27 12:23:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Respect segment override prefixes even when there's no ModRM byte.
/gem5/src/mem/ruby/system/
H A DSConscriptdiff 6797:7bf0a839c237 Wed Nov 18 19:34:00 EST 2009 Brad Beckmann <Brad.Beckmann@amd.com> Resurrection of the CMP token protocol to GEM5
diff 6782:db88ebe2c9fc Wed Nov 18 19:33:00 EST 2009 Brad Beckmann <Brad.Beckmann@amd.com> ruby: split CacheMemory.hh into a .hh and a .cc
diff 6286:40b142645016 Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> scons: update SCons files for changes in ruby.
diff 6168:ba6fe02228db Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: add RUBY sticky option that must be set to add ruby to the build
Default is false
diff 6163:92318648212f Mon May 11 13:38:00 EDT 2009 Polina Dudnik <pdudnik@gmail.com> ruby: decommission code

1. Set.* and BigSet.* are replaced with OptBigSet.* which was renamed Set.*
2. Decomissioned all bloom filters
3. Decomissioned ruby/simics directory
6157:eaf2fd8f54c0 Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Migrate all of ruby and slicc to SCons.
Add the PROTOCOL sticky option sets the coherence protocol that slicc
will parse and therefore ruby will use. This whole process was made
difficult by the fact that the set of files that are output by slicc
are not easily known ahead of time. The easiest thing wound up being
to write a parser for slicc that would tell me. Incidentally this
means we now have a slicc grammar written in python.
/gem5/src/arch/arm/isa/formats/
H A Dbranch.isadiff 6724:70129fdded75 Sun Nov 08 05:08:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Split the condition codes out of the CPSR.

This allows those bits to be renamed while allowing the other fields to
control the behavior of the processor.
diff 6259:71dd4e07e626 Thu Jun 25 00:22:00 EDT 2009 Jack Whitman <jack-m5ml2@cs.york.ac.uk> ARM: Link register is trashed by non-executed branch and link operations.
diff 6253:988a001820f8 Sun Jun 21 20:21:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Simplify the ISA desc by pulling some classes out of it.
diff 6243:3a1698fbbc9f Sun Jun 21 12:37:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Make the isa parser aware that CPSR is being used.
diff 6242:1cee707c1228 Sun Jun 21 12:21:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Pull some static code out of the isa desc and create miscregs.hh.
6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5
/gem5/src/arch/x86/linux/
H A Dlinux.hhdiff 6693:ce63047d1bd9 Tue Oct 20 15:15:00 EDT 2009 Vince Weaver <vince@csl.cornell.edu> Fix stat64 structure on 32-bit X86_SE

The st_size entry was in the wrong place
(see linux-2.6.29/arch/x86/include/asm/stat.h )

Also, the packed attribute is needed when compiling on a
64-bit machine, otherwise gcc adds extra padding that
break the layout of the structure.
diff 6673:f8453ff56966 Fri Oct 02 04:32:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make successive anonymous mmaps move down in 32 bit SE mode Linux.
diff 6640:30d92d2b66a1 Wed Sep 16 01:36:00 EDT 2009 Vince Weaver <vince@csl.cornell.edu> Syscalls: Implement sysinfo() syscall.
diff 5976:536125d85fa3 Fri Feb 27 12:26:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add a structure to allow mapping between the host and guest fstat formats.
diff 5971:9c6391381323 Fri Feb 27 12:25:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add a 32 bit mmap2 system call.
diff 5960:c9c465241d3b Fri Feb 27 12:22:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Install some 32 bit system calls.
/gem5/src/base/
H A Dstatistics.hhdiff 6227:a17798f2a52c Fri Jun 05 02:21:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: clean up types, especially signed vs unsigned
diff 6216:2f4020838149 Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> includes: sort includes again
diff 6214:1ec0ec8933ae Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: Move stuff for global types into src/base/types.hh
diff 6213:2f07b47d95a1 Wed May 13 10:18:00 EDT 2009 Nathan Binkert <nate@binkert.org> stats: tidy up the Distribution type a little bit
diff 6212:64c3b989238c Wed May 13 10:18:00 EDT 2009 Nathan Binkert <nate@binkert.org> stats: fancy is a bad name
diff 6130:0fb959250892 Wed Apr 22 16:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> stats: Move flags into info.hh and use base/flags.hh to manage the flags
diff 6129:05405c5b8c16 Wed Apr 22 16:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> stats: Shuffle around info stuff so it can be accessed separately
diff 6128:fdfbd4c6e449 Wed Apr 22 16:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> stats: Rename the info classes to hopefully make things a bit clearer
FooInfoBase became FooInfo
FooInfo became FooInfoProxy
diff 6026:45c8a91d1174 Thu Apr 09 01:22:00 EDT 2009 Nathan Binkert <nate@binkert.org> stats: disallow duplicate statistic names.
diff 6015:4df1c7698e52 Mon Mar 16 18:16:00 EDT 2009 Nathan Binkert <nate@binkert.org> stats: fix compiler error
/gem5/src/mem/slicc/ast/
H A DMemberExprAST.pydiff 6690:4dc4e494e4d8 Mon Oct 26 20:06:00 EDT 2009 Brad Beckmann <Brad.Beckmann@amd.com> fixed error message generation bug in SLICC ast files
6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc.
This is simply a translation of the C++ slicc into python with very minimal
reorganization of the code. The output can be verified as nearly identical
by doing a "diff -wBur".

Slicc can easily be run manually by using util/slicc
H A DReturnStatementAST.pydiff 6690:4dc4e494e4d8 Mon Oct 26 20:06:00 EDT 2009 Brad Beckmann <Brad.Beckmann@amd.com> fixed error message generation bug in SLICC ast files
6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc.
This is simply a translation of the C++ slicc into python with very minimal
reorganization of the code. The output can be verified as nearly identical
by doing a "diff -wBur".

Slicc can easily be run manually by using util/slicc

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