16019Shines@cs.fsu.edu// -*- mode:c++ -*- 26019Shines@cs.fsu.edu 313354Sciro.santilli@arm.com// Copyright (c) 2010,2012-2013,2017-2018 ARM Limited 47152Sgblack@eecs.umich.edu// All rights reserved 57152Sgblack@eecs.umich.edu// 67152Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 77152Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 87152Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 97152Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 107152Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 117152Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 127152Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 137152Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 147152Sgblack@eecs.umich.edu// 156019Shines@cs.fsu.edu// Copyright (c) 2007-2008 The Florida State University 166019Shines@cs.fsu.edu// All rights reserved. 176019Shines@cs.fsu.edu// 186019Shines@cs.fsu.edu// Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu// modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu// met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu// redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu// documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu// neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu// contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu// this software without specific prior written permission. 286019Shines@cs.fsu.edu// 296019Shines@cs.fsu.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu// 416019Shines@cs.fsu.edu// Authors: Stephen Hines 426019Shines@cs.fsu.edu 436019Shines@cs.fsu.edu//////////////////////////////////////////////////////////////////// 446019Shines@cs.fsu.edu// 456019Shines@cs.fsu.edu// Control transfer instructions 466019Shines@cs.fsu.edu// 476019Shines@cs.fsu.edu 487152Sgblack@eecs.umich.edudef format ArmBBlxImm() {{ 497152Sgblack@eecs.umich.edu decode_block = ''' 507152Sgblack@eecs.umich.edu if (machInst.condCode == 0xF) { 517152Sgblack@eecs.umich.edu int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) | 527152Sgblack@eecs.umich.edu (bits(machInst, 24) << 1); 537602SGene.Wu@arm.com return new BlxImm(machInst, imm, COND_UC); 547152Sgblack@eecs.umich.edu } else { 557152Sgblack@eecs.umich.edu return new B(machInst, sext<26>(bits(machInst, 23, 0) << 2), 567152Sgblack@eecs.umich.edu (ConditionCode)(uint32_t)machInst.condCode); 577152Sgblack@eecs.umich.edu } 587152Sgblack@eecs.umich.edu ''' 597152Sgblack@eecs.umich.edu}}; 607152Sgblack@eecs.umich.edu 617152Sgblack@eecs.umich.edudef format ArmBlBlxImm() {{ 627152Sgblack@eecs.umich.edu decode_block = ''' 637152Sgblack@eecs.umich.edu if (machInst.condCode == 0xF) { 647152Sgblack@eecs.umich.edu int32_t imm = (sext<26>(bits(machInst, 23, 0) << 2)) | 657152Sgblack@eecs.umich.edu (bits(machInst, 24) << 1); 667602SGene.Wu@arm.com return new BlxImm(machInst, imm, COND_UC); 677152Sgblack@eecs.umich.edu } else { 687152Sgblack@eecs.umich.edu return new Bl(machInst, sext<26>(bits(machInst, 23, 0) << 2), 697152Sgblack@eecs.umich.edu (ConditionCode)(uint32_t)machInst.condCode); 707152Sgblack@eecs.umich.edu } 717152Sgblack@eecs.umich.edu ''' 727152Sgblack@eecs.umich.edu}}; 737152Sgblack@eecs.umich.edu 747252Sgblack@eecs.umich.edudef format ArmBxClz() {{ 757152Sgblack@eecs.umich.edu decode_block = ''' 767252Sgblack@eecs.umich.edu { 777252Sgblack@eecs.umich.edu const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0); 787252Sgblack@eecs.umich.edu const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12); 797252Sgblack@eecs.umich.edu if (OPCODE == 0x9) { 807252Sgblack@eecs.umich.edu return new BxReg(machInst, rm, 817252Sgblack@eecs.umich.edu (ConditionCode)(uint32_t)machInst.condCode); 827252Sgblack@eecs.umich.edu } else if (OPCODE == 0xb) { 837252Sgblack@eecs.umich.edu return new Clz(machInst, rd, rm); 847252Sgblack@eecs.umich.edu } else { 857252Sgblack@eecs.umich.edu return new Unknown(machInst); 867252Sgblack@eecs.umich.edu } 877252Sgblack@eecs.umich.edu } 887152Sgblack@eecs.umich.edu ''' 897152Sgblack@eecs.umich.edu}}; 907152Sgblack@eecs.umich.edu 917152Sgblack@eecs.umich.edudef format ArmBlxReg() {{ 927152Sgblack@eecs.umich.edu decode_block = ''' 937152Sgblack@eecs.umich.edu return new BlxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 3, 0), 947152Sgblack@eecs.umich.edu (ConditionCode)(uint32_t)machInst.condCode); 957152Sgblack@eecs.umich.edu ''' 967152Sgblack@eecs.umich.edu}}; 977154Sgblack@eecs.umich.edu 987154Sgblack@eecs.umich.edudef format Thumb16CondBranchAndSvc() {{ 997154Sgblack@eecs.umich.edu decode_block = ''' 1007154Sgblack@eecs.umich.edu if (bits(machInst, 11, 9) != 0x7) { 1017154Sgblack@eecs.umich.edu return new B(machInst, sext<9>(bits(machInst, 7, 0) << 1), 1027154Sgblack@eecs.umich.edu (ConditionCode)(uint32_t)bits(machInst, 11, 8)); 1037154Sgblack@eecs.umich.edu } else if (bits(machInst, 8)) { 10410037SARM gem5 Developers return new Svc(machInst, bits(machInst, 7, 0)); 1057154Sgblack@eecs.umich.edu } else { 1067154Sgblack@eecs.umich.edu // This space will not be allocated in the future. 1077281Sgblack@eecs.umich.edu return new Unknown(machInst); 1087154Sgblack@eecs.umich.edu } 1097154Sgblack@eecs.umich.edu ''' 1107154Sgblack@eecs.umich.edu}}; 1117154Sgblack@eecs.umich.edu 1127154Sgblack@eecs.umich.edudef format Thumb16UncondBranch() {{ 1137154Sgblack@eecs.umich.edu decode_block = ''' 1147154Sgblack@eecs.umich.edu return new B(machInst, sext<12>(bits(machInst, 10, 0) << 1), COND_UC); 1157154Sgblack@eecs.umich.edu ''' 1167154Sgblack@eecs.umich.edu}}; 1177154Sgblack@eecs.umich.edu 1187155Sgblack@eecs.umich.edudef format Thumb32BranchesAndMiscCtrl() {{ 1197154Sgblack@eecs.umich.edu decode_block = ''' 1207155Sgblack@eecs.umich.edu { 1217155Sgblack@eecs.umich.edu const uint32_t op = bits(machInst, 26, 20); 1227155Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 14, 12); 1237155Sgblack@eecs.umich.edu switch (op1 & 0x5) { 1247155Sgblack@eecs.umich.edu case 0x0: 1257155Sgblack@eecs.umich.edu if (op == 127) { 1267155Sgblack@eecs.umich.edu if (op1 & 0x2) { 1277281Sgblack@eecs.umich.edu // Permanently undefined. 1287281Sgblack@eecs.umich.edu return new Unknown(machInst); 1297155Sgblack@eecs.umich.edu } else { 13010037SARM gem5 Developers return new Smc(machInst); 1317155Sgblack@eecs.umich.edu } 1327155Sgblack@eecs.umich.edu } else if ((op & 0x38) != 0x38) { 1337155Sgblack@eecs.umich.edu const uint32_t s = bits(machInst, 26); 1347155Sgblack@eecs.umich.edu const uint32_t j1 = bits(machInst, 13); 1357155Sgblack@eecs.umich.edu const uint32_t j2 = bits(machInst, 11); 1367155Sgblack@eecs.umich.edu const uint32_t imm6 = bits(machInst, 21, 16); 1377155Sgblack@eecs.umich.edu const uint32_t imm11 = bits(machInst, 10, 0); 1387155Sgblack@eecs.umich.edu const int32_t imm = sext<21>((s << 20) | 1397155Sgblack@eecs.umich.edu (j2 << 19) | (j1 << 18) | 1407155Sgblack@eecs.umich.edu (imm6 << 12) | (imm11 << 1)); 1417155Sgblack@eecs.umich.edu return new B(machInst, imm, 1427155Sgblack@eecs.umich.edu (ConditionCode)(uint32_t)bits(machInst, 25, 22)); 1437155Sgblack@eecs.umich.edu } else { 14410037SARM gem5 Developers // HIGH: 12-11=10, LOW: 15-14=00, 12=0 1457155Sgblack@eecs.umich.edu switch (op) { 1467155Sgblack@eecs.umich.edu case 0x38: 1477155Sgblack@eecs.umich.edu case 0x39: 1487204Sgblack@eecs.umich.edu { 1497204Sgblack@eecs.umich.edu const IntRegIndex rn = 1507204Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 19, 16); 1517204Sgblack@eecs.umich.edu const uint8_t byteMask = bits(machInst, 11, 8); 15210037SARM gem5 Developers const bool r = bits(machInst, 20); 15310037SARM gem5 Developers if (bits(machInst, 5)) { 15410037SARM gem5 Developers const uint8_t sysM = (bits(machInst, 4) << 4) | 15510037SARM gem5 Developers byteMask; 15610037SARM gem5 Developers return new MsrBankedReg(machInst, rn, sysM, r); 15710037SARM gem5 Developers } else { 15810037SARM gem5 Developers if (r) { 15910037SARM gem5 Developers return new MsrSpsrReg(machInst, rn, byteMask); 16010037SARM gem5 Developers } else { 16110037SARM gem5 Developers return new MsrCpsrReg(machInst, rn, byteMask); 16210037SARM gem5 Developers } 16310037SARM gem5 Developers } 1647204Sgblack@eecs.umich.edu } 1657155Sgblack@eecs.umich.edu case 0x3a: 1667155Sgblack@eecs.umich.edu { 1677155Sgblack@eecs.umich.edu const uint32_t op1 = bits(machInst, 10, 8); 16813354Sciro.santilli@arm.com const uint32_t hint = bits(machInst, 7, 4); 16913354Sciro.santilli@arm.com const uint32_t option = bits(machInst, 3, 0); 1707155Sgblack@eecs.umich.edu if (op1 != 0) { 1717316Sgblack@eecs.umich.edu const bool enable = bits(machInst, 10, 9) == 0x2; 1727316Sgblack@eecs.umich.edu const uint32_t mods = bits(machInst, 8, 0) | 1737316Sgblack@eecs.umich.edu ((enable ? 1 : 0) << 9); 1747316Sgblack@eecs.umich.edu return new Cps(machInst, mods); 17513354Sciro.santilli@arm.com } else if (hint == 0xf) { 1767613SGene.Wu@arm.com return new Dbg(machInst); 1777155Sgblack@eecs.umich.edu } else { 17813354Sciro.santilli@arm.com switch (hint) { 1797155Sgblack@eecs.umich.edu case 0x0: 18013354Sciro.santilli@arm.com switch (option) { 18113354Sciro.santilli@arm.com case 0x0: 18213354Sciro.santilli@arm.com return new NopInst(machInst); 18313354Sciro.santilli@arm.com case 0x1: 18413354Sciro.santilli@arm.com return new YieldInst(machInst); 18513354Sciro.santilli@arm.com case 0x2: 18613354Sciro.santilli@arm.com return new WfeInst(machInst); 18713354Sciro.santilli@arm.com case 0x3: 18813354Sciro.santilli@arm.com return new WfiInst(machInst); 18913354Sciro.santilli@arm.com case 0x4: 19013354Sciro.santilli@arm.com return new SevInst(machInst); 19113354Sciro.santilli@arm.com case 0x5: 19213354Sciro.santilli@arm.com return new WarnUnimplemented( 19313354Sciro.santilli@arm.com "sevl", machInst); 19413354Sciro.santilli@arm.com } 19513354Sciro.santilli@arm.com break; 1967155Sgblack@eecs.umich.edu case 0x1: 19713354Sciro.santilli@arm.com switch (option) { 19813354Sciro.santilli@arm.com case 0x0: 19913354Sciro.santilli@arm.com return new WarnUnimplemented( 20013354Sciro.santilli@arm.com "esb", machInst); 20113354Sciro.santilli@arm.com case 0x2: 20213354Sciro.santilli@arm.com return new WarnUnimplemented( 20313354Sciro.santilli@arm.com "tsb csync", machInst); 20413354Sciro.santilli@arm.com case 0x4: 20513354Sciro.santilli@arm.com return new WarnUnimplemented( 20613354Sciro.santilli@arm.com "csdb", machInst); 20713354Sciro.santilli@arm.com } 2087155Sgblack@eecs.umich.edu break; 2097155Sgblack@eecs.umich.edu } 2107155Sgblack@eecs.umich.edu } 21113354Sciro.santilli@arm.com return new WarnUnimplemented( 21213354Sciro.santilli@arm.com "unallocated_hint", machInst); 2137155Sgblack@eecs.umich.edu } 2147155Sgblack@eecs.umich.edu case 0x3b: 2157155Sgblack@eecs.umich.edu { 2167155Sgblack@eecs.umich.edu const uint32_t op = bits(machInst, 7, 4); 2177155Sgblack@eecs.umich.edu switch (op) { 2187155Sgblack@eecs.umich.edu case 0x0: 2197284Sgblack@eecs.umich.edu return new Leavex(machInst); 2207155Sgblack@eecs.umich.edu case 0x1: 2217284Sgblack@eecs.umich.edu return new Enterx(machInst); 2227155Sgblack@eecs.umich.edu case 0x2: 2237603SGene.Wu@arm.com return new Clrex(machInst); 2247155Sgblack@eecs.umich.edu case 0x4: 22510037SARM gem5 Developers return new Dsb(machInst, 0); 2267155Sgblack@eecs.umich.edu case 0x5: 22710037SARM gem5 Developers return new Dmb(machInst, 0); 2287155Sgblack@eecs.umich.edu case 0x6: 22910037SARM gem5 Developers return new Isb(machInst, 0); 2307155Sgblack@eecs.umich.edu default: 2317155Sgblack@eecs.umich.edu break; 2327155Sgblack@eecs.umich.edu } 2337155Sgblack@eecs.umich.edu break; 2347155Sgblack@eecs.umich.edu } 2357155Sgblack@eecs.umich.edu case 0x3c: 2367344SAli.Saidi@ARM.com { 23710037SARM gem5 Developers return new BxjReg(machInst, 2387344SAli.Saidi@ARM.com (IntRegIndex)(uint32_t)bits(machInst, 19, 16), 2397344SAli.Saidi@ARM.com COND_UC); 2407344SAli.Saidi@ARM.com } 2417155Sgblack@eecs.umich.edu case 0x3d: 2427188Sgblack@eecs.umich.edu { 2437188Sgblack@eecs.umich.edu const uint32_t imm32 = bits(machInst, 7, 0); 24410037SARM gem5 Developers if (imm32 == 0) { 24510037SARM gem5 Developers return new Eret(machInst); 24610037SARM gem5 Developers } else { 24710037SARM gem5 Developers return new SubsImmPclr(machInst, INTREG_PC, 24810037SARM gem5 Developers INTREG_LR, imm32, false); 24910037SARM gem5 Developers } 2507188Sgblack@eecs.umich.edu } 2517155Sgblack@eecs.umich.edu case 0x3e: 25210037SARM gem5 Developers case 0x3f: 2537204Sgblack@eecs.umich.edu { 25410037SARM gem5 Developers 2557204Sgblack@eecs.umich.edu const IntRegIndex rd = 2567204Sgblack@eecs.umich.edu (IntRegIndex)(uint32_t)bits(machInst, 11, 8); 25710037SARM gem5 Developers const bool r = bits(machInst, 20); 25810037SARM gem5 Developers if (bits(machInst, 5)) { 25910037SARM gem5 Developers const uint8_t sysM = (bits(machInst, 4) << 4) | 26010037SARM gem5 Developers bits(machInst, 11, 8); 26110037SARM gem5 Developers return new MrsBankedReg(machInst, rd, sysM, r); 26210037SARM gem5 Developers } else { 26310037SARM gem5 Developers if (r) { 26410037SARM gem5 Developers return new MrsSpsr(machInst, rd); 26510037SARM gem5 Developers } else { 26610037SARM gem5 Developers return new MrsCpsr(machInst, rd); 26710037SARM gem5 Developers } 26810037SARM gem5 Developers } 2697204Sgblack@eecs.umich.edu } 27012248Sgiacomo.travaglini@arm.com case 0x7e: 2717204Sgblack@eecs.umich.edu { 27210037SARM gem5 Developers uint32_t imm16 = (bits(machInst, 19, 16) << 12) | 27310037SARM gem5 Developers (bits(machInst, 11, 0) << 0); 27410037SARM gem5 Developers return new Hvc(machInst, imm16); 2757204Sgblack@eecs.umich.edu } 2767155Sgblack@eecs.umich.edu } 2777155Sgblack@eecs.umich.edu break; 2787155Sgblack@eecs.umich.edu } 2797155Sgblack@eecs.umich.edu case 0x1: 2807155Sgblack@eecs.umich.edu { 2817155Sgblack@eecs.umich.edu const uint32_t s = bits(machInst, 26); 2827155Sgblack@eecs.umich.edu const uint32_t i1 = !(bits(machInst, 13) ^ s); 2837155Sgblack@eecs.umich.edu const uint32_t i2 = !(bits(machInst, 11) ^ s); 2847155Sgblack@eecs.umich.edu const uint32_t imm10 = bits(machInst, 25, 16); 2857155Sgblack@eecs.umich.edu const uint32_t imm11 = bits(machInst, 10, 0); 2867155Sgblack@eecs.umich.edu const int32_t imm = sext<25>((s << 24) | 2877155Sgblack@eecs.umich.edu (i1 << 23) | (i2 << 22) | 2887155Sgblack@eecs.umich.edu (imm10 << 12) | (imm11 << 1)); 2898909SAli.Saidi@ARM.com return new B(machInst, imm, COND_UC); 2907155Sgblack@eecs.umich.edu } 2917155Sgblack@eecs.umich.edu case 0x4: 2927155Sgblack@eecs.umich.edu { 2937290Sgblack@eecs.umich.edu if (bits(machInst, 0) == 1) { 2947290Sgblack@eecs.umich.edu return new Unknown(machInst); 2957290Sgblack@eecs.umich.edu } 2967155Sgblack@eecs.umich.edu const uint32_t s = bits(machInst, 26); 2977155Sgblack@eecs.umich.edu const uint32_t i1 = !(bits(machInst, 13) ^ s); 2987155Sgblack@eecs.umich.edu const uint32_t i2 = !(bits(machInst, 11) ^ s); 2997155Sgblack@eecs.umich.edu const uint32_t imm10h = bits(machInst, 25, 16); 3007155Sgblack@eecs.umich.edu const uint32_t imm10l = bits(machInst, 10, 1); 3017155Sgblack@eecs.umich.edu const int32_t imm = sext<25>((s << 24) | 3027155Sgblack@eecs.umich.edu (i1 << 23) | (i2 << 22) | 3037155Sgblack@eecs.umich.edu (imm10h << 12) | (imm10l << 2)); 3048909SAli.Saidi@ARM.com return new BlxImm(machInst, imm, COND_UC); 3057155Sgblack@eecs.umich.edu } 3067155Sgblack@eecs.umich.edu case 0x5: 3077155Sgblack@eecs.umich.edu { 3087155Sgblack@eecs.umich.edu const uint32_t s = bits(machInst, 26); 3097155Sgblack@eecs.umich.edu const uint32_t i1 = !(bits(machInst, 13) ^ s); 3107155Sgblack@eecs.umich.edu const uint32_t i2 = !(bits(machInst, 11) ^ s); 3117155Sgblack@eecs.umich.edu const uint32_t imm10 = bits(machInst, 25, 16); 3127155Sgblack@eecs.umich.edu const uint32_t imm11 = bits(machInst, 10, 0); 3137155Sgblack@eecs.umich.edu const int32_t imm = sext<25>((s << 24) | 3147155Sgblack@eecs.umich.edu (i1 << 23) | (i2 << 22) | 3157155Sgblack@eecs.umich.edu (imm10 << 12) | (imm11 << 1)); 3168909SAli.Saidi@ARM.com return new Bl(machInst, imm, COND_UC); 3177155Sgblack@eecs.umich.edu } 3187155Sgblack@eecs.umich.edu default: 3197155Sgblack@eecs.umich.edu break; 3207155Sgblack@eecs.umich.edu } 3217155Sgblack@eecs.umich.edu return new Unknown(machInst); 3227155Sgblack@eecs.umich.edu } 3237154Sgblack@eecs.umich.edu ''' 3247154Sgblack@eecs.umich.edu}}; 325