Searched hist:2009 (Results 101 - 125 of 951) sorted by relevance

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/gem5/src/mem/slicc/symbols/
H A DAction.py6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc.
This is simply a translation of the C++ slicc into python with very minimal
reorganization of the code. The output can be verified as nearly identical
by doing a "diff -wBur".

Slicc can easily be run manually by using util/slicc
H A DEvent.py6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc.
This is simply a translation of the C++ slicc into python with very minimal
reorganization of the code. The output can be verified as nearly identical
by doing a "diff -wBur".

Slicc can easily be run manually by using util/slicc
H A DSymbol.py6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc.
This is simply a translation of the C++ slicc into python with very minimal
reorganization of the code. The output can be verified as nearly identical
by doing a "diff -wBur".

Slicc can easily be run manually by using util/slicc
/gem5/src/arch/alpha/
H A Dregredir.cc6332:2c3e2326a3c3 Thu Jul 09 03:20:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Alpha: Missed a file in an earlier changeset.
/gem5/src/arch/arm/insts/
H A Dpred_inst.ccdiff 6306:fe1004d455b2 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Tune up predicated instruction decoding.
diff 6264:588457e03a81 Sat Jun 27 03:30:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Show more information when disassembling data processing intstructions.
This will need more work, but it should be a lot closer.
diff 6262:43950710afdc Sat Jun 27 03:29:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Write a function for printing mnemonics and predicates.
6253:988a001820f8 Sun Jun 21 20:21:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Simplify the ISA desc by pulling some classes out of it.
/gem5/src/arch/arm/isa/
H A Dcopyright.txt6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5
/gem5/src/arch/power/
H A DSConsopts6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
/gem5/src/arch/power/insts/
H A Dcondition.cc6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
H A Dfloating.cc6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
H A Dinteger.cc6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
H A Dmisc.cc6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
/gem5/src/arch/power/isa/formats/
H A Dcondition.isa6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
H A Dformats.isa6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
/gem5/src/arch/power/isa/
H A Dmain.isa6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
/gem5/src/arch/x86/isa/decoder/
H A Dlocked_opcodes.isadiff 6611:2cd76560a1f1 Mon Aug 17 23:25:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Double check the two byte portion of the decoder and fix bugs/clean up.
diff 6486:33faa9915d16 Sun Aug 09 04:01:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement the CMPXCHG8B/CMPXCHG16B instruction.
diff 6100:a61ac4a3591d Sun Apr 19 16:17:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Fix up a copyright.
6098:34690e3cf53e Sun Apr 19 07:57:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Recognize and handle the lock legacy prefix.
/gem5/src/arch/x86/isa/insts/general_purpose/
H A Dlogical.pydiff 6089:030c2a63fb61 Sun Apr 19 07:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement a locking version of NOT.
diff 6087:7736bc8824a1 Sun Apr 19 07:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement a locking version of XOR.
diff 6085:c210d3e04532 Sun Apr 19 07:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement a locking version of AND.
diff 6082:5db340cc3c47 Sun Apr 19 07:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement a locking version of OR.
H A Dsystem_calls.pydiff 6344:b7104eda0795 Thu Jul 16 12:27:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Fix a number of places where the wrong form of a microop was used.
diff 6222:9ee4a06a960b Fri May 29 02:27:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Keep track of more descriptor state to accomodate KVM.
diff 6062:2116d308076f Sun Apr 19 06:47:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Explicitly use the right width in a few places that need a 64 bit value.
diff 5908:c24a1ffc4ad0 Wed Feb 25 13:17:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement the sysret instruction in long mode.
diff 5907:8a633e6a8df1 Wed Feb 25 13:17:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement the longmode versions of the syscall instruction.
/gem5/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/
H A Drotate.pydiff 6455:709527fb7250 Wed Aug 05 06:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Set the flags on rotate left with carry instructions.
diff 6450:b9aa6a397b57 Wed Aug 05 06:00:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Set the flags for rotate right with carry instructions.
diff 6448:a32abe4e17e1 Wed Aug 05 05:59:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Set the flags on a rotate right instruction.
diff 6445:647111272094 Wed Aug 05 05:58:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Actually set the flags on a rotate left instruction.
H A Dshift.pydiff 6481:fa6d324aa2f9 Fri Aug 07 13:13:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: (Re)Implemented SHRD.
diff 6480:ed9d773de88f Fri Aug 07 13:13:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement SHLD.
diff 5977:4fff54ab52ae Fri Feb 27 12:26:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement shrd.
diff 5961:969fb3187eba Fri Feb 27 12:23:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Compute shift instruction flags correctly.
/gem5/src/arch/arm/isa/formats/
H A Dpred.isadiff 6741:73d89772f409 Wed Nov 11 02:44:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Fix some bugs in the ISA desc and fill out some instructions.
diff 6724:70129fdded75 Sun Nov 08 05:08:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Split the condition codes out of the CPSR.

This allows those bits to be renamed while allowing the other fields to
control the behavior of the processor.
diff 6423:727622fa50e5 Thu Jul 30 01:24:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Mul and mla ignore the c and v flags, but we were setting them to 1.
diff 6276:11dab30a70e8 Thu Jul 02 01:17:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Make DataOps select from a set of ways to set the c and v flags.
diff 6273:e46f6767b2c0 Thu Jul 02 01:16:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Add defaults for DataOp flag code.
diff 6272:fa79e8f9ab41 Thu Jul 02 01:16:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Get rid of the val2 variable.
diff 6271:d0fb87f3318e Thu Jul 02 01:15:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Centralize the declaration of resTemp.
diff 6270:e5794c49dd7c Thu Jul 02 01:12:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Add a DataImmOp format similar to DataOp.
diff 6265:154338c2c6f6 Thu Jul 02 01:10:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Add a DataOp format so data op definitions can be aggregated.
diff 6253:988a001820f8 Sun Jun 21 20:21:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Simplify the ISA desc by pulling some classes out of it.
/gem5/src/arch/x86/isa/insts/system/
H A Dsegmentation.pydiff 6644:57fba079b7ff Wed Sep 16 22:28:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Fix setting the busy bit in the task descriptor in LTR.
diff 6062:2116d308076f Sun Apr 19 06:47:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Explicitly use the right width in a few places that need a 64 bit value.
diff 5937:177534612ec0 Wed Feb 25 13:21:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement the lldt instruction.
diff 5930:ec124ac0984b Wed Feb 25 13:20:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Rename oszForPseudoDesc maxOsz to reflect its more general use.
diff 5927:5e3367b103da Wed Feb 25 13:20:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Do a merge for the zero extension microop.
diff 5902:7a323daa3df2 Wed Feb 25 13:17:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement the LTR instruction.
/gem5/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/
H A Dmove.pydiff 6715:fb4a3a61bc74 Wed Nov 04 13:22:00 EST 2009 Vince Weaver <vince@csl.cornell.edu> X86: Fix problem with movhps instruction

This problem is like the one fixed with movhpd a few weeks ago.
A +8 displacement is used to access memory when there should
be none.

This fix is needed for the perlbmk spec2k benchmark to run.
diff 6698:21047815f78e Wed Oct 28 02:50:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Replace "DISPLACEMENT" with disp in movhpd.
diff 6697:4863725cb4d9 Tue Oct 27 14:11:00 EDT 2009 Vince Weaver <vince@csl.cornell.edu> Fix problem with the x86 sse movhpd instruction.

The movhpd instruction was writing to the wrong memory offset.
diff 6600:bb997cd711af Mon Aug 17 23:25:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement MOVSS.
diff 6564:9ed64f6888cf Mon Aug 17 21:44:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement many of the media mov instructions.
diff 6518:1ad4a7774b3c Mon Aug 17 21:15:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Use suffixes to differentiate XMM/MMX/GPR operands.
/gem5/src/mem/slicc/ast/
H A DDeclAST.pydiff 6714:028047200ff7 Thu Nov 05 14:11:00 EST 2009 Steve Reinhardt <steve.reinhardt@amd.com> slicc: tweak file enumeration for scons
Right now .cc and .hh files are handled separately, but then
they're just munged together at the end by scons, so it
doesn't buy us anything. Might as well munge from the start
since we'll eventually be adding generated Python files
to the list too.
6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc.
This is simply a translation of the C++ slicc into python with very minimal
reorganization of the code. The output can be verified as nearly identical
by doing a "diff -wBur".

Slicc can easily be run manually by using util/slicc
/gem5/src/arch/mips/
H A Dpra_constants.hhdiff 6379:75d4aaf7dd54 Tue Jul 21 04:09:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Get MIPS_FS to compile, more style fixes.
Some breakage was from my BitUnion change, some was much older.
diff 6376:eaf61ef6a8f2 Mon Jul 20 23:14:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Use BitUnions instead of bits() functions and constants.
Also fix style issues in regions around these changes.
/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/
H A Dendian_conversion.pydiff 6478:2ec6bfc8f9c7 Fri Aug 07 13:12:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Make the qaud width bswap instruction handle the fact that 32 bit operations zero extend.
diff 5814:a9e8668557bf Sun Jan 25 23:32:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement the bswap instruction.

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