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8610:9bdd52a2214c |
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03-Nov-2011 |
Nilay Vaish<nilay@cs.wisc.edu> |
x86: Add microop for fence
This patch adds a new microop for memory barrier. The microop itself does
nothing, but since it is marked as a memory barrier, the O3 CPU should flush
all the pending loads and stores before the fence to the memory system.
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7087:fb8d5786ff30 |
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24-May-2010 |
Nathan Binkert <nate@binkert.org> |
copyright: Change HP copyright on x86 code to be more friendly
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6089:030c2a63fb61 |
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19-Apr-2009 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Implement a locking version of NOT.
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6087:7736bc8824a1 |
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19-Apr-2009 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Implement a locking version of XOR.
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6085:c210d3e04532 |
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19-Apr-2009 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Implement a locking version of AND.
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6082:5db340cc3c47 |
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19-Apr-2009 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Implement a locking version of OR.
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5119:a4469f2919f3 |
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03-Oct-2007 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Put ldst into the microcode (the earlier changeset didn't really).
Also clean things up as much as possible so that faulting won't break an
instruction. More microops which verify addresses are needed.
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5081:2ccce8600a9d |
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19-Sep-2007 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
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