xref: /gem5/src/arch/power/isa/formats/condition.isa

// -*- mode:c++ -*-

// Copyright (c) 2009 The University of Edinburgh
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// Authors: Timothy M. Jones

// Logical instructions that manipulate the condition register
def format CondLogicOp(code, *flags) {{
        iop = InstObjParams(name, Name, 'CondLogicOp', code, flags)
        header_output = BasicDeclare.subst(iop)
        decoder_output = BasicConstructor.subst(iop)
        decode_block = BasicDecode.subst(iop)
        exec_output = BasicExecute.subst(iop)
}};

// Instructions that condition register fields
def format CondMoveOp(code, *flags) {{
        iop = InstObjParams(name, Name, 'CondMoveOp', code, flags)
        header_output = BasicDeclare.subst(iop)
        decoder_output = BasicConstructor.subst(iop)
        decode_block = BasicDecode.subst(iop)
        exec_output = BasicExecute.subst(iop)
}};