Searched hist:2008 (Results 401 - 425 of 494) sorted by relevance
/gem5/src/arch/riscv/ | ||
H A D | faults.cc | diff 11725:eb58f1bbeac8 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD Third of five patches adding RISC-V to GEM5. This patch adds the RV64FD extensions, which include single- and double-precision floating point instructions. Patch 1 introduced RISC-V and implemented the base instruction set, RV64I and patch 2 implemented the integer multiply extension, RV64M. Patch 4 will implement the atomic memory instructions, RV64A, and patch 5 will add support for timing, minor, and detailed CPU models that is missing from the first four patches. [Fixed exception handling in floating-point instructions to conform better to IEEE-754 2008 standard and behavior of the Chisel-generated RISC-V simulator.] [Fixed style errors in decoder.isa.] [Fixed some fuzz caused by modifying a previous patch.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com> |
/gem5/src/kern/linux/ | ||
H A D | linux.hh | diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs |
/gem5/src/sim/ | ||
H A D | insttracer.hh | diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs |
H A D | sim_exit.hh | diff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API. For now, there is still a single global event queue, but this is necessary for making the steps towards a parallelized m5. |
H A D | process.cc | diff 5771:f58d82cb8b7f Sun Dec 07 15:07:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> imported patch aux-fix.patch diff 5759:6e65ac8a2c80 Fri Dec 05 00:09:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> This brings M5 closer to modernity - the kernel being advertised is newer so it won't die on binaries compiled with newer glibc's, and enables use of TLS-toolchain built binaries for ALPHA_SE by putting auxiliary vectors on the stack. There are some comments in the code to help. Finally, stats changes for ALPHA are from slight perturbations to the initial stack frame, all minimal diffs. diff 5758:9c3edb28db1a Thu Dec 04 18:03:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> This patch pulls out the auxiliary vector struct from individual ISA LiveProcesses to the base LiveProcess definition so anyone can use them. diff 5753:db1653549204 Thu Nov 20 22:08:00 EST 2008 Steve Reinhardt <steve.reinhardt@amd.com> Assume files w/o obvious OS are Linux (with warning) instead of giving a fatal error. diff 5713:993c7952b930 Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Make it so that all thread contexts are registered with the System, even in SE. Process still keeps track of the tc's it owns, but registration occurs with the System, this eases the way for system-wide context Ids based on registration. diff 5514:9a903bf83a33 Wed Jul 23 17:41:00 EDT 2008 Michael Adler <Michael.Adler@intel.com> process: separate stderr from stdout - Add the option of redirecting stderr to a file. With the old behaviour, stderr would follow stdout if stdout was to a file, but stderr went to the host stderr if stdout went to the host stdout. The new default maintains stdout and stderr going to the host. Now the two can specify different files, but they will share a file descriptor if the name of the files is the same. - Add --output and --errout options to se.py to go with --input. diff 5512:755fcaf7a4cf Wed Jul 23 17:41:00 EDT 2008 Michael Adler <Michael.Adler@intel.com> RemoteGDB: add an m5 command line option for setting or disabling remote gdb. diff 5335:69d45f5f21a2 Tue Feb 05 23:44:00 EST 2008 Stephen Hines <hines@cs.fsu.edu> Add base ARM code to M5 |
/gem5/tests/ | ||
H A D | run.py | diff 5523:6279e78a2df2 Sun Aug 03 21:19:00 EDT 2008 Nathan Binkert <nate@binkert.org> sockets: Add a function to disable all listening sockets. When invoking several copies of m5 on the same machine at the same time, there can be a race for TCP ports for the terminal connections or remote gdb. Expose a function to disable those ports, and have the regression scripts disable them. There are some SimObjects that have no other function than to be used with ports (NativeTrace and EtherTap), so they will panic if the ports are disabled. |
/gem5/src/arch/mips/isa/formats/ | ||
H A D | mt.isa | diff 5715:e8c1d4e669a7 Tue Nov 04 11:35:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> get rid of all instances of readTid() and getThreadNum(). Unify and eliminate redundancies with threadId() as their replacement. |
/gem5/src/arch/x86/ | ||
H A D | process.cc | diff 5771:f58d82cb8b7f Sun Dec 07 15:07:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> imported patch aux-fix.patch diff 5758:9c3edb28db1a Thu Dec 04 18:03:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> This patch pulls out the auxiliary vector struct from individual ISA LiveProcesses to the base LiveProcess definition so anyone can use them. diff 5713:993c7952b930 Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Make it so that all thread contexts are registered with the System, even in SE. Process still keeps track of the tc's it owns, but registration occurs with the System, this eases the way for system-wide context Ids based on registration. diff 5567:8fc3b004b0df Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> arch: TheISA shouldn't really ever be used in the arch directory. We should always refer to the specific ISA in that arch directory. This is especially necessary if we're ever going to make it to the point where we actually have heterogeneous systems. |
/gem5/src/base/ | ||
H A D | trace.hh | diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs |
/gem5/src/arch/alpha/linux/ | ||
H A D | system.hh | diff 5569:baeee670d4ce Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Make a style pass over the whole arch/alpha directory. |
H A D | system.cc | diff 5569:baeee670d4ce Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Make a style pass over the whole arch/alpha directory. diff 5499:8bfc7650c344 Tue Jul 01 10:25:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Remove delVirtPort() and make getVirtPort() only return cached version. |
/gem5/src/mem/cache/prefetch/ | ||
H A D | SConscript | diff 5337:f81512eb8bdf Sun Feb 10 17:15:00 EST 2008 Steve Reinhardt <stever@gmail.com> Rename cache files for brevity and consistency with rest of tree. |
/gem5/src/dev/ | ||
H A D | Device.py | diff 6122:9af6fb59752f Wed Jul 16 14:10:00 EDT 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> mem: use single BadAddr responder per system. Previously there was one per bus, which caused some coherence problems when more than one decided to respond. Now there is just one on the main memory bus. The default bus responder on all other buses is now the downstream cache's cpu_side port. Caches no longer need to do address range filtering; instead, we just have a simple flag to prevent snoops from propagating to the I/O bus. |
/gem5/src/arch/x86/isa/decoder/ | ||
H A D | one_byte_opcodes.isa | diff 5448:67c8b7badec1 Thu Jun 12 00:58:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement and hook up STI and CLI instructions. diff 5434:2f6dad874e14 Thu Jun 12 00:53:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement a partial, sort of correct version of the protected mode variant of iret. |
/gem5/src/arch/sparc/ | ||
H A D | SConscript | diff 5647:b06b49498c79 Sun Oct 12 12:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object. diff 5403:92d376c98a41 Tue May 20 14:04:00 EDT 2008 Stephen Hines <hines@cs.fsu.edu> SCons: Fixing SCons bug 2006 issues for non-alpha ISAs |
/gem5/util/m5/ | ||
H A D | m5.c | diff 5755:8ef4ad572a6b Wed Dec 03 07:57:00 EST 2008 Nathan Binkert <nate@binkert.org> util/m5: Add a new function called pin to bind a program to a set of cores. This is not m5 specific and this currently only works in linux. diff 5754:b50a557f93df Wed Dec 03 07:57:00 EST 2008 Nathan Binkert <nate@binkert.org> util/m5: reorganize code so it is easier to add operations |
/gem5/src/arch/alpha/isa/ | ||
H A D | mem.isa | diff 5745:6b0f8306704b Fri Nov 14 07:55:00 EST 2008 Nathan Binkert <nate@binkert.org> Fix a bunch of bugs I introduced when I changed the flags stuff for packets. I did some of the flags and assertions wrong. Thanks to Brad Beckmann for pointing this out. I should have run the opt regressions instead of the fast. I also screwed up some of the logical functions in the Flags class. diff 5736:426510e758ad Mon Nov 10 14:51:00 EST 2008 Nathan Binkert <nate@binkert.org> mem: update stuff for changes to Packet and Request |
/gem5/src/arch/x86/isa/microops/ | ||
H A D | ldstop.isa | diff 5727:8b9aaeac5bab Mon Nov 10 00:55:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> X86: Fix completeAcc get call. diff 5359:8c6ff200e4c1 Tue Feb 26 23:39:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement the INVLPG instruction and the TIA microop. |
/gem5/src/cpu/o3/ | ||
H A D | inst_queue.hh | diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs. A whole bunch of stuff has been converted to use the new params stuff, but the CPU wasn't one of them. While we're at it, make some things a bit more stylish. Most of the work was done by Gabe, I just cleaned stuff up a bit more at the end. diff 5336:c7e21f4e5a2e Wed Feb 06 16:32:00 EST 2008 Stephen Hines <hines@cs.fsu.edu> Make the Event::description() a const function |
/gem5/src/mem/cache/tags/ | ||
H A D | base.cc | diff 5338:e75d02a09806 Sun Feb 10 17:45:00 EST 2008 Steve Reinhardt <stever@gmail.com> Fix #include lines for renamed cache files. 5337:f81512eb8bdf Sun Feb 10 17:15:00 EST 2008 Steve Reinhardt <stever@gmail.com> Rename cache files for brevity and consistency with rest of tree. |
/gem5/src/arch/mips/linux/ | ||
H A D | process.cc | diff 5748:f28f020f3006 Sat Nov 15 12:30:00 EST 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> syscalls: fix latent brk/obreak bug. Bogus calls to ChunkGenerator with negative size were triggering a new assertion that was added there. Also did a little renaming and cleanup in the process. diff 5513:8631b29873a2 Wed Jul 23 17:41:00 EDT 2008 Michael Adler <Michael.Adler@intel.com> syscalls: Add a bunch of missing system calls. readlink, umask, truncate, ftruncate, mkdir, and getcwd. |
/gem5/src/cpu/ | ||
H A D | base_dyn_inst_impl.hh | diff 5737:f43dbc09fad3 Mon Nov 10 14:51:00 EST 2008 Clint Smullen <cws3k@cs.virginia.edu> O3CPU: Make the instcount debugging stuff per-cpu. This is to prevent the assertion from firing if you have a large multicore. Also make sure that it's not compiled in when NDEBUG is defined diff 5375:2bd02f12dc05 Thu Mar 06 00:27:00 EST 2008 Vilas Sridharan <vilas.sridharan@gmail.com> O3CPU: Don't call dumpInsts if DEBUG is not defined |
H A D | SConscript | diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs. A whole bunch of stuff has been converted to use the new params stuff, but the CPU wasn't one of them. While we're at it, make some things a bit more stylish. Most of the work was done by Gabe, I just cleaned stuff up a bit more at the end. diff 5400:fee00a595efc Thu Apr 10 15:38:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> SCons: add comments to SConscript documenting bug workaround diff 5398:9727ba4600de Tue Apr 08 11:08:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> SCons: Manually specifying header only directories with Dir() works around the problem |
/gem5/src/mem/cache/ | ||
H A D | mshr.hh | diff 5730:dea5fcd1ead0 Mon Nov 10 17:10:00 EST 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> Cache: Refactor packet forwarding a bit. Makes adding write-through operations easier. 5337:f81512eb8bdf Sun Feb 10 17:15:00 EST 2008 Steve Reinhardt <stever@gmail.com> Rename cache files for brevity and consistency with rest of tree. |
/gem5/src/python/m5/ | ||
H A D | params.py | diff 5578:db6756431717 Tue Sep 30 02:30:00 EDT 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> Make overriding port assignments in Python work, and print better error messages when it doesn't. diff 5475:7c18f61da616 Mon Jun 16 00:26:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Prevent people from setting attributes on vector params. diff 5469:42719798884a Sat Jun 14 23:42:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Fix the memory bandwidth parameter diff 5468:786868ff3058 Sat Jun 14 23:39:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Fix floating point parameters diff 5451:01b4c909afc6 Thu Jun 12 00:59:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Params: Remove an unnecessary include. |
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