12068SN/A// -*- mode:c++ -*- 22068SN/A 32068SN/A// Copyright (c) 2003-2005 The Regents of The University of Michigan 42068SN/A// All rights reserved. 52068SN/A// 62068SN/A// Redistribution and use in source and binary forms, with or without 72068SN/A// modification, are permitted provided that the following conditions are 82068SN/A// met: redistributions of source code must retain the above copyright 92068SN/A// notice, this list of conditions and the following disclaimer; 102068SN/A// redistributions in binary form must reproduce the above copyright 112068SN/A// notice, this list of conditions and the following disclaimer in the 122068SN/A// documentation and/or other materials provided with the distribution; 132068SN/A// neither the name of the copyright holders nor the names of its 142068SN/A// contributors may be used to endorse or promote products derived from 152068SN/A// this software without specific prior written permission. 162068SN/A// 172068SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182068SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192068SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202068SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212068SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222068SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232068SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242068SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252068SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262068SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272068SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu// 292665Ssaidi@eecs.umich.edu// Authors: Steve Reinhardt 302665Ssaidi@eecs.umich.edu// Kevin Lim 312068SN/A 322649Ssaidi@eecs.umich.edu//////////////////////////////////////////////////////////////////// 332649Ssaidi@eecs.umich.edu// 342649Ssaidi@eecs.umich.edu// Memory-format instructions: LoadAddress, Load, Store 352649Ssaidi@eecs.umich.edu// 362649Ssaidi@eecs.umich.edu 372068SN/Aoutput header {{ 382068SN/A /** 392068SN/A * Base class for general Alpha memory-format instructions. 402068SN/A */ 412068SN/A class Memory : public AlphaStaticInst 422068SN/A { 432068SN/A protected: 442068SN/A 452068SN/A /// Memory request flags. See mem_req_base.hh. 465736Snate@binkert.org Request::Flags memAccessFlags; 472068SN/A 482068SN/A /// Constructor 496181Sksewell@umich.edu Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 506181Sksewell@umich.edu : AlphaStaticInst(mnem, _machInst, __opClass) 512068SN/A { 522068SN/A } 532068SN/A 5412616Sgabeblack@google.com std::string generateDisassembly( 5512616Sgabeblack@google.com Addr pc, const SymbolTable *symtab) const override; 562068SN/A }; 572068SN/A 582068SN/A /** 592068SN/A * Base class for memory-format instructions using a 32-bit 602068SN/A * displacement (i.e. most of them). 612068SN/A */ 622068SN/A class MemoryDisp32 : public Memory 632068SN/A { 642068SN/A protected: 652068SN/A /// Displacement for EA calculation (signed). 662068SN/A int32_t disp; 672068SN/A 682068SN/A /// Constructor. 696181Sksewell@umich.edu MemoryDisp32(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 706181Sksewell@umich.edu : Memory(mnem, _machInst, __opClass), 712068SN/A disp(MEMDISP) 722068SN/A { 732068SN/A } 742068SN/A }; 752068SN/A 762068SN/A 772068SN/A /** 782068SN/A * Base class for a few miscellaneous memory-format insts 792068SN/A * that don't interpret the disp field: wh64, fetch, fetch_m, ecb. 802068SN/A * None of these instructions has a destination register either. 812068SN/A */ 822068SN/A class MemoryNoDisp : public Memory 832068SN/A { 842068SN/A protected: 852068SN/A /// Constructor 866181Sksewell@umich.edu MemoryNoDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 876181Sksewell@umich.edu : Memory(mnem, _machInst, __opClass) 882068SN/A { 892068SN/A } 902068SN/A 9112616Sgabeblack@google.com std::string generateDisassembly( 9212616Sgabeblack@google.com Addr pc, const SymbolTable *symtab) const override; 932068SN/A }; 942068SN/A}}; 952068SN/A 962068SN/A 972068SN/Aoutput decoder {{ 982068SN/A std::string 992068SN/A Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const 1002068SN/A { 1012068SN/A return csprintf("%-10s %c%d,%d(r%d)", mnemonic, 1022068SN/A flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB); 1032068SN/A } 1042068SN/A 1052068SN/A std::string 1062068SN/A MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 1072068SN/A { 1082068SN/A return csprintf("%-10s (r%d)", mnemonic, RB); 1092068SN/A } 1102068SN/A}}; 1112068SN/A 1122068SN/Adef format LoadAddress(code) {{ 1133953Sstever@eecs.umich.edu iop = InstObjParams(name, Name, 'MemoryDisp32', code) 1142068SN/A header_output = BasicDeclare.subst(iop) 1152068SN/A decoder_output = BasicConstructor.subst(iop) 1162068SN/A decode_block = BasicDecode.subst(iop) 1172068SN/A exec_output = BasicExecute.subst(iop) 1182068SN/A}}; 1192068SN/A 1202068SN/A 1212068SN/Adef template LoadStoreDeclare {{ 1222068SN/A /** 1232068SN/A * Static instruction class for "%(mnemonic)s". 1242068SN/A */ 1252068SN/A class %(class_name)s : public %(base_class)s 1262068SN/A { 1272068SN/A public: 1282068SN/A 1292068SN/A /// Constructor. 1302227SN/A %(class_name)s(ExtMachInst machInst); 1312068SN/A 13212616Sgabeblack@google.com Fault execute(ExecContext *, Trace::InstRecord *) const override; 13312616Sgabeblack@google.com Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; 13412616Sgabeblack@google.com Fault completeAcc(PacketPtr, ExecContext *, 13512616Sgabeblack@google.com Trace::InstRecord *) const override; 1362068SN/A }; 1372068SN/A}}; 1382068SN/A 1396181Sksewell@umich.edudef template LoadStoreConstructor {{ 14010184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s(ExtMachInst machInst) 1416181Sksewell@umich.edu : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) 1422068SN/A { 1433953Sstever@eecs.umich.edu %(constructor)s; 1442068SN/A } 1453953Sstever@eecs.umich.edu}}; 1462068SN/A 1472068SN/A 1482069SN/Adef template LoadExecute {{ 14912234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 1502068SN/A Trace::InstRecord *traceData) const 1512068SN/A { 1522068SN/A Addr EA; 1532132SN/A Fault fault = NoFault; 1542068SN/A 1552068SN/A %(fp_enable_check)s; 1562068SN/A %(op_decl)s; 1572069SN/A %(op_rd)s; 1582068SN/A %(ea_code)s; 1592068SN/A 1602090SN/A if (fault == NoFault) { 1618442Sgblack@eecs.umich.edu fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); 1622068SN/A %(memacc_code)s; 1632068SN/A } 1642068SN/A 1652090SN/A if (fault == NoFault) { 1662069SN/A %(op_wb)s; 1672069SN/A } 1682069SN/A 1692069SN/A return fault; 1702069SN/A } 1712069SN/A}}; 1722069SN/A 1732069SN/A 1742095SN/Adef template LoadInitiateAcc {{ 17512234Sgabeblack@google.com Fault %(class_name)s::initiateAcc(ExecContext *xc, 1762095SN/A Trace::InstRecord *traceData) const 1772095SN/A { 1782095SN/A Addr EA; 1792132SN/A Fault fault = NoFault; 1802095SN/A 1812095SN/A %(fp_enable_check)s; 1822095SN/A %(op_src_decl)s; 1832095SN/A %(op_rd)s; 1842095SN/A %(ea_code)s; 1852095SN/A 1862098SN/A if (fault == NoFault) { 18711303Ssteve.reinhardt@amd.com fault = initiateMemRead(xc, traceData, EA, Mem, memAccessFlags); 1882095SN/A } 1892095SN/A 1902095SN/A return fault; 1912095SN/A } 1922095SN/A}}; 1932095SN/A 1942095SN/A 1952095SN/Adef template LoadCompleteAcc {{ 19612234Sgabeblack@google.com Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, 1972095SN/A Trace::InstRecord *traceData) const 1982095SN/A { 1992132SN/A Fault fault = NoFault; 2002095SN/A 2012095SN/A %(fp_enable_check)s; 2022506SN/A %(op_decl)s; 2032095SN/A 2048442Sgblack@eecs.umich.edu getMem(pkt, Mem, traceData); 2052095SN/A 2062098SN/A if (fault == NoFault) { 2072095SN/A %(memacc_code)s; 2082095SN/A } 2092095SN/A 2102098SN/A if (fault == NoFault) { 2112095SN/A %(op_wb)s; 2122095SN/A } 2132095SN/A 2142095SN/A return fault; 2152095SN/A } 2162095SN/A}}; 2172095SN/A 2182095SN/A 2192069SN/Adef template StoreExecute {{ 22012234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 2212069SN/A Trace::InstRecord *traceData) const 2222069SN/A { 2232069SN/A Addr EA; 2242132SN/A Fault fault = NoFault; 2254027Sstever@eecs.umich.edu 2264027Sstever@eecs.umich.edu %(fp_enable_check)s; 2274027Sstever@eecs.umich.edu %(op_decl)s; 2284027Sstever@eecs.umich.edu %(op_rd)s; 2294027Sstever@eecs.umich.edu %(ea_code)s; 2304027Sstever@eecs.umich.edu 2314027Sstever@eecs.umich.edu if (fault == NoFault) { 2324027Sstever@eecs.umich.edu %(memacc_code)s; 2334027Sstever@eecs.umich.edu } 2344027Sstever@eecs.umich.edu 2354027Sstever@eecs.umich.edu if (fault == NoFault) { 2368442Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, 2378442Sgblack@eecs.umich.edu memAccessFlags, NULL); 2384027Sstever@eecs.umich.edu } 2394027Sstever@eecs.umich.edu 2404027Sstever@eecs.umich.edu if (fault == NoFault) { 2414027Sstever@eecs.umich.edu %(postacc_code)s; 2424027Sstever@eecs.umich.edu } 2434027Sstever@eecs.umich.edu 2444027Sstever@eecs.umich.edu if (fault == NoFault) { 2454027Sstever@eecs.umich.edu %(op_wb)s; 2464027Sstever@eecs.umich.edu } 2474027Sstever@eecs.umich.edu 2484027Sstever@eecs.umich.edu return fault; 2494027Sstever@eecs.umich.edu } 2504027Sstever@eecs.umich.edu}}; 2514027Sstever@eecs.umich.edu 2524027Sstever@eecs.umich.edudef template StoreCondExecute {{ 25312234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 2544027Sstever@eecs.umich.edu Trace::InstRecord *traceData) const 2554027Sstever@eecs.umich.edu { 2564027Sstever@eecs.umich.edu Addr EA; 2574027Sstever@eecs.umich.edu Fault fault = NoFault; 2582069SN/A uint64_t write_result = 0; 2592069SN/A 2602069SN/A %(fp_enable_check)s; 2612069SN/A %(op_decl)s; 2622069SN/A %(op_rd)s; 2632069SN/A %(ea_code)s; 2642069SN/A 2652090SN/A if (fault == NoFault) { 2662069SN/A %(memacc_code)s; 2672069SN/A } 2682069SN/A 2692090SN/A if (fault == NoFault) { 2708442Sgblack@eecs.umich.edu fault = writeMemAtomic(xc, traceData, Mem, EA, 2718442Sgblack@eecs.umich.edu memAccessFlags, &write_result); 2722069SN/A } 2732069SN/A 2742090SN/A if (fault == NoFault) { 2752069SN/A %(postacc_code)s; 2762069SN/A } 2772069SN/A 2782090SN/A if (fault == NoFault) { 2792069SN/A %(op_wb)s; 2802069SN/A } 2812069SN/A 2822069SN/A return fault; 2832069SN/A } 2842069SN/A}}; 2852069SN/A 2862095SN/Adef template StoreInitiateAcc {{ 28712234Sgabeblack@google.com Fault %(class_name)s::initiateAcc(ExecContext *xc, 2882095SN/A Trace::InstRecord *traceData) const 2892095SN/A { 2902095SN/A Addr EA; 2912132SN/A Fault fault = NoFault; 2922095SN/A 2932095SN/A %(fp_enable_check)s; 2942506SN/A %(op_decl)s; 2952095SN/A %(op_rd)s; 2962095SN/A %(ea_code)s; 2972095SN/A 2982098SN/A if (fault == NoFault) { 2992095SN/A %(memacc_code)s; 3002095SN/A } 3012095SN/A 3022098SN/A if (fault == NoFault) { 3038442Sgblack@eecs.umich.edu fault = writeMemTiming(xc, traceData, Mem, EA, 3048442Sgblack@eecs.umich.edu memAccessFlags, NULL); 3052095SN/A } 3062095SN/A 3072095SN/A return fault; 3082095SN/A } 3092095SN/A}}; 3102095SN/A 3112095SN/A 3122095SN/Adef template StoreCompleteAcc {{ 31312234Sgabeblack@google.com Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, 3142095SN/A Trace::InstRecord *traceData) const 3152095SN/A { 3167712Sgblack@eecs.umich.edu return NoFault; 3172623SN/A } 3182623SN/A}}; 3192623SN/A 3202623SN/A 3212623SN/Adef template StoreCondCompleteAcc {{ 32212234Sgabeblack@google.com Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, 3232623SN/A Trace::InstRecord *traceData) const 3242623SN/A { 3252623SN/A Fault fault = NoFault; 3262623SN/A 3272623SN/A %(fp_enable_check)s; 3282623SN/A %(op_dest_decl)s; 3292623SN/A 3304040Ssaidi@eecs.umich.edu uint64_t write_result = pkt->req->getExtraData(); 3312095SN/A 3322098SN/A if (fault == NoFault) { 3332095SN/A %(postacc_code)s; 3342095SN/A } 3352095SN/A 3362098SN/A if (fault == NoFault) { 3372095SN/A %(op_wb)s; 3382095SN/A } 3392095SN/A 3402095SN/A return fault; 3412095SN/A } 3422095SN/A}}; 3432095SN/A 3442069SN/A 3452069SN/Adef template MiscExecute {{ 34612234Sgabeblack@google.com Fault %(class_name)s::execute(ExecContext *xc, 3472068SN/A Trace::InstRecord *traceData) const 3482068SN/A { 3498607Sgblack@eecs.umich.edu Addr EA M5_VAR_USED; 3502132SN/A Fault fault = NoFault; 3512068SN/A 3522068SN/A %(fp_enable_check)s; 3532068SN/A %(op_decl)s; 3542069SN/A %(op_rd)s; 3552068SN/A %(ea_code)s; 3562068SN/A 3578406Sksewell@umich.edu warn_once("Prefetch instructions in Alpha do not do anything\n"); 3582090SN/A if (fault == NoFault) { 3592069SN/A %(memacc_code)s; 3602068SN/A } 3612068SN/A 3622090SN/A return NoFault; 3632068SN/A } 3642068SN/A}}; 3652068SN/A 3667725SAli.Saidi@ARM.com// Prefetches in Alpha don't actually do anything 3677725SAli.Saidi@ARM.com// They just build an effective address and complete 3682095SN/Adef template MiscInitiateAcc {{ 36912234Sgabeblack@google.com Fault %(class_name)s::initiateAcc(ExecContext *xc, 3702095SN/A Trace::InstRecord *traceData) const 3712095SN/A { 3726185Sksewell@umich.edu warn("initiateAcc undefined: Misc instruction does not support split " 3736185Sksewell@umich.edu "access method!"); 3742098SN/A return NoFault; 3752095SN/A } 3762095SN/A}}; 3772095SN/A 3782095SN/A 3792095SN/Adef template MiscCompleteAcc {{ 38012234Sgabeblack@google.com Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc, 3812095SN/A Trace::InstRecord *traceData) const 3822095SN/A { 3836185Sksewell@umich.edu warn("completeAcc undefined: Misc instruction does not support split " 3846185Sksewell@umich.edu "access method!"); 3852110SN/A 3862098SN/A return NoFault; 3872095SN/A } 3882095SN/A}}; 3892095SN/A 3906179Sksewell@umich.edu 3912068SN/A// load instructions use Ra as dest, so check for 3922068SN/A// Ra == 31 to detect nops 3932068SN/Adef template LoadNopCheckDecode {{ 3942068SN/A { 3952068SN/A AlphaStaticInst *i = new %(class_name)s(machInst); 3962068SN/A if (RA == 31) { 3972068SN/A i = makeNop(i); 3982068SN/A } 3992068SN/A return i; 4002068SN/A } 4012068SN/A}}; 4022068SN/A 4032068SN/A 4042068SN/A// for some load instructions, Ra == 31 indicates a prefetch (not a nop) 4052068SN/Adef template LoadPrefetchCheckDecode {{ 4062068SN/A { 4072068SN/A if (RA != 31) { 4082068SN/A return new %(class_name)s(machInst); 4092068SN/A } 4102068SN/A else { 4112068SN/A return new %(class_name)sPrefetch(machInst); 4122068SN/A } 4132068SN/A } 4142068SN/A}}; 4152068SN/A 4162068SN/A 4172068SN/Alet {{ 4182075SN/Adef LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4192075SN/A postacc_code = '', base_class = 'MemoryDisp32', 4202069SN/A decode_template = BasicDecode, exec_template_base = ''): 4212075SN/A # Make sure flags are in lists (convert to lists if not). 4222075SN/A mem_flags = makeList(mem_flags) 4232075SN/A inst_flags = makeList(inst_flags) 4242068SN/A 4253953Sstever@eecs.umich.edu iop = InstObjParams(name, Name, base_class, 4263953Sstever@eecs.umich.edu { 'ea_code':ea_code, 'memacc_code':memacc_code, 'postacc_code':postacc_code }, 4273953Sstever@eecs.umich.edu inst_flags) 4282068SN/A 4292068SN/A if mem_flags: 4305736Snate@binkert.org mem_flags = [ 'Request::%s' % flag for flag in mem_flags ] 4315745Snate@binkert.org s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';' 4322068SN/A iop.constructor += s 4332068SN/A 4342069SN/A # select templates 4352623SN/A 4364027Sstever@eecs.umich.edu # The InitiateAcc template is the same for StoreCond templates as the 4374027Sstever@eecs.umich.edu # corresponding Store template.. 4382623SN/A StoreCondInitiateAcc = StoreInitiateAcc 4392623SN/A 4402069SN/A fullExecTemplate = eval(exec_template_base + 'Execute') 4412095SN/A initiateAccTemplate = eval(exec_template_base + 'InitiateAcc') 4422095SN/A completeAccTemplate = eval(exec_template_base + 'CompleteAcc') 4432069SN/A 4442068SN/A # (header_output, decoder_output, decode_block, exec_output) 4453953Sstever@eecs.umich.edu return (LoadStoreDeclare.subst(iop), 4466181Sksewell@umich.edu LoadStoreConstructor.subst(iop), 4472068SN/A decode_template.subst(iop), 4486181Sksewell@umich.edu fullExecTemplate.subst(iop) 4493953Sstever@eecs.umich.edu + initiateAccTemplate.subst(iop) 4506192Sksewell@umich.edu + completeAccTemplate.subst(iop)) 4512068SN/A}}; 4522068SN/A 4532075SN/Adef format LoadOrNop(memacc_code, ea_code = {{ EA = Rb + disp; }}, 4542075SN/A mem_flags = [], inst_flags = []) {{ 4552068SN/A (header_output, decoder_output, decode_block, exec_output) = \ 4562075SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4572069SN/A decode_template = LoadNopCheckDecode, 4582069SN/A exec_template_base = 'Load') 4592068SN/A}}; 4602068SN/A 4612068SN/A 4622068SN/A// Note that the flags passed in apply only to the prefetch version 4632075SN/Adef format LoadOrPrefetch(memacc_code, ea_code = {{ EA = Rb + disp; }}, 4642075SN/A mem_flags = [], pf_flags = [], inst_flags = []) {{ 4652068SN/A # declare the load instruction object and generate the decode block 4662068SN/A (header_output, decoder_output, decode_block, exec_output) = \ 4672075SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4682069SN/A decode_template = LoadPrefetchCheckDecode, 4692069SN/A exec_template_base = 'Load') 4702068SN/A 4712068SN/A # Declare the prefetch instruction object. 4722068SN/A 4732075SN/A # Make sure flag args are lists so we can mess with them. 4742075SN/A mem_flags = makeList(mem_flags) 4752075SN/A pf_flags = makeList(pf_flags) 4762075SN/A inst_flags = makeList(inst_flags) 4772075SN/A 4786739Sgblack@eecs.umich.edu pf_mem_flags = mem_flags + pf_flags + ['PREFETCH'] 4797725SAli.Saidi@ARM.com pf_inst_flags = inst_flags 4802068SN/A 4812068SN/A (pf_header_output, pf_decoder_output, _, pf_exec_output) = \ 4827725SAli.Saidi@ARM.com LoadStoreBase(name, Name + 'Prefetch', ea_code, ';', 4832075SN/A pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') 4842068SN/A 4852068SN/A header_output += pf_header_output 4862068SN/A decoder_output += pf_decoder_output 4872068SN/A exec_output += pf_exec_output 4882068SN/A}}; 4892068SN/A 4902068SN/A 4912075SN/Adef format Store(memacc_code, ea_code = {{ EA = Rb + disp; }}, 4922075SN/A mem_flags = [], inst_flags = []) {{ 4932068SN/A (header_output, decoder_output, decode_block, exec_output) = \ 4942075SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 4952069SN/A exec_template_base = 'Store') 4962068SN/A}}; 4972068SN/A 4982068SN/A 4992075SN/Adef format StoreCond(memacc_code, postacc_code, 5002075SN/A ea_code = {{ EA = Rb + disp; }}, 5012075SN/A mem_flags = [], inst_flags = []) {{ 5022068SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5032075SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5042623SN/A postacc_code, exec_template_base = 'StoreCond') 5052068SN/A}}; 5062068SN/A 5072068SN/A 5082068SN/A// Use 'MemoryNoDisp' as base: for wh64, fetch, ecb 5092075SN/Adef format MiscPrefetch(ea_code, memacc_code, 5102075SN/A mem_flags = [], inst_flags = []) {{ 5112068SN/A (header_output, decoder_output, decode_block, exec_output) = \ 5122075SN/A LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, 5132069SN/A base_class = 'MemoryNoDisp', exec_template_base = 'Misc') 5142068SN/A}}; 5152068SN/A 5162068SN/A 517