Searched hist:2008 (Results 351 - 375 of 494) sorted by relevance
/gem5/configs/common/ | ||
H A D | Benchmarks.py | diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs |
/gem5/src/arch/riscv/ | ||
H A D | faults.hh | diff 11725:eb58f1bbeac8 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD Third of five patches adding RISC-V to GEM5. This patch adds the RV64FD extensions, which include single- and double-precision floating point instructions. Patch 1 introduced RISC-V and implemented the base instruction set, RV64I and patch 2 implemented the integer multiply extension, RV64M. Patch 4 will implement the atomic memory instructions, RV64A, and patch 5 will add support for timing, minor, and detailed CPU models that is missing from the first four patches. [Fixed exception handling in floating-point instructions to conform better to IEEE-754 2008 standard and behavior of the Chisel-generated RISC-V simulator.] [Fixed style errors in decoder.isa.] [Fixed some fuzz caused by modifying a previous patch.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com> |
/gem5/src/dev/x86/ | ||
H A D | Pc.py | 5638:dc073dc6358b Sat Oct 11 05:23:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Rename the PC device to Pc. |
H A D | intdev.cc | 5633:e1605152cc54 Sat Oct 11 04:37:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create the IntDev and IntPin system. The IntDev class is a base for anything that supports IntPins. IntPins allow devices to generically trigger interrupts on a particular pin of an IntDev device without having to know what the device is or what pin they're attached to. |
/gem5/src/sim/ | ||
H A D | init.hh | 5522:e56c3d89be79 Sun Aug 03 21:19:00 EDT 2008 Nathan Binkert <nate@binkert.org> libm5: Create a libm5 static library for embedding m5. This should allow m5 to be more easily embedded into other simulators. The m5 binary adds a simple main function which then calls into the m5 libarary to start the simulation. In order to make this work correctly, it was necessary embed python code directly into the library instead of the zipfile hack. This is because you can't just append the zipfile to the end of a library the way you can a binary. As a result, Python files that are part of the m5 simulator are now compile, marshalled, compressed, and then inserted into the library's data section with a certain symbol name. Additionally, a new Importer was needed to allow python to get at the embedded python code. Small additional changes include: - Get rid of the PYTHONHOME stuff since I don't think anyone ever used it, and it just confuses things. Easy enough to add back if I'm wrong. - Create a few new functions that are key to initializing and running the simulator: initSignals, initM5Python, m5Main. The original code for creating libm5 was inspired by a patch Michael Adler, though the code here was done by me. |
H A D | SConscript | diff 5780:50c9d48de3ca Wed Dec 17 12:51:00 EST 2008 Steve Reinhardt <steve.reinhardt@amd.com> Make Alpha pseudo-insts available from SE mode. diff 5628:f79155751e1d Sat Oct 11 02:47:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> TLB: Make all tlbs derive from a common base class in both python and C++. diff 5522:e56c3d89be79 Sun Aug 03 21:19:00 EDT 2008 Nathan Binkert <nate@binkert.org> libm5: Create a libm5 static library for embedding m5. This should allow m5 to be more easily embedded into other simulators. The m5 binary adds a simple main function which then calls into the m5 libarary to start the simulation. In order to make this work correctly, it was necessary embed python code directly into the library instead of the zipfile hack. This is because you can't just append the zipfile to the end of a library the way you can a binary. As a result, Python files that are part of the m5 simulator are now compile, marshalled, compressed, and then inserted into the library's data section with a certain symbol name. Additionally, a new Importer was needed to allow python to get at the embedded python code. Small additional changes include: - Get rid of the PYTHONHOME stuff since I don't think anyone ever used it, and it just confuses things. Easy enough to add back if I'm wrong. - Create a few new functions that are key to initializing and running the simulator: initSignals, initM5Python, m5Main. The original code for creating libm5 was inspired by a patch Michael Adler, though the code here was done by me. diff 5474:a9b2504432d1 Sun Jun 15 23:56:00 EDT 2008 Nathan Binkert <nate@binkert.org> add compile flags to m5 |
H A D | sim_object.cc | diff 5605:b194a80157e2 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: Major API change for the Event and EventQueue structures. Since the early days of M5, an event needed to know which event queue it was on, and that data was required at the time of construction of the event object. In the future parallelized M5, this sort of requirement does not work well since the proper event queue will not always be known at the time of construction of an event. Now, events are created, and the EventQueue itself has the schedule function, e.g. eventq->schedule(event, when). To simplify the syntax, I created a class called EventManager which holds a pointer to an EventQueue and provides the schedule interface that is a proxy for the EventQueue. The intent is that objects that frequently schedule events can be derived from EventManager and then they have the schedule interface. SimObject and Port are examples of objects that will become EventManagers. The end result is that any SimObject can just call schedule(event, when) and it will just call that SimObject's eventq->schedule function. Of course, some objects may have more than one EventQueue, so this interface might not be perfect for those, but they should be relatively few. diff 5530:bbfff6d0c42c Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Get rid of the remnants of the old style parameter configuration stuff. diff 5314:e902f12a3af1 Wed Jan 02 03:20:00 EST 2008 Steve Reinhardt <stever@gmail.com> Add functional PrintReq command for memory-system debugging. |
H A D | process.hh | diff 5771:f58d82cb8b7f Sun Dec 07 15:07:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> imported patch aux-fix.patch diff 5758:9c3edb28db1a Thu Dec 04 18:03:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> This patch pulls out the auxiliary vector struct from individual ISA LiveProcesses to the base LiveProcess definition so anyone can use them. diff 5713:993c7952b930 Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Make it so that all thread contexts are registered with the System, even in SE. Process still keeps track of the tc's it owns, but registration occurs with the System, this eases the way for system-wide context Ids based on registration. diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs diff 5513:8631b29873a2 Wed Jul 23 17:41:00 EDT 2008 Michael Adler <Michael.Adler@intel.com> syscalls: Add a bunch of missing system calls. readlink, umask, truncate, ftruncate, mkdir, and getcwd. |
/gem5/src/arch/riscv/isa/ | ||
H A D | bitfields.isa | diff 11725:eb58f1bbeac8 Wed Nov 30 17:10:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD Third of five patches adding RISC-V to GEM5. This patch adds the RV64FD extensions, which include single- and double-precision floating point instructions. Patch 1 introduced RISC-V and implemented the base instruction set, RV64I and patch 2 implemented the integer multiply extension, RV64M. Patch 4 will implement the atomic memory instructions, RV64A, and patch 5 will add support for timing, minor, and detailed CPU models that is missing from the first four patches. [Fixed exception handling in floating-point instructions to conform better to IEEE-754 2008 standard and behavior of the Chisel-generated RISC-V simulator.] [Fixed style errors in decoder.isa.] [Fixed some fuzz caused by modifying a previous patch.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com> |
/gem5/src/arch/alpha/ | ||
H A D | process.cc | diff 5771:f58d82cb8b7f Sun Dec 07 15:07:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> imported patch aux-fix.patch diff 5759:6e65ac8a2c80 Fri Dec 05 00:09:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> This brings M5 closer to modernity - the kernel being advertised is newer so it won't die on binaries compiled with newer glibc's, and enables use of TLS-toolchain built binaries for ALPHA_SE by putting auxiliary vectors on the stack. There are some comments in the code to help. Finally, stats changes for ALPHA are from slight perturbations to the initial stack frame, all minimal diffs. diff 5713:993c7952b930 Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Make it so that all thread contexts are registered with the System, even in SE. Process still keeps track of the tc's it owns, but registration occurs with the System, this eases the way for system-wide context Ids based on registration. diff 5569:baeee670d4ce Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Make a style pass over the whole arch/alpha directory. |
/gem5/src/cpu/checker/ | ||
H A D | thread_context.hh | diff 5715:e8c1d4e669a7 Tue Nov 04 11:35:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> get rid of all instances of readTid() and getThreadNum(). Unify and eliminate redundancies with threadId() as their replacement. diff 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch. diff 5668:5b5a9f4203d1 Sun Oct 12 20:57:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Get rid of old RegContext code. diff 5499:8bfc7650c344 Tue Jul 01 10:25:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Remove delVirtPort() and make getVirtPort() only return cached version. |
H A D | cpu_impl.hh | diff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used, the primary identifier for a hardware context should be contextId(). The concept of threads within a CPU remains, in the form of threadId() because sometimes you need to know which context within a cpu to manipulate. diff 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch. diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs |
/gem5/src/python/ | ||
H A D | SConscript | diff 5522:e56c3d89be79 Sun Aug 03 21:19:00 EDT 2008 Nathan Binkert <nate@binkert.org> libm5: Create a libm5 static library for embedding m5. This should allow m5 to be more easily embedded into other simulators. The m5 binary adds a simple main function which then calls into the m5 libarary to start the simulation. In order to make this work correctly, it was necessary embed python code directly into the library instead of the zipfile hack. This is because you can't just append the zipfile to the end of a library the way you can a binary. As a result, Python files that are part of the m5 simulator are now compile, marshalled, compressed, and then inserted into the library's data section with a certain symbol name. Additionally, a new Importer was needed to allow python to get at the embedded python code. Small additional changes include: - Get rid of the PYTHONHOME stuff since I don't think anyone ever used it, and it just confuses things. Easy enough to add back if I'm wrong. - Create a few new functions that are key to initializing and running the simulator: initSignals, initM5Python, m5Main. The original code for creating libm5 was inspired by a patch Michael Adler, though the code here was done by me. diff 5471:576aa675d4e5 Sun Jun 15 00:15:00 EDT 2008 Nathan Binkert <nate@binkert.org> Add .m5 configuration directory diff 5470:ad060d1f1037 Sun Jun 15 00:15:00 EDT 2008 Nathan Binkert <nate@binkert.org> python: Separate the options parsing stuff. Remove options parsing stuff from main.py so things are a bit more obvious. diff 5467:6d9df90d70d7 Sat Jun 14 23:19:00 EDT 2008 Nathan Binkert <nate@binkert.org> python: Move various utility classes into a new m5.util package so they're all in the same place. This also involves having just one jobfile.py and moving it into the utils directory to avoid duplication. Lots of improvements to the utility as well. |
/gem5/ | ||
H A D | SConstruct | diff 10881:133d8bb2024f Fri Jul 03 10:14:00 EDT 2015 Curtis Dunham <Curtis.Dunham@arm.com> scons: remove dead leading underscore check e56c3d8 (2008) added it but 8e37348 (2010) removed its only use. diff 5749:7015e400bd1d Sat Nov 15 23:42:00 EST 2008 Clint Smullen <cws3k@cs.virginia.edu> Output: Include gzstream package to allow automatically-gzipped output The gzstream package provides an ostream-interface for writing gzipped files. The package comes from: http://www.cs.unc.edu/Research/compgeom/gzstream/ And is distributed under the LGPL license. Both the license and version information has been preservered, though all other files in the package have been purged. Minor modifications to the code have been made. The output module detects when a filename ends in .gz and constructs an ogzstream object instead of an ofstream object. This works for both the create(...) and find(...) commands. Additionally, since gzstream objects needs to be closed to ensure proper file termination, I have the output deconstructor deleting all ostream's that it manages on behalf of find(...). At the moment, the only output file that I know this functionality works for is stats, i.e. by specifying "--stats-file=m5stats.txt.gz" on the command line. diff 5742:828a8296270e Mon Nov 10 14:51:00 EST 2008 Nathan Binkert <nate@binkert.org> SCons: Allow top level directory of EXTRAS able to contain SConscripts. The current EXTRAS will fail if the top level directory pointed to by EXTRAS has a SConscript file in it. We allow this by including the directory name of the EXTRA in the build directory which prevents a clash between src/SConscript and extra/SConscript. Maintain compatibility with older uses of EXTRAS by adding a -I for each top level extra directory. diff 5708:96614cd66f76 Sun Oct 26 14:45:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> BATCH: Run as, ar, and ranlib with BATCH_CMD so that they execute on the batch hosts, not local host. diff 5588:d8b246a665c1 Wed Oct 08 18:34:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Scons: Update compare_versions() to ignore trailing charecters after an int. This is a fix for a mysql version number that includes a (E.g. 5.0.51a) diff 5571:7f81bb169068 Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> gcc: Version 4.3 adds some warnings that we're turning off. We just can't deal with right now. diff 5550:26231e06f86d Fri Sep 19 12:42:00 EDT 2008 Nathan Binkert <nate@binkert.org> We're searching for g++ incorrectly diff 5522:e56c3d89be79 Sun Aug 03 21:19:00 EDT 2008 Nathan Binkert <nate@binkert.org> libm5: Create a libm5 static library for embedding m5. This should allow m5 to be more easily embedded into other simulators. The m5 binary adds a simple main function which then calls into the m5 libarary to start the simulation. In order to make this work correctly, it was necessary embed python code directly into the library instead of the zipfile hack. This is because you can't just append the zipfile to the end of a library the way you can a binary. As a result, Python files that are part of the m5 simulator are now compile, marshalled, compressed, and then inserted into the library's data section with a certain symbol name. Additionally, a new Importer was needed to allow python to get at the embedded python code. Small additional changes include: - Get rid of the PYTHONHOME stuff since I don't think anyone ever used it, and it just confuses things. Easy enough to add back if I'm wrong. - Create a few new functions that are key to initializing and running the simulator: initSignals, initM5Python, m5Main. The original code for creating libm5 was inspired by a patch Michael Adler, though the code here was done by me. diff 5398:9727ba4600de Tue Apr 08 11:08:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> SCons: Manually specifying header only directories with Dir() works around the problem diff 5397:58e5b68f7095 Mon Apr 07 23:40:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> SCons: Make BATCH options global sticky so libelf is built appropriately. |
/gem5/src/dev/ | ||
H A D | io_device.hh | diff 5732:1a24f9a28729 Mon Nov 10 17:45:00 EST 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> DmaDevice: fix minor type in error message. diff 5578:db6756431717 Tue Sep 30 02:30:00 EDT 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> Make overriding port assignments in Python work, and print better error messages when it doesn't. diff 5534:9eaf72819836 Wed Aug 13 17:41:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Add the ability for a DMA to tack on an extra delay after the DMA is actually finished. diff 5386:5614618f4027 Mon Mar 24 01:08:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Don't FastAlloc MSHRs since we don't allocate them on the fly. |
/gem5/src/base/ | ||
H A D | statistics.hh | diff 5599:5bad83cddb8c Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> stats: use properly signed types for looping and comparison diff 5598:345ef3bda3d2 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Bring statistics code in line with the proper style. diff 5582:c2fd66e6a919 Thu Oct 02 14:26:00 EDT 2008 Nathan Binkert <nate@binkert.org> stats: Fix small bug pointed out by unit testing. diff 5547:747034106af4 Fri Sep 19 12:11:00 EDT 2008 Nathan Binkert <nate@binkert.org> Use C++ limits where applicable for portability |
H A D | remote_gdb.cc | diff 5545:d7c7b6752e2c Fri Sep 19 12:11:00 EDT 2008 Nathan Binkert <nate@binkert.org> Check the return value of I/O operations for failure diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs diff 5523:6279e78a2df2 Sun Aug 03 21:19:00 EDT 2008 Nathan Binkert <nate@binkert.org> sockets: Add a function to disable all listening sockets. When invoking several copies of m5 on the same machine at the same time, there can be a race for TCP ports for the terminal connections or remote gdb. Expose a function to disable those ports, and have the regression scripts disable them. There are some SimObjects that have no other function than to be used with ports (NativeTrace and EtherTap), so they will panic if the ports are disabled. diff 5499:8bfc7650c344 Tue Jul 01 10:25:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Remove delVirtPort() and make getVirtPort() only return cached version. diff 5498:2af99511ded4 Tue Jul 01 10:24:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Change everything to use the cached virtPort rather than created their own each time. This appears to work, but I don't want to commit it until it gets tested a lot more. I haven't deleted the functionality in this patch that will come later, but one question is how to enforce encourage objects that call getVirtPort() to not cache the virtual port since if the CPU changes out from under them it will be worse than useless. Perhaps a null function like delVirtPort() is still useful in that case. |
/gem5/src/mem/ | ||
H A D | physical.hh | diff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used, the primary identifier for a hardware context should be contextId(). The concept of threads within a CPU remains, in the form of threadId() because sometimes you need to know which context within a cpu to manipulate. diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs diff 5399:e951ca2d56e2 Thu Apr 10 14:44:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> PhysicalMemory: Add parameter for variance in memory delay. |
H A D | packet.cc | diff 5735:a88e8e7dec75 Mon Nov 10 14:51:00 EST 2008 Nathan Binkert <nate@binkert.org> style: clean up the Packet stuff diff 5650:d2782c951841 Sun Oct 12 03:08:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Create a message port for sending messages as apposed to reading/writing a memory range. diff 5507:52bcc301b467 Tue Jul 15 14:38:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Use ReadResp instead of LoadLockedResp for LoadLockedReq responses. diff 5319:13cb690ba6d6 Wed Jan 02 18:22:00 EST 2008 Steve Reinhardt <stever@gmail.com> Add ReadRespWithInvalidate to handle multi-level coherence situation where we defer a response to a read from a far-away cache A, then later defer a ReadExcl from a cache B on the same bus as us. We'll assert MemInhibit in both cases, but in the latter case MemInhibit will keep the invalidation from reaching cache A. This special response tells cache A that it gets the block to satisfy its read, but must immediately invalidate it. diff 5314:e902f12a3af1 Wed Jan 02 03:20:00 EST 2008 Steve Reinhardt <stever@gmail.com> Add functional PrintReq command for memory-system debugging. |
H A D | port.hh | diff 5605:b194a80157e2 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: Major API change for the Event and EventQueue structures. Since the early days of M5, an event needed to know which event queue it was on, and that data was required at the time of construction of the event object. In the future parallelized M5, this sort of requirement does not work well since the proper event queue will not always be known at the time of construction of an event. Now, events are created, and the EventQueue itself has the schedule function, e.g. eventq->schedule(event, when). To simplify the syntax, I created a class called EventManager which holds a pointer to an EventQueue and provides the schedule interface that is a proxy for the EventQueue. The intent is that objects that frequently schedule events can be derived from EventManager and then they have the schedule interface. SimObject and Port are examples of objects that will become EventManagers. The end result is that any SimObject can just call schedule(event, when) and it will just call that SimObject's eventq->schedule function. Of course, some objects may have more than one EventQueue, so this interface might not be perfect for those, but they should be relatively few. diff 5494:85c8d296c1cb Sat Jun 28 13:19:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Backed out changeset 94a7bb476fca: caused memory leak. diff 5489:94a7bb476fca Sat Jun 21 01:04:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Generate more useful error messages for unconnected ports. Force all non-default ports to provide a name and an owner in the constructor. diff 5476:758c2413765a Mon Jun 16 00:34:00 EDT 2008 Nathan Binkert <nate@binkert.org> port: Clean up default port setup and port switchover code. diff 5314:e902f12a3af1 Wed Jan 02 03:20:00 EST 2008 Steve Reinhardt <stever@gmail.com> Add functional PrintReq command for memory-system debugging. |
/gem5/src/arch/x86/ | ||
H A D | utility.cc | diff 5648:e8abda6e0980 Sun Oct 12 14:08:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make the local APIC accessible through the memory system directly, and make the timer work. diff 5647:b06b49498c79 Sun Oct 12 12:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object. diff 5360:02a3af203516 Tue Feb 26 23:39:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> X86: Put in initial implementation of the local APIC. |
H A D | tlb.hh | diff 5360:02a3af203516 Tue Feb 26 23:39:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> X86: Put in initial implementation of the local APIC. diff 5358:e9acb84bbafb Tue Feb 26 23:38:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> TLB: Make a TLB base class and put a virtual demapPage function in it. diff 5357:eecb5fd0be62 Tue Feb 26 23:38:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> X86: Get PCI config space to work, and adjust address space prefix numbering scheme. |
/gem5/src/mem/cache/prefetch/ | ||
H A D | base.cc | diff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used, the primary identifier for a hardware context should be contextId(). The concept of threads within a CPU remains, in the form of threadId() because sometimes you need to know which context within a cpu to manipulate. diff 5338:e75d02a09806 Sun Feb 10 17:45:00 EST 2008 Steve Reinhardt <stever@gmail.com> Fix #include lines for renamed cache files. 5337:f81512eb8bdf Sun Feb 10 17:15:00 EST 2008 Steve Reinhardt <stever@gmail.com> Rename cache files for brevity and consistency with rest of tree. |
/gem5/src/cpu/o3/ | ||
H A D | cpu.hh | diff 5737:f43dbc09fad3 Mon Nov 10 14:51:00 EST 2008 Clint Smullen <cws3k@cs.virginia.edu> O3CPU: Make the instcount debugging stuff per-cpu. This is to prevent the assertion from firing if you have a large multicore. Also make sure that it's not compiled in when NDEBUG is defined diff 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch. diff 5707:da86e00f87a0 Thu Oct 23 16:49:00 EDT 2008 Lisa Hsu <hsul@eecs.umich.edu> s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos in comments. diff 5704:98224505352a Tue Oct 21 10:12:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Use the correct m5 style for things relating to interrupts. diff 5702:bf84e2fa05f7 Mon Oct 20 16:22:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Removing hwrei causes the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal call sys and thus the translation fails because the user is attempting to access a super page address. Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs. Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were removed since a great deal of manual patching would be required to only remove the hwrei change. diff 5640:c811ced9efc1 Sat Oct 11 03:17:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Eliminate the simPalCheck funciton. diff 5639:67cc7f0427e7 Sat Oct 11 05:27:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Eliminate the hwrei function. diff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API. For now, there is still a single global event queue, but this is necessary for making the steps towards a parallelized m5. diff 5595:6ebdae3f619b Thu Oct 09 03:08:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> O3: Generalize the O3 CPU object so it isn't split out by ISA. diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs. A whole bunch of stuff has been converted to use the new params stuff, but the CPU wasn't one of them. While we're at it, make some things a bit more stylish. Most of the work was done by Gabe, I just cleaned stuff up a bit more at the end. |
/gem5/src/cpu/ | ||
H A D | thread_state.hh | diff 5715:e8c1d4e669a7 Tue Nov 04 11:35:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> get rid of all instances of readTid() and getThreadNum(). Unify and eliminate redundancies with threadId() as their replacement. diff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used, the primary identifier for a hardware context should be contextId(). The concept of threads within a CPU remains, in the form of threadId() because sometimes you need to know which context within a cpu to manipulate. diff 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch. diff 5499:8bfc7650c344 Tue Jul 01 10:25:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Remove delVirtPort() and make getVirtPort() only return cached version. diff 5497:89a6483d7047 Tue Jul 01 10:24:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Make the cached virtPort have a thread context so it can do everything that a newly created one can. |
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