Searched hist:2008 (Results 251 - 275 of 494) sorted by relevance

<<11121314151617181920

/gem5/src/sim/
H A Dsim_object.hhdiff 5605:b194a80157e2 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: Major API change for the Event and EventQueue structures.

Since the early days of M5, an event needed to know which event queue
it was on, and that data was required at the time of construction of
the event object. In the future parallelized M5, this sort of
requirement does not work well since the proper event queue will not
always be known at the time of construction of an event. Now, events
are created, and the EventQueue itself has the schedule function,
e.g. eventq->schedule(event, when). To simplify the syntax, I created
a class called EventManager which holds a pointer to an EventQueue and
provides the schedule interface that is a proxy for the EventQueue.
The intent is that objects that frequently schedule events can be
derived from EventManager and then they have the schedule interface.
SimObject and Port are examples of objects that will become
EventManagers. The end result is that any SimObject can just call
schedule(event, when) and it will just call that SimObject's
eventq->schedule function. Of course, some objects may have more than
one EventQueue, so this interface might not be perfect for those, but
they should be relatively few.
diff 5530:bbfff6d0c42c Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Get rid of the remnants of the old style parameter configuration stuff.
diff 5491:c2509c70de08 Sat Jun 21 14:23:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> SimObject: Add in missing includes of <string> and fix minor style problem.
diff 5315:30997e988446 Wed Jan 02 16:46:00 EST 2008 Steve Reinhardt <stever@gmail.com> Additional comments and helper functions for PrintReq.
diff 5314:e902f12a3af1 Wed Jan 02 03:20:00 EST 2008 Steve Reinhardt <stever@gmail.com> Add functional PrintReq command for memory-system debugging.
H A Dsim_events.ccdiff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API.
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
diff 5501:b1beee9351a4 Fri Jul 11 00:35:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: Clean up the Event class so that it uses fewer bytes. This
will hopefullly allow it to fit in a cache line.
diff 5336:c7e21f4e5a2e Wed Feb 06 16:32:00 EST 2008 Stephen Hines <hines@cs.fsu.edu> Make the Event::description() a const function
H A Dsim_events.hhdiff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API.
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
diff 5336:c7e21f4e5a2e Wed Feb 06 16:32:00 EST 2008 Stephen Hines <hines@cs.fsu.edu> Make the Event::description() a const function
H A DProcess.pydiff 5514:9a903bf83a33 Wed Jul 23 17:41:00 EDT 2008 Michael Adler <Michael.Adler@intel.com> process: separate stderr from stdout
- Add the option of redirecting stderr to a file. With the old
behaviour, stderr would follow stdout if stdout was to a file, but
stderr went to the host stderr if stdout went to the host stdout. The
new default maintains stdout and stderr going to the host. Now the
two can specify different files, but they will share a file descriptor
if the name of the files is the same.
- Add --output and --errout options to se.py to go with --input.
diff 5361:e379019a1abd Wed Feb 27 00:35:00 EST 2008 Rick Strong <rstrong@cs.ucsd.edu> Configs: Make using Simpoints easier with some config files that support them easily
/gem5/src/arch/mips/
H A Dtlb.ccdiff 5736:426510e758ad Mon Nov 10 14:51:00 EST 2008 Nathan Binkert <nate@binkert.org> mem: update stuff for changes to Packet and Request
diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
diff 5358:e9acb84bbafb Tue Feb 26 23:38:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> TLB: Make a TLB base class and put a virtual demapPage function in it.
H A Dtlb.hhdiff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
diff 5358:e9acb84bbafb Tue Feb 26 23:38:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> TLB: Make a TLB base class and put a virtual demapPage function in it.
/gem5/src/arch/alpha/
H A Dutility.ccdiff 5569:baeee670d4ce Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Make a style pass over the whole arch/alpha directory.
diff 5499:8bfc7650c344 Tue Jul 01 10:25:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Remove delVirtPort() and make getVirtPort() only return cached version.
diff 5498:2af99511ded4 Tue Jul 01 10:24:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Change everything to use the cached virtPort rather than created their own each time.
This appears to work, but I don't want to commit it until it gets tested a lot more.
I haven't deleted the functionality in this patch that will come later, but one question
is how to enforce encourage objects that call getVirtPort() to not cache the virtual port
since if the CPU changes out from under them it will be worse than useless. Perhaps a null
function like delVirtPort() is still useful in that case.
H A Dprocess.hhdiff 5759:6e65ac8a2c80 Fri Dec 05 00:09:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> This brings M5 closer to modernity - the kernel being advertised is newer so it won't die on binaries compiled with newer glibc's, and enables use of TLS-toolchain built binaries for ALPHA_SE by putting auxiliary vectors on the stack. There are some comments in the code to help. Finally, stats changes for ALPHA are from slight perturbations to the initial stack frame, all minimal diffs.
diff 5569:baeee670d4ce Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Make a style pass over the whole arch/alpha directory.
H A Dev5.ccdiff 5702:bf84e2fa05f7 Mon Oct 20 16:22:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Removing hwrei causes
the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal
call sys and thus the translation fails because the user is attempting to access a super page address.

Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think
this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs.

Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were
removed since a great deal of manual patching would be required to only remove the hwrei change.
diff 5640:c811ced9efc1 Sat Oct 11 03:17:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Eliminate the simPalCheck funciton.
diff 5639:67cc7f0427e7 Sat Oct 11 05:27:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Eliminate the hwrei function.
diff 5569:baeee670d4ce Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Make a style pass over the whole arch/alpha directory.
diff 5568:d14250d688d2 Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> alpha: Clean up namespace usage.
diff 5567:8fc3b004b0df Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> arch: TheISA shouldn't really ever be used in the arch directory.
We should always refer to the specific ISA in that arch directory.
This is especially necessary if we're ever going to make it to the
point where we actually have heterogeneous systems.
diff 5566:3440c9ad49b4 Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> alpha: Get rid fo the namespace called EV5.
We're never going to do an alpha platform other than the one we've got.
diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
/gem5/src/mem/cache/
H A Dcache.hhdiff 6122:9af6fb59752f Wed Jul 16 14:10:00 EDT 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> mem: use single BadAddr responder per system.
Previously there was one per bus, which caused some coherence problems
when more than one decided to respond. Now there is just one on
the main memory bus. The default bus responder on all other buses
is now the downstream cache's cpu_side port. Caches no longer need
to do address range filtering; instead, we just have a simple flag
to prevent snoops from propagating to the I/O bus.
diff 5707:da86e00f87a0 Thu Oct 23 16:49:00 EDT 2008 Lisa Hsu <hsul@eecs.umich.edu> s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos in
comments.
diff 5706:2cc2387049bc Thu Oct 23 16:49:00 EDT 2008 Lisa Hsu <hsul@eecs.umich.edu> probe function no longer used anywhere.
diff 5699:ab3067124402 Tue Oct 14 17:22:00 EDT 2008 Lisa Hsu <hsul@eecs.umich.edu> This function declaration isn't used anywhere.
HG: user: Lisa Hsu <hsul@eecs.umich.edu> HG: branch default HG: changed
src/mem/cache/cache.hh
diff 5494:85c8d296c1cb Sat Jun 28 13:19:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Backed out changeset 94a7bb476fca: caused memory leak.
diff 5489:94a7bb476fca Sat Jun 21 01:04:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Generate more useful error messages for unconnected ports.
Force all non-default ports to provide a name and an
owner in the constructor.
diff 5388:3b4772ca8368 Tue Mar 25 10:01:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Fix handling of writeback-induced writebacks in atomic mode.
diff 5365:49bef92749d1 Tue Feb 26 23:17:00 EST 2008 Steve Reinhardt <stever@gmail.com> Cache: better comments particularly regarding writeback situation.
diff 5350:67e5e13f4146 Sat Feb 16 14:58:00 EST 2008 Steve Reinhardt <stever@gmail.com> Make L2+ caches allocate new block for writeback misses
instead of forwarding down the line.
diff 5338:e75d02a09806 Sun Feb 10 17:45:00 EST 2008 Steve Reinhardt <stever@gmail.com> Fix #include lines for renamed cache files.
H A Dmshr_queue.hhdiff 5338:e75d02a09806 Sun Feb 10 17:45:00 EST 2008 Steve Reinhardt <stever@gmail.com> Fix #include lines for renamed cache files.
5337:f81512eb8bdf Sun Feb 10 17:15:00 EST 2008 Steve Reinhardt <stever@gmail.com> Rename cache files for brevity and consistency with rest of tree.
/gem5/src/dev/x86/
H A Di82094aa.hhdiff 5657:7539092b28ac Sun Oct 12 16:54:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create a mechanism for the IO APIC to access I8259 vectors.
diff 5651:7f0c8006c3d7 Sun Oct 12 16:28:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make APICs communicate through the memory system.
5643:2b1611137af4 Sat Oct 11 19:08:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create an IO APIC device.
/gem5/tests/configs/
H A Dtsunami-o3-dual.pydiff 6122:9af6fb59752f Wed Jul 16 14:10:00 EDT 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> mem: use single BadAddr responder per system.
Previously there was one per bus, which caused some coherence problems
when more than one decided to respond. Now there is just one on
the main memory bus. The default bus responder on all other buses
is now the downstream cache's cpu_side port. Caches no longer need
to do address range filtering; instead, we just have a simple flag
to prevent snoops from propagating to the I/O bus.
5703:7478bc206949 Mon Oct 20 19:00:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
H A Dtsunami-o3.pydiff 6122:9af6fb59752f Wed Jul 16 14:10:00 EDT 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> mem: use single BadAddr responder per system.
Previously there was one per bus, which caused some coherence problems
when more than one decided to respond. Now there is just one on
the main memory bus. The default bus responder on all other buses
is now the downstream cache's cpu_side port. Caches no longer need
to do address range filtering; instead, we just have a simple flag
to prevent snoops from propagating to the I/O bus.
5703:7478bc206949 Mon Oct 20 19:00:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> Regression: Add single and dual boot O3 regressions. They both take about 8 minutes to complete.
/gem5/src/arch/mips/isa/formats/
H A Dutil.isadiff 5745:6b0f8306704b Fri Nov 14 07:55:00 EST 2008 Nathan Binkert <nate@binkert.org> Fix a bunch of bugs I introduced when I changed the flags stuff for packets.
I did some of the flags and assertions wrong. Thanks to Brad Beckmann
for pointing this out. I should have run the opt regressions instead
of the fast. I also screwed up some of the logical functions in the Flags
class.
diff 5736:426510e758ad Mon Nov 10 14:51:00 EST 2008 Nathan Binkert <nate@binkert.org> mem: update stuff for changes to Packet and Request
/gem5/src/arch/alpha/isa/
H A Dfp.isadiff 5568:d14250d688d2 Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> alpha: Clean up namespace usage.
diff 5566:3440c9ad49b4 Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> alpha: Get rid fo the namespace called EV5.
We're never going to do an alpha platform other than the one we've got.
/gem5/src/dev/alpha/
H A Dtsunami_cchip.ccdiff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used,
the primary identifier for a hardware context should be contextId(). The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
diff 5570:13592d41f290 Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> gcc: Add extra parens to quell warnings.
Even though we're not incorrect about operator precedence, let's add
some parens in some particularly confusing places to placate GCC 4.3
so that we don't have to turn the warning off. Agreed that this is a
bit of a pain for those users who get the order of operations correct,
but it is likely to prevent bugs in certain cases.
/gem5/src/arch/sparc/
H A Dinterrupts.hhdiff 5704:98224505352a Tue Oct 21 10:12:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Use the correct m5 style for things relating to interrupts.
diff 5647:b06b49498c79 Sun Oct 12 12:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.
/gem5/src/arch/sparc/linux/
H A Dsyscalls.ccdiff 5748:f28f020f3006 Sat Nov 15 12:30:00 EST 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> syscalls: fix latent brk/obreak bug.
Bogus calls to ChunkGenerator with negative size were triggering
a new assertion that was added there.
Also did a little renaming and cleanup in the process.
diff 5513:8631b29873a2 Wed Jul 23 17:41:00 EDT 2008 Michael Adler <Michael.Adler@intel.com> syscalls: Add a bunch of missing system calls.
readlink, umask, truncate, ftruncate, mkdir, and getcwd.
/gem5/src/cpu/
H A DBaseCPU.pydiff 5780:50c9d48de3ca Wed Dec 17 12:51:00 EST 2008 Steve Reinhardt <steve.reinhardt@amd.com> Make Alpha pseudo-insts available from SE mode.
diff 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
diff 5658:55f9947891fb Sun Oct 12 17:01:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Fix the ordering of special physical address ranges.
diff 5651:7f0c8006c3d7 Sun Oct 12 16:28:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make APICs communicate through the memory system.
diff 5648:e8abda6e0980 Sun Oct 12 14:08:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make the local APIC accessible through the memory system directly, and make the timer work.
diff 5647:b06b49498c79 Sun Oct 12 12:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.
diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs.
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them. While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
diff 5335:69d45f5f21a2 Tue Feb 05 23:44:00 EST 2008 Stephen Hines <hines@cs.fsu.edu> Add base ARM code to M5
/gem5/src/arch/x86/isa/
H A Dmacroop.isadiff 5692:0d6addcde185 Mon Oct 13 02:29:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Set the delayed commit flag in x86 microops appropriately.
diff 5666:e7925fa8f0d6 Sun Oct 12 20:48:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make X86's microcode ROM actually do something.
/gem5/src/cpu/simple/
H A Dtiming.hhdiff 5744:342cbc20a188 Fri Nov 14 02:30:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Refactor read/write in the simple timing CPU.
diff 5728:9574f561dfa2 Mon Nov 10 00:56:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Make unaligned accesses work in the timing simple CPU.
diff 5710:b44dd45bd604 Mon Oct 27 18:18:00 EDT 2008 Clint Smullen <cws3k@cs.virginia.edu> CPU: The API change to EventWrapper did not get propagated to the entirety of TimingSimpleCPU.
The constructor no-longer schedules an event at construction and the implict conversion between int and bool was allowing the old code to compile without warning.

Signed-off By: Ali Saidi
diff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API.
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs.
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them. While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
diff 5496:6899b894166f Tue Jul 01 10:24:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> After a checkpoint (and thus a stats reset), the not_idle_fraction/notIdleFraction statistic is really wrong.
The notIdleFraction statistic isn't updated when the statistics reset, probably because the cpu Status information
was pulled into the atomic and timing cpus. This changeset pulls Status back into the BaseSimpleCPU object. Anyone
care to comment on the odd naming of the Status instance? It shouldn't just be status because that is confusing
with Port::Status, but _status seems a bit strage too.
diff 5336:c7e21f4e5a2e Wed Feb 06 16:32:00 EST 2008 Stephen Hines <hines@cs.fsu.edu> Make the Event::description() a const function
diff 5315:30997e988446 Wed Jan 02 16:46:00 EST 2008 Steve Reinhardt <stever@gmail.com> Additional comments and helper functions for PrintReq.
H A Dtiming.ccdiff 5744:342cbc20a188 Fri Nov 14 02:30:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Refactor read/write in the simple timing CPU.
diff 5728:9574f561dfa2 Mon Nov 10 00:56:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Make unaligned accesses work in the timing simple CPU.
diff 5726:17157c5f7e15 Mon Nov 10 00:55:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make the timing simple CPU handle variable length instructions.
diff 5714:76abee886def Sun Nov 02 21:57:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Add in Context IDs to the simulator. From now on, cpuId is almost never used,
the primary identifier for a hardware context should be contextId(). The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
diff 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
diff 5710:b44dd45bd604 Mon Oct 27 18:18:00 EDT 2008 Clint Smullen <cws3k@cs.virginia.edu> CPU: The API change to EventWrapper did not get propagated to the entirety of TimingSimpleCPU.
The constructor no-longer schedules an event at construction and the implict conversion between int and bool was allowing the old code to compile without warning.

Signed-off By: Ali Saidi
diff 5669:cbac62a59686 Sun Oct 12 22:32:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Don't fetch in the simple CPU if you're in the ROM.
diff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API.
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs.
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them. While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
diff 5507:52bcc301b467 Tue Jul 15 14:38:00 EDT 2008 Steve Reinhardt <stever@gmail.com> Use ReadResp instead of LoadLockedResp for LoadLockedReq responses.
/gem5/src/cpu/o3/
H A Dcpu_policy.hhdiff 5553:de0fa35df4cb Mon Sep 22 11:25:00 EDT 2008 Nathan Binkert <nate@binkert.org> gcc: Version 4.3 is pretty anal about shadowing types, placate it.
In the future, it would be nice to put the O3CPU into its own
namespace so that we don't end up hardcoding pointers to the global
namespace.
/gem5/src/arch/alpha/freebsd/
H A Dsystem.hhdiff 5569:baeee670d4ce Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Make a style pass over the whole arch/alpha directory.

Completed in 260 milliseconds

<<11121314151617181920