Searched hist:2008 (Results 101 - 125 of 494) sorted by relevance

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/gem5/src/arch/x86/
H A Dsystem.hhdiff 5627:31eac202dbd1 Sat Oct 11 02:43:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create SimObjects in python and C++ to represent the ACPI system description tables.
diff 5625:ea7d3676ac8d Sat Oct 11 02:39:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create SimObjects in python and C++ to represent the Intel MP tables.
diff 5615:1c4b9b1aa500 Fri Oct 10 06:50:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Turn SMBios structures into simobjects.
diff 5334:5136aad50b97 Wed Jan 23 15:28:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> X86: Put an SMBios/DMI table in memory.
This is basically just the header right now, but there's an untested
mechanism in place to fill out the table and make sure everything is
updated correctly.
H A DSConscriptdiff 5680:39ae093fb4eb Mon Oct 13 01:42:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement entering an interrupt in microcode.
diff 5659:f4b9c344d1ca Sun Oct 12 18:31:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement CPUID with a magical function instead of microcode.
diff 5649:0e9c904551c1 Sun Oct 12 03:07:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Add a LocalApic trace flag.
diff 5647:b06b49498c79 Sun Oct 12 12:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.
diff 5612:1bd333953e49 Fri Oct 10 06:50:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Move the smbios objects into a folder for BIOS objects.
diff 5450:25e395a87745 Thu Jun 12 00:58:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make the e820 table manually or automatically configurable from python.
diff 5406:fc680749b40e Wed Jun 11 10:54:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> SCons: Fix more SCons version issues
diff 5359:8c6ff200e4c1 Tue Feb 26 23:39:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement the INVLPG instruction and the TIA microop.
diff 5334:5136aad50b97 Wed Jan 23 15:28:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> X86: Put an SMBios/DMI table in memory.
This is basically just the header right now, but there's an untested
mechanism in place to fill out the table and make sure everything is
updated correctly.
H A Demulenv.ccdiff 5616:05fd71ca96db Fri Oct 10 13:15:00 EDT 2008 Nathan Binkert <nate@binkert.org> misc: remove #include <cassert> from misc.hh since not everyone needs it.
diff 5570:13592d41f290 Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> gcc: Add extra parens to quell warnings.
Even though we're not incorrect about operator precedence, let's add
some parens in some particularly confusing places to placate GCC 4.3
so that we don't have to turn the warning off. Agreed that this is a
bit of a pain for those users who get the order of operations correct,
but it is likely to prevent bugs in certain cases.
/gem5/src/arch/x86/isa/insts/system/
H A Dinvlpg.py5359:8c6ff200e4c1 Tue Feb 26 23:39:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement the INVLPG instruction and the TIA microop.
/gem5/src/base/loader/
H A Dcoff_sym.hdiff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
H A Dhex_file.ccdiff 5545:d7c7b6752e2c Fri Sep 19 12:11:00 EDT 2008 Nathan Binkert <nate@binkert.org> Check the return value of I/O operations for failure
diff 5541:bb31ea8583d8 Mon Sep 08 21:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: This file hugely violated the M5 style.
Remove a bunch of unused cruft from the interface while we're at it
/gem5/src/arch/x86/isa/
H A Dmicroasm.isadiff 5682:6f1cab082ba7 Mon Oct 13 01:55:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Add wrval/rdval microops for reading significant miscregs.
diff 5676:cca6726c0d88 Sun Oct 12 23:44:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement local labels for the ROM that actually refer into the ROM.
diff 5674:4a4f20dfbc60 Sun Oct 12 23:33:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Add a check type for interrupt gates.
diff 5671:379f926bc5ff Sun Oct 12 23:17:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Let the microassembler know about the microcode only H segment.
diff 5667:78b94954f66a Sun Oct 12 20:52:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create a handy way to access labels from the ROM in microcode.
diff 5666:e7925fa8f0d6 Sun Oct 12 20:48:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make X86's microcode ROM actually do something.
diff 5428:5a27fea50fee Thu Jun 12 00:50:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Change what the microop chks does.
Instead of computing the segment descriptor address, this now checks if a
selector value/descriptor are legal for a particular purpose.
diff 5426:0bdcc60ccc45 Thu Jun 12 00:49:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Add microops and supporting code to manipulate the whole rflags register.
diff 5326:7e4cef0e528b Sat Jan 12 06:41:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> X86: Redo the bit test instructions.
/gem5/src/dev/alpha/
H A Dtsunami_io.ccdiff 5635:b65e232e7755 Sat Oct 11 04:49:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Devices: Make the Intel8254Timer device only use pointers to its counters.
diff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API.
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
diff 5455:d63afee4c46a Thu Jun 12 01:54:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Alpha: Get rid of an old include of a non-existant file.
diff 5443:394d180e8c04 Thu Jun 12 00:54:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Dev: Seperate the 8254 timer from tsunami and use it in that and the PC.
diff 5392:c3a45fac35f8 Tue Mar 25 02:15:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Devices: Separate out the MC146818 RTC so both Alpha and X86 can use it.
diff 5336:c7e21f4e5a2e Wed Feb 06 16:32:00 EST 2008 Stephen Hines <hines@cs.fsu.edu> Make the Event::description() a const function
H A Dtsunami_io.hhdiff 5606:6da7a58b0bc8 Thu Oct 09 07:58:00 EDT 2008 Nathan Binkert <nate@binkert.org> eventq: convert all usage of events to use the new API.
For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
diff 5443:394d180e8c04 Thu Jun 12 00:54:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Dev: Seperate the 8254 timer from tsunami and use it in that and the PC.
diff 5392:c3a45fac35f8 Tue Mar 25 02:15:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Devices: Separate out the MC146818 RTC so both Alpha and X86 can use it.
diff 5336:c7e21f4e5a2e Wed Feb 06 16:32:00 EST 2008 Stephen Hines <hines@cs.fsu.edu> Make the Event::description() a const function
/gem5/src/arch/x86/isa/microops/
H A Dmicroops.isadiff 5661:443e6f925027 Sun Oct 12 18:33:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create a SeqOp class of microops and make Br one of them.
diff 5425:4226f6c2d03c Thu Jun 12 00:49:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Add microops which panic, fatal, warn, and warn_once.
/gem5/util/
H A Dtracediffdiff 5751:54cb03a1a577 Mon Nov 17 14:22:00 EST 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> Minor tracediff bug fixes.
diff 5725:61c838ecc225 Thu Nov 06 23:23:00 EST 2008 Steve Reinhardt <Steve.Reinhardt@amd.com> tracediff: add '#' support for sub-arg alternatives, '-n' param
/gem5/src/arch/mips/
H A Dsystem.ccdiff 5566:3440c9ad49b4 Sun Sep 28 00:03:00 EDT 2008 Nathan Binkert <nate@binkert.org> alpha: Get rid fo the namespace called EV5.
We're never going to do an alpha platform other than the one we've got.
diff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
H A Dinterrupts.hhdiff 5704:98224505352a Tue Oct 21 10:12:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Use the correct m5 style for things relating to interrupts.
diff 5646:0a488a147fb8 Sun Oct 12 11:24:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Eliminate the get_vec function.
H A Dinterrupts.ccdiff 5704:98224505352a Tue Oct 21 10:12:00 EDT 2008 Nathan Binkert <nate@binkert.org> style: Use the correct m5 style for things relating to interrupts.
diff 5646:0a488a147fb8 Sun Oct 12 11:24:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> CPU: Eliminate the get_vec function.
/gem5/src/arch/x86/isa/insts/general_purpose/data_transfer/
H A Dstack_operations.pydiff 5661:443e6f925027 Sun Oct 12 18:33:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create a SeqOp class of microops and make Br one of them.
diff 5432:e1e42f18d376 Thu Jun 12 00:51:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make pushes and pops use the stack size instead of the data size.
/gem5/src/arch/
H A Dmicro_asm.pydiff 5594:7ef21c6c76bb Thu Oct 09 03:07:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Microcode: Fix a silent typo error in the microcode assembler.
diff 5593:6c00fcf12fdf Thu Oct 09 03:07:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Microcode: Fix a very old bug with parsing external labels in microcode.
/gem5/src/cpu/
H A DCheckerCPU.pydiff 5536:17c0c17726ff Mon Aug 18 13:50:00 EDT 2008 Richard Strong<rstrong@hp.com> Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was done to be consistent with its
python type of a latency. In addition, the multiple definitions of profile in the different cpu models caused
problems for intialization of the interval value. If a child class's profile value was defined, the parent
BaseCPU::ProfileEvent interval field would be initialized with a garbage value. The fix was to remove the
multiple redifitions of profile in the child CPU classes.
5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs.
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them. While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
/gem5/src/mem/cache/prefetch/
H A Dtagged.hhdiff 5338:e75d02a09806 Sun Feb 10 17:45:00 EST 2008 Steve Reinhardt <stever@gmail.com> Fix #include lines for renamed cache files.
5337:f81512eb8bdf Sun Feb 10 17:15:00 EST 2008 Steve Reinhardt <stever@gmail.com> Rename cache files for brevity and consistency with rest of tree.
/gem5/src/python/m5/util/
H A Djobfile.pydiff 5618:1abb23c038d5 Fri Oct 10 13:15:00 EDT 2008 Nathan Binkert <nate@binkert.org> jobfile: Add support for dictionaries as jobfile options.
If the same dictionary option is seen in several options, those
dictionaries are composed. If you define the same dictionary key in
multiple options, the system flags an error.
Also, clean up the jobfile code so that it is more debuggable.
5467:6d9df90d70d7 Sat Jun 14 23:19:00 EDT 2008 Nathan Binkert <nate@binkert.org> python: Move various utility classes into a new m5.util package so
they're all in the same place. This also involves having just one
jobfile.py and moving it into the utils directory to avoid
duplication. Lots of improvements to the utility as well.
/gem5/src/dev/x86/
H A Di8254.ccdiff 5642:102cf92b8ea9 Sat Oct 11 18:15:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Set up a mechanism for the I8254 timer to cause interrupts.
5636:27a9526eea1f Sat Oct 11 05:16:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Change I8254 and PCSpeaker devices from subdevices to SimObjects and eliminate subdevices.
H A DI82094AA.pydiff 5651:7f0c8006c3d7 Sun Oct 12 16:28:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make APICs communicate through the memory system.
5643:2b1611137af4 Sat Oct 11 19:08:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create an IO APIC device.
/gem5/src/cpu/o3/
H A Disa_specific.hhdiff 5597:e2983d751be4 Thu Oct 09 03:10:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> O3: Generaize the O3 IMPL class so it isn't split out by ISA.
diff 5596:cdc8893c649e Thu Oct 09 03:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> O3: Generaize the O3 dynamic instruction class so it isn't split out by ISA.
diff 5595:6ebdae3f619b Thu Oct 09 03:08:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> O3: Generalize the O3 CPU object so it isn't split out by ISA.
diff 5529:9ae69b9cd7fd Mon Aug 11 03:22:00 EDT 2008 Nathan Binkert <nate@binkert.org> params: Convert the CPU objects to use the auto generated param structs.
A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them. While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
/gem5/src/sim/
H A Dasync.hhdiff 5543:3af77710f397 Wed Sep 10 14:26:00 EDT 2008 Ali Saidi <saidi@eecs.umich.edu> style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs
/gem5/src/arch/x86/isa/insts/general_purpose/arithmetic/
H A Dmultiply_and_divide.pydiff 5661:443e6f925027 Sun Oct 12 18:33:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create a SeqOp class of microops and make Br one of them.
/gem5/src/arch/x86/isa/insts/general_purpose/compare_and_test/
H A Dbit_test.pydiff 5326:7e4cef0e528b Sat Jan 12 06:41:00 EST 2008 Gabe Black <gblack@eecs.umich.edu> X86: Redo the bit test instructions.

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