1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 *          Andrew Schultz
30 *          Miguel Serrano
31 */
32
33/** @file
34 * Tsunami I/O Space mapping including RTC/timer interrupts
35 */
36
37#ifndef __DEV_TSUNAMI_IO_HH__
38#define __DEV_TSUNAMI_IO_HH__
39
40#include "dev/alpha/tsunami.hh"
41#include "dev/alpha/tsunami_cchip.hh"
42#include "dev/intel_8254_timer.hh"
43#include "dev/io_device.hh"
44#include "dev/mc146818.hh"
45#include "params/TsunamiIO.hh"
46#include "sim/eventq.hh"
47
48/**
49 * Tsunami I/O device is a catch all for all the south bridge stuff we care
50 * to implement.
51 */
52class TsunamiIO : public BasicPioDevice
53{
54
55  protected:
56
57    class RTC : public MC146818
58    {
59      public:
60        Tsunami *tsunami;
61        RTC(const std::string &n, const TsunamiIOParams *p);
62
63      protected:
64        void handleEvent()
65        {
66            //Actually interrupt the processor here
67            tsunami->cchip->postRTC();
68        }
69    };
70
71    /** Mask of the PIC1 */
72    uint8_t mask1;
73
74    /** Mask of the PIC2 */
75    uint8_t mask2;
76
77    /** Mode of PIC1. Not used for anything */
78    uint8_t mode1;
79
80    /** Mode of PIC2. Not used for anything */
81    uint8_t mode2;
82
83    /** Raw PIC interrupt register before masking */
84    uint8_t picr; //Raw PIC interrput register
85
86    /** Is the pic interrupting right now or not. */
87    bool picInterrupting;
88
89    /** A pointer to the Tsunami device which be belong to */
90    Tsunami *tsunami;
91
92    /** Intel 8253 Periodic Interval Timer */
93    Intel8254Timer pitimer;
94
95    RTC rtc;
96
97    uint8_t rtcAddr;
98
99    /** The interval is set via two writes to the PIT.
100     * This variable contains a flag as to how many writes have happened, and
101     * the time so far.
102     */
103    uint16_t timerData;
104
105  public:
106    /**
107     * Return the freqency of the RTC
108     * @return interrupt rate of the RTC
109     */
110    Tick frequency() const;
111
112  public:
113    typedef TsunamiIOParams Params;
114    /**
115     * Initialize all the data for devices supported by Tsunami I/O.
116     * @param p pointer to Params struct
117     */
118    TsunamiIO(const Params *p);
119
120    const Params *
121    params() const
122    {
123        return dynamic_cast<const Params *>(_params);
124    }
125
126    Tick read(PacketPtr pkt) override;
127    Tick write(PacketPtr pkt) override;
128
129    /**
130     * Post an PIC interrupt to the CPU via the CChip
131     * @param bitvector interrupt to post.
132     */
133    void postPIC(uint8_t bitvector);
134
135    /**
136     * Clear a posted interrupt
137     * @param bitvector interrupt to clear
138     */
139    void clearPIC(uint8_t bitvector);
140
141    void serialize(CheckpointOut &cp) const override;
142    void unserialize(CheckpointIn &cp) override;
143
144    /**
145     * Start running.
146     */
147    void startup() override;
148
149};
150
151#endif // __DEV_TSUNAMI_IO_HH__
152