Searched hist:13627 (Results 1 - 17 of 17) sorted by relevance
/gem5/src/cpu/pred/ | ||
H A D | loop_predictor.cc | 13627:ec1395943cd2 Mon Jan 28 17:59:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> cpu: Made the Loop Predictor a SimObject The Loop Predictor implementation is now a SimObject so that other branch predictors can easily use it (including LTAGE, which is now using it). It has also been updated with the latest available loop predictor implementation from Andre Seznec: http://www.irisa.fr/alf/downloads/seznec/TAGE-GSC-IMLI.tar Change-Id: I60ad079a2c49b00a1f84d5cfd3611631883a4b57 Reviewed-on: https://gem5-review.googlesource.com/c/15775 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
H A D | loop_predictor.hh | 13627:ec1395943cd2 Mon Jan 28 17:59:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> cpu: Made the Loop Predictor a SimObject The Loop Predictor implementation is now a SimObject so that other branch predictors can easily use it (including LTAGE, which is now using it). It has also been updated with the latest available loop predictor implementation from Andre Seznec: http://www.irisa.fr/alf/downloads/seznec/TAGE-GSC-IMLI.tar Change-Id: I60ad079a2c49b00a1f84d5cfd3611631883a4b57 Reviewed-on: https://gem5-review.googlesource.com/c/15775 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
H A D | ltage.hh | diff 13627:ec1395943cd2 Mon Jan 28 17:59:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> cpu: Made the Loop Predictor a SimObject The Loop Predictor implementation is now a SimObject so that other branch predictors can easily use it (including LTAGE, which is now using it). It has also been updated with the latest available loop predictor implementation from Andre Seznec: http://www.irisa.fr/alf/downloads/seznec/TAGE-GSC-IMLI.tar Change-Id: I60ad079a2c49b00a1f84d5cfd3611631883a4b57 Reviewed-on: https://gem5-review.googlesource.com/c/15775 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
H A D | ltage.cc | diff 13627:ec1395943cd2 Mon Jan 28 17:59:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> cpu: Made the Loop Predictor a SimObject The Loop Predictor implementation is now a SimObject so that other branch predictors can easily use it (including LTAGE, which is now using it). It has also been updated with the latest available loop predictor implementation from Andre Seznec: http://www.irisa.fr/alf/downloads/seznec/TAGE-GSC-IMLI.tar Change-Id: I60ad079a2c49b00a1f84d5cfd3611631883a4b57 Reviewed-on: https://gem5-review.googlesource.com/c/15775 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
H A D | SConscript | diff 13627:ec1395943cd2 Mon Jan 28 17:59:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> cpu: Made the Loop Predictor a SimObject The Loop Predictor implementation is now a SimObject so that other branch predictors can easily use it (including LTAGE, which is now using it). It has also been updated with the latest available loop predictor implementation from Andre Seznec: http://www.irisa.fr/alf/downloads/seznec/TAGE-GSC-IMLI.tar Change-Id: I60ad079a2c49b00a1f84d5cfd3611631883a4b57 Reviewed-on: https://gem5-review.googlesource.com/c/15775 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
H A D | BranchPredictor.py | diff 13627:ec1395943cd2 Mon Jan 28 17:59:00 EST 2019 Javier Bueno <javier.bueno@metempsy.com> cpu: Made the Loop Predictor a SimObject The Loop Predictor implementation is now a SimObject so that other branch predictors can easily use it (including LTAGE, which is now using it). It has also been updated with the latest available loop predictor implementation from Andre Seznec: http://www.irisa.fr/alf/downloads/seznec/TAGE-GSC-IMLI.tar Change-Id: I60ad079a2c49b00a1f84d5cfd3611631883a4b57 Reviewed-on: https://gem5-review.googlesource.com/c/15775 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
/gem5/src/arch/sparc/ | ||
H A D | decoder.hh | diff 13583:f7482392b097 Thu Oct 18 20:50:00 EDT 2018 Gabe Black <gabeblack@google.com> sparc: Get rid of some register type definitions. These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been supplanted by the global types RegVal and FloatRegVal. Change-Id: I956abfc7b439b083403e1a0d01e0bb35020bde44 Reviewed-on: https://gem5-review.googlesource.com/c/13627 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
H A D | isa.cc | diff 13583:f7482392b097 Thu Oct 18 20:50:00 EDT 2018 Gabe Black <gabeblack@google.com> sparc: Get rid of some register type definitions. These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been supplanted by the global types RegVal and FloatRegVal. Change-Id: I956abfc7b439b083403e1a0d01e0bb35020bde44 Reviewed-on: https://gem5-review.googlesource.com/c/13627 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
H A D | registers.hh | diff 13583:f7482392b097 Thu Oct 18 20:50:00 EDT 2018 Gabe Black <gabeblack@google.com> sparc: Get rid of some register type definitions. These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been supplanted by the global types RegVal and FloatRegVal. Change-Id: I956abfc7b439b083403e1a0d01e0bb35020bde44 Reviewed-on: https://gem5-review.googlesource.com/c/13627 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
H A D | isa.hh | diff 13583:f7482392b097 Thu Oct 18 20:50:00 EDT 2018 Gabe Black <gabeblack@google.com> sparc: Get rid of some register type definitions. These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been supplanted by the global types RegVal and FloatRegVal. Change-Id: I956abfc7b439b083403e1a0d01e0bb35020bde44 Reviewed-on: https://gem5-review.googlesource.com/c/13627 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
H A D | process.hh | diff 13583:f7482392b097 Thu Oct 18 20:50:00 EDT 2018 Gabe Black <gabeblack@google.com> sparc: Get rid of some register type definitions. These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been supplanted by the global types RegVal and FloatRegVal. Change-Id: I956abfc7b439b083403e1a0d01e0bb35020bde44 Reviewed-on: https://gem5-review.googlesource.com/c/13627 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
H A D | faults.hh | diff 13583:f7482392b097 Thu Oct 18 20:50:00 EDT 2018 Gabe Black <gabeblack@google.com> sparc: Get rid of some register type definitions. These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been supplanted by the global types RegVal and FloatRegVal. Change-Id: I956abfc7b439b083403e1a0d01e0bb35020bde44 Reviewed-on: https://gem5-review.googlesource.com/c/13627 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
H A D | faults.cc | diff 13583:f7482392b097 Thu Oct 18 20:50:00 EDT 2018 Gabe Black <gabeblack@google.com> sparc: Get rid of some register type definitions. These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been supplanted by the global types RegVal and FloatRegVal. Change-Id: I956abfc7b439b083403e1a0d01e0bb35020bde44 Reviewed-on: https://gem5-review.googlesource.com/c/13627 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
H A D | process.cc | diff 13583:f7482392b097 Thu Oct 18 20:50:00 EDT 2018 Gabe Black <gabeblack@google.com> sparc: Get rid of some register type definitions. These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been supplanted by the global types RegVal and FloatRegVal. Change-Id: I956abfc7b439b083403e1a0d01e0bb35020bde44 Reviewed-on: https://gem5-review.googlesource.com/c/13627 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
H A D | ua2005.cc | diff 13583:f7482392b097 Thu Oct 18 20:50:00 EDT 2018 Gabe Black <gabeblack@google.com> sparc: Get rid of some register type definitions. These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been supplanted by the global types RegVal and FloatRegVal. Change-Id: I956abfc7b439b083403e1a0d01e0bb35020bde44 Reviewed-on: https://gem5-review.googlesource.com/c/13627 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
/gem5/src/arch/sparc/linux/ | ||
H A D | syscalls.cc | diff 13583:f7482392b097 Thu Oct 18 20:50:00 EDT 2018 Gabe Black <gabeblack@google.com> sparc: Get rid of some register type definitions. These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been supplanted by the global types RegVal and FloatRegVal. Change-Id: I956abfc7b439b083403e1a0d01e0bb35020bde44 Reviewed-on: https://gem5-review.googlesource.com/c/13627 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
/gem5/src/arch/sparc/isa/ | ||
H A D | decoder.isa | diff 13583:f7482392b097 Thu Oct 18 20:50:00 EDT 2018 Gabe Black <gabeblack@google.com> sparc: Get rid of some register type definitions. These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been supplanted by the global types RegVal and FloatRegVal. Change-Id: I956abfc7b439b083403e1a0d01e0bb35020bde44 Reviewed-on: https://gem5-review.googlesource.com/c/13627 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
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