| /gem5/src/dev/arm/ |
| H A D | smmu_v3.cc | 236 Tick delay = 0; local
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| H A D | gic_v3_its.cc | 1194 Tick delay = 0; local
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| H A D | gic_v3_its.hh | 66 Tick delay; member in struct:ItsAction
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| /gem5/src/systemc/tlm_bridge/ |
| H A D | tlm_to_gem5.cc | 110 auto delay = sc_core::SC_ZERO_TIME; local
292 auto delay = local
398 auto delay = sc_core::sc_time::from_value(pkt->payloadDelay); local
119 sendBeginResp(tlm::tlm_generic_payload &trans, sc_core::sc_time &delay) argument
240 nb_transport_fw( tlm::tlm_generic_payload &trans, tlm::tlm_phase &phase, sc_core::sc_time &delay) argument
[all...] |
| /gem5/ext/mcpat/cacti/ |
| H A D | decoder.h | 66 double delay; member in class:Decoder
232 double delay; member in class:Driver
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| H A D | decoder.cc | 1388 double delay; local
[all...] |
| H A D | wire.cc | 720 wire_model(double space, double size, double *delay) argument
[all...] |
| /gem5/ext/systemc/src/tlm_utils/ |
| H A D | tlm2_base_protocol_checker.h | 198 nb_transport_fw( tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay) argument
215 nb_transport_bw( tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay) argument
345 b_transport_pre_checks( tlm::tlm_generic_payload& trans, sc_core::sc_time& delay) argument
374 b_transport_post_checks( tlm::tlm_generic_payload& trans, sc_core::sc_time& delay) argument
384 nb_transport_fw_pre_checks( tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay) argument
455 nb_transport_fw_post_checks( tlm::tlm_generic_payload& trans, tlm::tlm_phase& start_phase, tlm::tlm_phase& phase, sc_core::sc_time& delay, tlm::tlm_sync_enum status) argument
483 nb_transport_bw_pre_checks( tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay) argument
502 nb_transport_bw_post_checks( tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay, tlm::tlm_sync_enum status) argument
562 nb_transport_response_checks( tlm::tlm_generic_payload& trans, tlm::tlm_phase& phase, sc_core::sc_time& delay, const char* txt2, const char* txt3, const char* txt4) argument
[all...] |
| /gem5/src/dev/net/ |
| H A D | dist_iface.cc | 824 DistIface::readyToCkpt(Tick delay, Tick period) argument
898 DistIface::readyToExit(Tick delay) argument
[all...] |
| H A D | i8254xGBe.cc | 1463 Tick delay = igbe->regs.rdtr.delay() * igbe->intClock(); local
1469 Tick delay = igbe->regs.radv.idv() * igbe->intClock(); local
1914 Tick delay = igbe->regs.tidv.idv() * igbe->intClock(); local
1920 Tick delay = igbe->regs.tadv.idv() * igbe->intClock(); local
[all...] |
| H A D | Ethernet.py | 63 delay = Param.Latency('0us', "packet transmit delay") variable in class:EtherLink
72 delay = Param.Latency('0us', "packet transmit delay") variable in class:DistEtherLink
101 delay = Param.Latency('0us', "packet transmit delay") variable in class:EtherSwitch
[all...] |
| /gem5/src/arch/mips/ |
| H A D | isa.cc | 519 ISA::scheduleCP0Update(BaseCPU *cpu, Cycles delay) argument
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| /gem5/src/sim/ |
| H A D | pseudo_inst.cc | 303 m5exit(ThreadContext *tc, Tick delay) argument
313 m5fail(ThreadContext *tc, Tick delay, uint64_t code) argument
435 resetstats(ThreadContext *tc, Tick delay, Tick period) argument
449 dumpstats(ThreadContext *tc, Tick delay, Tick period) argument
463 dumpresetstats(ThreadContext *tc, Tick delay, Tick period) argument
477 m5checkpoint(ThreadContext *tc, Tick delay, Tick period) argument
[all...] |
| /gem5/src/cpu/kvm/ |
| H A D | base.cc | 183 Tick delay = sendAtomic(pkt); local
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| /gem5/src/cpu/minor/ |
| H A D | buffers.hh | 225 Cycles delay; member in class:Minor::Latch
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| /gem5/src/systemc/core/ |
| H A D | scheduler.hh | 233 delayed(const ::sc_core::sc_time &delay) argument
240 schedule(ScEvent *event, const ::sc_core::sc_time &delay) argument
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| /gem5/src/mem/cache/ |
| H A D | base.cc | 981 BaseCache::calculateTagOnlyLatency(const uint32_t delay, argument
990 BaseCache::calculateAccessLatency(const CacheBlk* blk, const uint32_t delay, argument
[all...] |
| H A D | base.hh | 1325 bool delay(Add function in class:WriteAllocator
[all...] |
| /gem5/src/arch/arm/ |
| H A D | tlb.cc | 1210 bool delay = false; local
1231 bool delay = false; local
565 translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing) argument
1036 translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing, TLB::ArmTranslationType tranType, bool functional) argument
1263 bool delay = false; local
[all...] |
| /gem5/ext/dsent/model/ |
| H A D | ElectricalModel.cc | 480 ElectricalDelay* delay = new ElectricalDelay(name_, this); local
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| /gem5/src/cpu/o3/ |
| H A D | lsq_unit.hh | 672 Cycles delay = req->handleIprRead(thread, main_pkt); local
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| H A D | cpu.hh | 143 void scheduleTickEvent(Cycles delay) argument
|